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Hardware Implementation of Video StreamingBy Jorgen Peddersen School of Information Technology and Electrical Engineering, The University of Queensland.

Submitted for the Degree of Bachelor of Engineering (Honours) in the Computer Systems Engineering StreamOctober 2001

62 Macalister Street Carina Heights, Q 4152 Tel. (07) 3398 8424 October 19, 2001 The Head School of Information Technology and Electrical Engineering The University of Queensland St Lucia, Q 4072 Dear Professor Kaplan, In accordance with the requirements of the degree of Bachelor of Engineering (Honours) in the Computer Systems Engineering stream, I present the following thesis entitled Hardware Implementation of Video Streaming. This work was performed under the supervision of Dr. Peter Sutton. I declare that the work submitted in this thesis is my own, except as acknowledged in the text and endnotes, and has not been previously submitted for a degree at the University of Queensland or any other institution. Yours sincerely,

Jorgen Peddersen

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Abstract

by Jorgen Peddersen

AbstractThis thesis describes a pure hardware implementation of simple real-time video streaming using an FPGA (Field Programmable Gate Array). Video streaming is presently performed using mainly software-based techniques on dedicated computers, as designing pure hardware solutions can be slower and harder to debug. The advantage of hardware designs is in cost, as one chip could be mass produced to perform simple video streaming tasks and used in areas such as security video cameras and other live video feeds. The implementation discussed herein uses the XSV-300 FPGA board designed by XESS Corporation to implement a real-time video streaming system. The board provides a simple video decoding chip, a network interface chip and a Xilinx XCV-300 FPGA. The FPGA is configured with code designed in VHDL that handles control of the chips involved to implement a sturdy video streaming design. that can be transmitted over the network to a destination host. The final result is a complete streaming design that does not require a PC. This design has been fully tested and performs well. Possible sources that can be streamed are TV, DVD and game consoles. At its present stage, the image quality and the network bandwidth required for the design are not a match for software-based techniques, although with some future work, the design could match these more expensive solutions in quality and speed. The resulting implementation allows streaming of any RCA or S-Video data source into UDP packets

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Acknowledgments

by Jorgen Peddersen

AcknowledgmentsThis thesis was the product of many hours of work. Long hour implementations that dont end up working can be frustrating as well as interesting to debug. The final design could not be completed without the help of many people, the author therefore wishes to thank: Dr. Peter Sutton for his guidance and patience during many 5-minute meetings. Mum and Dad for being so supportive and understanding. Ashley Partis for proofreading and for co-writing the original VHDL IP stack. James Brennan for writing the RAM code and helping with formatting. Dave Vanden Bout for being a technical support genius who can actually solve problems. Alex Song for some brilliant inspiration. Simon Leung for proofreading the thesis. And last, but not least, Sri Parameswaran who inspired me to choose Computer Systems Engineering.

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Contents

by Jorgen Peddersen

ContentsAbstract ....................................................................................................... iv Acknowledgments........................................................................................ v Contents....................................................................................................... vi List of Tables.............................................................................................viii List of Figures ............................................................................................. ix CHAPTER 1 INTRODUCTION ..................................................................... 11.1 1.2 1.3 1.4 Introduction to Video Streaming.......................................................................1 The Problem ...................................................................................................... 2 FPGA Solution ..................................................................................................2 Overview ........................................................................................................... 3

CHAPTER 2 REVIEW OF PREVIOUS WORK .............................................. 52.1 Previous Work with Board................................................................................ 5 2.1.1 Video Decoder...............................................................................................5 2.1.2 Network Stack................................................................................................5 2.2 Video Streaming Formats.................................................................................. 6 2.3 Other work.........................................................................................................7 2.3.1 Xilinx/MidStream Server ...............................................................................7 2.3.2 Axis Web Cameras and Servers ....................................................................8 2.3.3 JPEG on FPGA .............................................................................................9 2.3.4 Ethernet Intellectual Properties ....................................................................9 2.4 Summary ...........................................................................................................9

CHAPTER 3 PROBLEM DEFINITION........................................................ 113.1 General Problem.............................................................................................. 11 3.2 Video quality ...................................................................................................11 3.3 Network Issues ................................................................................................ 12 3.3.1 UDP or TCP?..............................................................................................12 3.3.2 Packet Format .............................................................................................13 3.4 PC Program .....................................................................................................14 3.5 Summary .........................................................................................................14

CHAPTER 4 HARDWARE ENVIRONMENT ............................................... 154.1 Description of Board .......................................................................................15 4.1.1 FPGA...........................................................................................................15 4.1.2 CPLD...........................................................................................................16 4.1.3 Video Decoder Chip ....................................................................................16 4.1.4 Ethernet Port ...............................................................................................17 4.1.5 SRAM...........................................................................................................17 4.1.6 Flash RAM...................................................................................................17 4.2 VHDL / Foundation ........................................................................................18 4.2.1 VHDL ..........................................................................................................18 4.2.2 The Foundation Series ................................................................................18 4.3 Summary .........................................................................................................19

CHAPTER 5 VHDL IMPLEMENTATION ................................................. 205.1 vi Video Decoding...............................................................................................20

Contents

by Jorgen Peddersen

5.1.1 Initialisation................................................................................................ 20 5.1.2 RAM Format ............................................................................................... 21 5.2 Networking ..................................................................................................... 21 5.2.1 Removal of IP Re-assembly ........................................................................ 21 5.2.2 Fixing Ethernet ........................................................................................... 21 5.2.3 ICMP........................................................................................................... 22 5.2.4 RAM Arbitration ......................................................................................... 22 5.2.5 PC SRAM Viewer........................................................................................ 23 5.3 Image Format .................................................................................................. 23 5.4 Video to Network Interface ............................................................................ 23 5.4.1 Video-In to UDP Packet Converter ............................................................ 24 5.4.2 UDP Connection Handler .......................................................................... 25 5.5 Complete FPGA Design ................................................................................. 26 5.6 CPLD Alteration