Thermodynamics in Chip Processing II

31
Thermodynamics in Chip Processing II Terry A. Ring

description

Thermodynamics in Chip Processing II. Terry A. Ring. CVD. Materials Deposited. Dielectrics SiO2, BSG Metals W, Cu, Al Semiconductors Poly silicon (doped) Barrier Layers Nitrides (TaN, TiN), Silicides (WSi 2 , TaSi 2 , CoSi, MoSi 2 ). Deposition Methods. Growth of an oxidation layer - PowerPoint PPT Presentation

Transcript of Thermodynamics in Chip Processing II

Page 1: Thermodynamics in Chip Processing II

Thermodynamics in Chip Processing II

Terry A. Ring

Page 2: Thermodynamics in Chip Processing II

CVD

Page 3: Thermodynamics in Chip Processing II

Materials Deposited• Dielectrics

– SiO2, BSG• Metals

– W, Cu, Al• Semiconductors

– Poly silicon (doped)• Barrier Layers

– Nitrides (TaN, TiN), Silicides (WSi2, TaSi2, CoSi, MoSi2)

Page 4: Thermodynamics in Chip Processing II

Deposition Methods

• Growth of an oxidation layer• Spin on Layer• Chemical Vapor Deposition (CVD)

– Heat = decomposition T of gasses– Plasma enhanced CVD (lower T process)

• Physical Deposition– Vapor Deposition– Sputtering

Page 5: Thermodynamics in Chip Processing II

Critical Issues

• Adherence of the layer• Chemical Compatibility

– Electro Migration– Inter diffusion during subsequent processing

• Strong function of Processing

• Even Deposition at all wafer locations

Page 6: Thermodynamics in Chip Processing II

CVD of Si3N4 - Implantation mask• 3 SiH2Cl2 + 4 NH3Si3N4 + 6 HCl + 6 H2

– 780C, vacuum– Carrier gas with NH3 / SiH2Cl2 >>1

• Stack of wafer into furnace– Higher temperature at exit to compensate for gas

conversion losses• Add gases• Stop after layer is thick enough

Page 7: Thermodynamics in Chip Processing II

CVD of Poly Si – Gate conductor• SiH4 Si + 2 H2

– 620C, vacuum– N2 Carrier gas with SiH4 and dopant precursor

• Stack of wafer into furnace– Higher temperature at exit to compensate for gas

conversion losses• Add gases• Stop after layer is thick enough

Page 8: Thermodynamics in Chip Processing II

CVD of SiO2 – Dielectric• Si0C2H5 +O2SiO2 + 2 H2

– 400C, vacuum– He carrier gas with vaporized(or atomized) Si0C2H5

and O2 and B(CH3)3 and/or P(CH3)3 dopants for BSG and BPSG

• Stack of wafer into furnace– Higher temperature at exit to compensate for gas

conversion losses• Add gases• Stop after layer is thick enough

Page 9: Thermodynamics in Chip Processing II

CVD of W – Metal plugs

• 3H2+WF6 W + 6HF– T>800C, vacuum– He carrier gas with WF6

– Side Reactions at lower temperatures• Oxide etching reactions• 2H2+2WF6+3SiO2 3SiF4 + 2WO2 + 2H2O• SiO2 + 4HF 2H2O +SiF4

• Stack of wafer into furnace– Higher temperature at exit to compensate for gas conversion losses

• Add gases• Stop after layer is thick enough

Page 10: Thermodynamics in Chip Processing II

Chemical Equilibrium

Page 11: Thermodynamics in Chip Processing II

CVD Reactor

• Wafers in Carriage (Quartz)

• Gasses enter• Pumped out via

vacuum system• Plug Flow Reactor

Vacuum

Page 12: Thermodynamics in Chip Processing II

CVD Reactor

• Macroscopic Analysis– Plug flow reactor

• Microscopic Analysis– Surface Reaction

• Film Growth Rate

Page 13: Thermodynamics in Chip Processing II

Macroscopic Analysis• Plug Flow Reactor (PFR)

– Like a Catalytic PFR Reactor– FAo= Reactant Molar Flow

Rate– X = conversion– rA=Reaction rate = f(CA)=kCA

– Ci=Concentration of Species, i.– Θi= Initial molar ratio for species i to

reactant, A.– νi= stoichiometeric coefficient– ε = change in number of moles

TRPC

TT

PP

XXCC

VA

Xr

dXFV

g

AoAo

o

o

iiioi

X

reactor

waferA

Aoreactor

1

)(0 '

Page 14: Thermodynamics in Chip Processing II

Combined Effects

Contours = Concentration

Page 15: Thermodynamics in Chip Processing II

Reactor Length Effects

SiH2Cl2(g) + 2 N2O(g) SiO2(s)+ 2 N2(g)+2 HCl(g)

nwafer VReactorPerWafer a

FAo0

X

X1

r'A X( )

d n X( )FAo

VReactorPerWafer a 0

X

X1

r'A X( )

d

rate X( )r'A X( )

4

Dwafer2

SiO2

MwSiO2Awafer

0 50 100 1500

2000

4000

6000

Wafer Number

Thic

knes

s(nm

)

rate X'( ) 10 min

nm

n X'( )0 0.5 10

200

400

600

Conversion

Dep

ositi

on R

ate,

Waf

er N

umbe

r

rate X( )nmmin

n X( )

X

How to solve? Higher T at exit!

Page 16: Thermodynamics in Chip Processing II

Deposition Rate over the Radius

r

wAsA

A

pABe

wA

Ae

RrCCrfiniteCConditionsBoundary

DDVAr

drCdrD

drd

r

,0,

1 "

CAs

Thiele Modulus Φ1=(2kRw/DABx)1/2

Page 17: Thermodynamics in Chip Processing II

Radial Effects

This is bad!!!

Pseudo First Order Results

CA 1

sinh 1 sinh 1

00.510.97

0.98

0.99

1

r/R.wafer

Con

cent

ratio

n

CA

00.514900

4950

5000

5050

r/R.wafer

Thic

knes

s(nm

)rate 1 CA 10 min

nm

x 0.5

Page 18: Thermodynamics in Chip Processing II

Combined Length and Radial Effects

00.512400

2600

2800

3000

3200

3400

3600

r/R.wafer

Thic

knes

s

Rate 10 10 minnm

Rate 20 10 min

nm

Wafer 20

Wafer 10

Page 19: Thermodynamics in Chip Processing II

CVD Reactor

• External Convective Diffusion– Either reactants or products

• Internal Diffusion in Wafer Stack– Either reactants or products

• Adsorption• Surface Reaction• Desorption

Page 20: Thermodynamics in Chip Processing II

Microscopic Analysis -Reaction Steps

• Adsorption – A(g)+SA*S– rAD=kAD (PACv-CA*S/KAD)

• Surface Reaction-1 – A*S+SS*S + C*S– rS=kS(CvCA*S - Cv CC*S/KS)

• Surface Reaction-2– A*S+B*SS*S+C*S+P(g)– rS=kS(CA*SCB*S - Cv CC*SPP/KS)

• Desorption: C*S<----> C(g) +S– rD=kD(CC*S-PCCv/KD)

• Any can be rate determining! Others in Equilib.• Write in terms of gas pressures, total site conc.

Page 21: Thermodynamics in Chip Processing II

CMP

Page 22: Thermodynamics in Chip Processing II

What is CMP?

• Polishing of Layer to Remove a Specific Material, e.g. Metal, dielectric

• Planarization of IC Surface Topology

Page 23: Thermodynamics in Chip Processing II

Scratching Cases

• Rolling Indenter• Line Scratches

– Copper Only– Copper & ILD

• Chatter Scratches• Uncovery of Pores

120 microns

Page 24: Thermodynamics in Chip Processing II

CMP Tooling• Rotating Multi-head

Wafer Carriage• Rotating Pad• Wafer Rests on Film of

Slurry • Velocity= -

(WtRcc)–[Rh(Wh –Wt)] • when Wh=Wt

Velocity = const.

Page 25: Thermodynamics in Chip Processing II

Slurry

• Aqueous Chemical Mixture– Material to be removed is soluble in liquid– Material to be removed reacts to form an oxide layer

which is abraded by abrasive• Abrasive

– 5-20% wgt of ~200±50nm particles• Narrow PSD, high purity(<100ppm)• Fumed particle = fractal aggregates of spherical primary

particles (15-30nm)

Page 26: Thermodynamics in Chip Processing II

Pad Properties

• Rodel Suba IV• Polyurethane

– tough polymer• Hardness = 55

– Fiber Pile• Specific Gravity = 0.3• Compressibility=16%• rms Roughness = 30μm

– Conditioned

Page 27: Thermodynamics in Chip Processing II

Heuristic Understanding of CMP

• Preston Equation(Preston, F., J. Soc. Glass Technol., 11,247,(1927).

– Removal Rate = Kp*V*P• V = Velocity, P = pressure and Kp is the proportionality constant.

Page 28: Thermodynamics in Chip Processing II

CMP Pad Modeling• Pad Mechanical Model - Planar Pad

• Warnock,J.,J. Electrochemical Soc.138(8)2398-402(1991).

• Does not account for Pad Microstructure

Page 29: Thermodynamics in Chip Processing II

CMP Modeling

• Numerical Model of Flow under Wafer– 3D-Runnels, S.R. and Eyman, L.M., J. Electrochemical Soc.

141,1698(1994).

– 2-D-Sundararajan, S., Thakurta, D.G., Schwendeman, D.W., Muraraka, S.P. and Gill, W.N., J. Electrochemical Soc. 146(2),761-766(1999).

PadU

Pappliedy

x

h(x)

Wafer

Slurry

D

Page 30: Thermodynamics in Chip Processing II

Copper Dissolution

• Solution Chemistry– Must Dissolve Surface

Slowly without Pitting• Supersaturation

Page 31: Thermodynamics in Chip Processing II

Oxidation of Metal Causes Stress

• Stress, i = E i (P-B i – 1)/(1 - i)• P-Bi is the Pilling-Bedworth ratio for the oxide