The SPIN & DSPIN networks on chip - lip6.fr file13 Mai 2005 / Journée Informatique Embarquée : Du...

13 Mai 2005 / Journée Informatique Embarquée : Du matériel au Logiciel

The SPIN & DSPIN networks on chip

Alain Greiner


Outline

Introduction

The SPIN micro-network architecture

The SPIN32 evaluation chip

The DSPIN micro-network architecture

DSPIN performances

Conclusion


Multiprocessors architectures

I0 I1 I2

T0 T1 T2 T3

Interconnect

VCI

VCI

Targets

Initiators

Request

Response

I3


Shared bus

I0 I1 I2

T0 T1 T2 T3

I3

Complexity : O( M + T)

Bandwidth : O(1)

=> non scalable


Cross-bar

I1 I2

T0 T1 T2 T3

I3

Complexity : O( M * T)

Bandwidth : O(max (M,T))

=> non scalable

I0


Multi-stage network

M0 M1 M2

T0 T1 T2 T3

M2

Complexity : O(log( M + T))

Bandwidth : O(max (M,T))

=> scalable

Router Router

Router Router


Outline

Introduction




DSPIN performances

Conclusion


SPIN micro-network architecture

SPIN network

• multi-level Fat-Tree topology

• packet switching network

• wormhole routing

• point to point bidirectional links

• credit-based flow control

• adaptative routing


Packet Switching :

ν No circuit reservation

ν Atomic transaction = packet

Wormhole routing:

ν routers forward packets ASAP

ν packets span several routers

Multistage Packet Switched Networks

target

source

router

router

router


Adaptive routing

SPIN network

• Upward routing is adaptive

• Downward routing is deterministic

A

B


Performance evaluation

© Simulation of multi-master / multi-target architectures

running a synthetic workload.

© All components are described in the SoCLib environment as

cycle-true bit-true models for SystemC,.

target

vci

target1

nativevci

target

vci

target0

nativevci

init

vci

init1

nativevci

init

vci

init0

nativevci

Communication Architecture

wrappers

cores


Latency / Load

ν The variable parameter is the offered load

ν 32 cores : 16 initiators and 16 targets.

ν Random traffic : The 16 initiators send randomly

read request (8 words = a cache line) to the 16

targets (for both architectures).

ν Measure the average latency for a transaction.


SPIN / PI-BUS comparison

- saturation threshold = 30%

-Minimal latency = 30 cycles


Outline

Introduction




DSPIN performances

Conclusion


Evaluation chip : SPIN32

main goals :

Provide a silicon proof of the SPIN concept in 0.13µ CMOS

Confirm the simulation results : latency & throughput

Measure the maximum clock frequency

Measure the reliability under several stress environments

Measure the power consumption


A 32 ports SPIN network


Evaluation chip architecture

The 32 ports SPIN micro-network (spin32 macrocell) issurrounded by a dedicated instrumentation logic.

This evaluation chip has been fabricated by ST Microelectronicsin 0.13 micron CMOS process.


RSPIN router layout

© Symbolic layout for

process portability

© Area is 0.24 mm2 in

CMOS 0.13µ


SPIN32 macrocell layout

© Symbolic layout for process portability

© Inter-routers wires are routed over cells in metal 4, 5 and 6

© 1 390 464 transistors

© 4.6 mm2 in STMicroelectronics 0.13 µ with 6 metal layers


Outline

Introduction




DSPIN performances

Conclusion


SPIN strengths

© For shared memory architectures, the SPIN micro-network with

VCI / SPIN wrappers provides the same service as a classical

“system bus” (making possible IP reuse).

© SPIN demonstrated a truly scalable bandwidth.

© A 32 ports SPIN can be physically implemented in 4.6 mm2 for a0.13 µ CMOS process, with all wires routed on top of the routers.


SPIN weaknesses

Adaptive routing improve the saturation theshold…,

but destroys the « in order delivery » property.

The fat-tree topology has a minimal diameter…,

but is not very flexible.

The SPIN32 « hard macrocell » is highly opimized…,

but it is not synthesisable.

The centralized approach for the SPIN network is

not compatible with the GALS (Globally Asynchronous,Locally synchronous) approach.


DSPIN / SPIN

What is conserved

© Packet switching

© Wormhole routing

© Full duplex physical links

© VCI interface

© Shared address space

What is different

© Mesh topology

© Distributed

© Asynchronous

© Deterministic routing

© Synthesisable

© Clustering


DSPIN : Mesh Topology

R R

R

R

R

R

R

R

R

Sub

System

CK7 CK8 CK9

CK3CK2CK1

CK6CK5CK4

Sub

System

Sub

System

Sub

System

Sub

System

Sub

System

Sub

System

Sub

System

Sub

System


Deterministic Routing

DSPIN uses the X-first routing algorithm, that gives themicro-network the « in-order delivery » property.

0,3

0,2

0,1

0,0

1,3

1,2

1,1

1,0

2,3

2,2

2,1

2,0

3,3

3,2

3,1

3,0

if X > Xloc -> EAST

If X < Xloc -> WEST

If X = Xloc

if Y > Yloc -> NORTH

if Y < Yloc -> SOUTH

if Y = Yloc -> LOCAL


DSPIN : Clock Boundaries

Subsystem iSubsystem i+1

CK CK ’


Distributed DSPIN Router

CK CK’CK’’


Separated Requests & Responses

VCI INITIATOR VCI TARGET

Request

Router

Response

Router

VCI / DSPIN

INITIATOR WRAPPER

VCI / DSPIN

TARGET WRAPPER

REQ

REQREQ

REQ

RSPRSP

RSPRSPVCI


Interleaved Request & Response networks

R R

R

R

R

R

R

R

R

R R

R

R

R

R

R

R

R

In order to prevent

dead-locks, DSPIN uses

two fully independant

networks for requests

and responses


Two level hierarchical routing

I0.0

VCI / VCI

Local Interconnect

VCI

DSPIN network

VCI / VCI

Local Interconnect

I0.1 T0.0 T0.1 In.0 In.1 Tn.0 Tn.1

VCI

Sub-system 0 Sub-system n


Outline

Introduction




DSPIN performances

Conclusion


DSPIN status

© SystemC Cycle-Accurate and Bit-Accurate simulation modelshave been written for the 3 DSPIN components :

ν DSPIN router

ν DSPIN/VCI initiator wrapper

ν DSPIN/VCI target wrapper

Those SystemC models have been validated in a 16 processorsintegrated network.

© VHDL synthesizable models have been designed andsynthesized, using SYNOPSYS and the Alliance standard cellslibrary. The footprint of the DSPIN router is two times smaller thanthe footprint of the SPIN router.


The simulation plat-form

R R

R

R

R

R

R

R

R

R

R

R

RR R R

R R

R

R

R

R

R

R

R

R

R

R

RR R R

• 16 nodes architecture

• Each node contains

1 processor and 1 RAM

• Each processor sends

randomly distributed

read request to all RAMS

• Each request is 8 words

(a cache line)


Saturation threshold & minimal latency


Conclusions

© The DSPIN architecture, as the SPIN architecture, providesthe system designer a truly scalable bandwidth.

© The DSPIN architecture is suited to the GALS (GloballySynchronous / Locally Synchronous) approach.

© The DSPIN architecture solves the problem of timingclosure due to long wires, that is critical in DSM processes.

© The DSPIN performances (bandwidth and latency) areequivalent to the SPIN performances, with a smaller footprint.

© The DSPIN components (routers and wrappers) aresynthesizable, which is mandatory for an industrial product.

© All SystemC SPIN &DSPIN simulation models will beintegrated in the SOCLIB modeling and simulation platform.

© A physical implementation of the DSPIN architecture isplanned in 2005 at CROLLES (90 nanometer process), incooperation with the group of J.P Schoelkopf.

The SPIN & DSPIN networks on chip - lip6.fr file13 Mai 2005 / Journée Informatique Embarquée : Du...

Documents

Transcript of The SPIN & DSPIN networks on chip - lip6.fr file13 Mai 2005 / Journée Informatique Embarquée : Du...