The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement...

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The Spartan 3e FPGA

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Transcript of The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement...

Page 1: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

The Spartan 3e FPGA

Page 2: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

The Spartan 3e FPGA

What’s inside the chip? How does it implement random logic? What other features can you use?

What do all these things mean? LUT, Slice, BRAM, DCM, IOB, CLB...

Two important documents (linked to the class web site) Spartan3e Family Complete Data Sheet Spartan3e User Guide

Page 3: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s on the chip?

Page 4: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s on the chip?

• CLB (Configurable Logic Blocks)

• Logic and flip flops• 1,164 CLBs on our chip• Each CLB is 4 Slices• 500k total “system gates”

Page 5: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s on the chip?

• IOB (Input Output Blocks)• Communicate off chip• Our chip has 232 total pins in a 320 BGA package

Page 6: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s on the chip?

• BRAM (Block RAM)• On-chip SRAM• 18k bits per block• 20 blocks on our chip

Page 7: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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What’s on the chip?

• Multiplier• Custom 18x18 multiplier• One per RAM block...

Page 8: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s on the chip?

• DCM (Digital Clock Manager)• Clock generation and distribution• Four on our chip

Page 9: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s on the chip?

• Programmable Interconnect• Connect everything together• Perhaps the most critical part of the chip!

Page 10: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

CLB: Configurable Logic Block

4 “Slices” per CLB The slices work together to make logic, flip flops,

distributed RAM, or shift registers Connected to other CLBs through Switch Matrix

Page 11: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Left and Right Slices

SRL16 = 16-bit shift register RAM16 = 16-bit RAM (16x1 bit memory) LUT4 = four-bit lookup table (16x1 bit memory) SLICEM = slice that can be memory or logic SLICEL = slice that can only be logic

Page 12: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

What’s Really in a

Slice?

Page 13: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

LUT 4 – Basic Building Block

Page 14: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

LUT 4 – Basic Building Block

Page 15: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Slice Muxes extend LUT4

Page 16: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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One CLB – up to LUT7

Page 17: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Top Half of a SliceM (left)

Page 18: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Top Half of a SliceM (left)

Page 19: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Logic-only (combinational)

Page 20: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Logic + register (sequential)

Page 21: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Just register

Page 22: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Fast Carry Path (arithmetic)

Page 23: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Fast Carry Path (arithmetic)

Page 24: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Fast Carry Path (arithmetic)

Page 25: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Mapping to CLBs

Each LUT can go through a flip flop So, these circuits map to the same number of Slices

Page 26: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Mapping to CLBs

How about these?

Page 27: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Mapping to CLBs

How about these?

Page 28: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

CLB Summary

Each CLB = 4 slices Each slice contains

2 LUT-4LUT can be random logic, or 16x1bit RAM or SR

2 flip flop MUXs Carry logic

ISE reports how many slices you use among lots of other things...

Page 29: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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IO Blocks

Connections to the outside world Each pin can be

configured a large number of ways

Different signaling voltages and drive currents

Page 30: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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IO Blocks

Connections to the outside world Each pin can be

configured a large number of ways

Different signaling voltages and drive currents

NOTE! No 5v!

Page 31: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Inside an IOB

Page 32: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Interconnect

Actually the most important part of the FPGA! Consumes the most area on the die Consumes the most power on the die In most cases, wires limit the performance

But, hardly mentioned in the datasheet People are more impressed with logic

Page 33: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Interconnect

RAM-programmable switches 2,270,208 bits of configuration RAM! Compare to 368,640 total bits of Block RAM or 74,752 total bits of Distributed RAM (LUTs)

Hierarchical organization Many fast, short wires with small drive Fewer longer wires with high drive LOTS of work goes into picking just the right

mix!

Page 34: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Interconnect

Page 35: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Interconnect

Four typesof wires

Page 36: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Clock Routing

Routed on a separate dedicated network Another reason to avoid gated clocks

Recursive “Fish bone”network that minimizesclock skew

Clocks come fromoff-chip, or froma DCM (dig. Clk man)

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Spartan XC3E500S

Page 38: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Block RAM

We’ve seen details of these already…

Page 39: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Behavioral Template

Dual-port1 R/W1 R

Page 40: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Structural Template

Page 41: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Structural Template

Page 42: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Distributed RAM

Page 43: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Distributed RAM

Page 44: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Distributed RAM

Dual-Port Distributed RAM

Page 45: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Distributed RAM

Dual-Port Distributed RAM

Page 46: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Digital Clock Manager (DCM)

Page 47: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Digital Clock Manager (DCM)

Page 48: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Digital Clock Manager (DCM)

Page 49: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Clock Skew

Page 50: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Clock Skew

Page 51: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Multipliers

Page 52: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Multipliers

Page 53: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Synthesis Output (mips example)

Page 54: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

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Synthesis Output (mips example)

Page 55: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Synthesis Output (mips example)

Page 56: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Synthesis Output (mips example)

Page 57: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Synthesis Output (mips example)

Page 58: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 59: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 60: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 61: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 62: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 63: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 64: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Implement Output (mips example)

Page 65: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

Conclusion

FPGAs are complex beasts! Made to be very general and flexible

ASIC vs. FPGA? Rule of thumb, FPGA about 5 times slower

clock than ASIC FPGAs consume more power FPGAs are bigger for the same function ASICs are much more expensive to develop

NRE – Non-Recurring Engineering

Page 66: The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA What’s inside the chip? How does it implement random logic? What other features can you use? What.

CS/EE 3710

ASIC vs. FPGA


Spartan 3e Labview Fpga

Spartan 3e Labview Fpga

Spartan-3E FPGA Family Data Sheet (DS312)...Spartan-3E FPGA Family: Introduction and Ordering Information DS312 (v4.2) December 14, 2018 Product Specification 4 Configuration Spartan-3E

Spartan-3E FPGA Family Data Sheet (DS312)...Spartan-3E FPGA Family: Introduction and Ordering Information DS312 (v4.2) December 14, 2018 Product Specification 4 Configuration Spartan-3E

Xilinx Spartan-3E

Xilinx Spartan-3E

FPGA and Spartan 3E Guide

FPGA and Spartan 3E Guide

Spartan-3 Generation Configuration User Guide (UG332) · R Spartan-3 Generation Configuration User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG332 (v1.7)

Spartan-3 Generation Configuration User Guide (UG332) · R Spartan-3 Generation Configuration User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG332 (v1.7)

Spartan-3E Display Development Kit

Spartan-3E Display Development Kit

Beginner’s Guide to Xilinx Spartan-3E FPGA Starter Kit Board

Beginner’s Guide to Xilinx Spartan-3E FPGA Starter Kit Board

Getting Started with LabVIEW FPGA and the Spartan-3E ......and the Spartan-3E Starter Board Contents ... Figure 1: USB B Connector to Spartan-3E Starter Board 2. Connect the USB A

Getting Started with LabVIEW FPGA and the Spartan-3E ......and the Spartan-3E Starter Board Contents ... Figure 1: USB B Connector to Spartan-3E Starter Board 2. Connect the USB A

Getting Started with LabVIEW FPGA and the Spartan-3E ...download.ni.com/evaluation/academic/getting_started_spartan.pdf · and the Spartan-3E Starter Board ... demonstration of how

Getting Started with LabVIEW FPGA and the Spartan-3E ...download.ni.com/evaluation/academic/getting_started_spartan.pdf · and the Spartan-3E Starter Board ... demonstration of how

Spartan-6 FPGA Configuration

Spartan-6 FPGA Configuration

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide · Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Xilinx is disclosing this Document and Intellectual

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide · Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Xilinx is disclosing this Document and Intellectual

Introducing the Spartan 3E FPGA and VHDL · PDF fileIntroducing the Spartan 3E FPGA and VHDL ii REVISION HISTORY NUMBER DATE DESCRIPTION NAME 0.42 15 September 2012 Includes another

Introducing the Spartan 3E FPGA and VHDL · PDF fileIntroducing the Spartan 3E FPGA and VHDL ii REVISION HISTORY NUMBER DATE DESCRIPTION NAME 0.42 15 September 2012 Includes another

Spartan 3e Manual

Spartan 3e Manual

Spartan-6 FPGA Memory Interface Solutions - Xilinx and any other FPGA resources required to implement the ... implementing a Spartan-6 FPGA memory ... Spartan-6 FPGA Memory Interface

Spartan-6 FPGA Memory Interface Solutions - Xilinx and any other FPGA resources required to implement the ... implementing a Spartan-6 FPGA memory ... Spartan-6 FPGA Memory Interface

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

Trenz Electronic GmbH Spartan-3E FPGA … · Spartan-3E FPGA Industrial Micromodule User Manual The ordering numbers of the connector receptacles are given in Table 1. supplier header

Trenz Electronic GmbH Spartan-3E FPGA … · Spartan-3E FPGA Industrial Micromodule User Manual The ordering numbers of the connector receptacles are given in Table 1. supplier header

Introduction to the Xilinx Spartan-3E Starter Kit Spartan... · Xilinx Spartan-3E Starter Kit Spartan-3E Starter Kit Overview •A full-featured Spartan-3E FPGA development board

Introduction to the Xilinx Spartan-3E Starter Kit Spartan... · Xilinx Spartan-3E Starter Kit Spartan-3E Starter Kit Overview •A full-featured Spartan-3E FPGA development board

Lab 1: Implementing a Boolean function in LabVIEW FPGA on the Xilinx SPARTAN-3E Board

Lab 1: Implementing a Boolean function in LabVIEW FPGA on the Xilinx SPARTAN-3E Board

Module 3: Spartan-3E FPGA Family: Introduction DC and … · 2019. 10. 13. · The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount

Module 3: Spartan-3E FPGA Family: Introduction DC and … · 2019. 10. 13. · The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount

Module 3: Spartan-3E FPGA Family: Introduction DC … DS312-1 (v3.8) August 26, 2009 Product Specification R Architectural Overview The Spartan-3E family architecture consists of five

Module 3: Spartan-3E FPGA Family: Introduction DC … DS312-1 (v3.8) August 26, 2009 Product Specification R Architectural Overview The Spartan-3E family architecture consists of five