The SLAC KPiX Chip for ILC GEM-Digital Hadron Calorimetry

download The SLAC KPiX Chip for ILC GEM-Digital Hadron Calorimetry

If you can't read please download the document

description

The SLAC KPiX Chip for ILC GEM-Digital Hadron Calorimetry. Andy White for the GEM-DHCAL Group (UTA – UW – CNU). With many thanks to SLAC colleagues: M. Breidenbach, G. Haller, D. Freytag, R. Herbst. RD51, Paris, October 2008. -2100V. ∆V ~400V. ∆V ~400V. 0V. - PowerPoint PPT Presentation

Transcript of The SLAC KPiX Chip for ILC GEM-Digital Hadron Calorimetry

  • The SLAC KPiX Chip for ILC GEM-Digital Hadron CalorimetryAndy Whitefor the GEM-DHCAL Group(UTA UW CNU)RD51, Paris, October 2008With many thanks to SLAC colleagues:M. Breidenbach, G. Haller, D. Freytag, R. Herbst

  • GEM/DHCAL active layer concept

  • KPiX chipOne channel of 1024DHCAL anode padDynamic gain selectEvent triggerLeakage current subtractioncalibrationStorage until end of train.Pipeline depth presently is 413 bit A/DKPiX/GEM/DHCAL

    1

    Reset

    Range Logic

    Control LogicPulses to Timing Latch, Range Latch, and Event Counter

    Reset

    Track

    Track

    Si-W Pixel Analog Section

    1 of 1024 pixels

    Range Register

    Analog 1

    Analog 4

    Range Threshold

    Reset

    Simplified Timing:

    There are ~ 3000 bunches separated by ~300 ns in a train, and trains are separated by ~200 ms.

    Say a signal above event threshold happens at bunch n and time T0.The Event discriminator triggers in ~100 ns and removes resets and strobes the Timing Latch (12 bit), range latch (1 bit) and Event Counter (5 bits).The Range discriminator triggers in ~100 ns if the signal exceeds the Range Threshold.When the glitch from the Range switch has had time to settle, Track connects the sample capacitor to the amplifier output. (~150 ns)The Track signal opens the switch isolating the sample capacitor at T0 + 1 micro s. At this time, the amplitude of the signal at T0 is held on the Sample Capacitor .Reset is asserted (synched to the bunch clock) . Note that the second capacitor is reset at startup and following an event, while the high gain (small) capacitor is reset each bunch crossing (except while processing an event)The system is ready for another signal in ~1.2 microsec.After the bunch train, the capacitor charge is measured by a Wilkinson converter.

    Event Threshold

    Wilkinson scaler and logic

    Leakage Current Servo

    ...

    Bunch Clock

    Latch (4x)

    Low Gain

    I Source

    High Gain (default)

    Cal Strobe

    Cal Dac

  • GEM-DHCAL/KPiX boards with Interface and FPGA boards

  • Redesigned chamber all fishing line spacer KPiX anode board with extra electronics protection Better/more direct gas flow through ionization gap No large dielectric spacer(s) previously killed signal

  • GEM chamber with KPiX v4 early 2008

  • Channel #Channel #Channel #fCGEM + KPiX long source run at SLAC

  • Away from the sourceAway from the sourceRight under the sourceRight under the sourceGEM + KPiX response in lab at SLAC

  • First results from new GEM chamber + KPiXfC scale

  • UTA 75hrLong run at SLAC

  • GEM/DHCAL with KPiX readout Due to the synchronous design of KPiX, data taking efficiency was low with (asynchronous) source. KPiX v7 offers new timing flexibility. Waiting for v7 -> study pedestal subtraction to (eventually) extract MIP distribution Also study channel variation/stability of calibration and pedestal feedback to SLAC KPiX developers.

  • Calibration studies with KPiX v4Goals: - understand relation between pedestal distribution and zero-charge injected distribution. - investigate stability of gain, response to injected charge, pedestals -> subtraction of noise to yield MIP signals. - understand factors that influence gain etc. (channel to channel, single channel/environment, long-term fluctuations - ultimately develop calibration procedure (how often, length of calibration/pedestal runs,)

  • KPiX injected charge calibrationInternal capacitor charged via DAC, readout through data path -> measure gain from slope -> measure zero-injected charge response, Y-int

  • Initial Calibration Analysis ExampleTwo Calib Data Sets19 hr run starting in evening weekend 6/2824 hr run starting in morning - work week 7/01Each Channels Pedestal Mean, Sigma; Gain, and Y-Intercept verses Run# (on order of an hour) is graphed for each channel and fit with a straight line.Work of UTA Masters student Jacob Smith

  • NormalDoublePedSigGainY-int16191817One channel KPiX v4

  • NormalDoublePedSigGainY-int19hrWeekend run

  • NormalDoublePedSigGainY-int24hrWeekday run

  • NormalDoublePedSigGainY-intApril - June

  • Issue with KPiX v4 triggering mode: forced trigger (software) mode was used no fixed time relation between arrival of electron from source and internal timing of KPiX.- we suspect that a reset is responsible for incomplete integration of the charge this would distort MIP (Landau) distribution by lowering ADC valuesGEM/KPiX source data taking- also noise peak wider with data than for pedestal runs -> working on understanding this effect.

  • Next step: KPiX v7KPiX is a synchronous device tied to ILC beam timing-> problem being efficient in an asynchronous environment e.g. MTBF , cosmics, or source(s).-> KPiX v4 was only 5% efficient for source or asynchronous beam.-> KPiX v7 allows more flexibility in timing adjustments via slowing down the master clock - should provide data taking efficiencies in 40-50% range in an asynchronous environment, and has new reset scheme. First version of v7 now at UTA, plus we have a new anode board designed to work with it. Initial tests -> calibration with injected charge (internal) -> results.

  • New KPiX Board for v71. The KPiX chip is located just next to the PAD area.2. 310 x 310 mm. with 8 x 8cm. pad area at the center with 0.2mm. Gaps between pads.3. Surface mount parts (connectors...). Nothing will be on the PAD side.4. All the holes filled for gas tightness.5. Leaving about 1" space on the edges for sealing.... 6. KPiX board thicker, flatter

  • KPiX v7 board layout

  • KPiX v7 first calibration results

  • KPiX v7 chamber plans New v7 chamber works well stable (no trips) over several weeks so far. Verify new software for v7 Operate v7 with new GEM chamber (in progress) Complete calibration/understand behavior with v7 Work with SLAC to achieve 40-50% efficiency in cosmic and source data taking. Work at UTA and SLAC. Take beam data at MTBF, CERN?

  • Future Plans for GEM/DHCAL Complete GEM chamber studies with v7 Construct ~1m x 0.3m chamber Construct ~ 1m2 plane(s). Issue with foil supplier: 3M closed plant in Missouri Have obtained quotes from CERN for 99cm x 32cm foils. Alternative: Thick-GEM chamber if large areas are viable LCDRD Supplement, 2nd year minimal amount to purchase foils + limited postdoc support. Attention to 1m2 plane design walls/thickness, gas supply, KPiX readout >>>

  • Future Plans for GEM/DHCAL Next generation KPiX (2561024 channels) Note: started out to test GEM with both KPiX and DCAL chips we would like to continue thisalso perhaps use alternative readout from Europe We will have a visitor joining our group in November much experience with detectors/readout We also will be hiring a postdoc 50% ILC R&D, 50% ATLAS