The Silicon Laboratories C8051F020

103
ECE/CS-352: Embedded Microcontroller Systems The Silicon Laboratories C8051F020 Enhanced 8051

description

The Silicon Laboratories C8051F020. Enhanced 8051. Overview. Timing – system clocks CPU Execution timing Software Delays Timers On-chip “external” RAM A/D and D/A Conversion Temperature Sensor Additional Timers and Interrupts. SFRs for Subsystems. Control registers: - PowerPoint PPT Presentation

Transcript of The Silicon Laboratories C8051F020

Page 2: The Silicon Laboratories C8051F020

ECE/CS-352: Embedded Microcontroller Systems

Overview

• Timing – system clocks

• CPU Execution timing

• Software Delays

• Timers

• On-chip “external” RAM

• A/D and D/A Conversion

• Temperature Sensor

• Additional Timers and Interrupts

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SFRs for Subsystems

• Control registers:– XXXCN (WDTCN, ADC0CN, DAC0CN, TMR3CN)

• Configuration registers:– XXXCF (ADC0CF, AMX0CF, EMI0CF)

• Data registers for subsystems:– ADC0H, ADC0L, DAC0H, DAC0L

• Many others.....

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System Clocks

• Internal clock oscillator– default at reset– 2 MHz default

frequency– configured by SFR

OSCICN

• External oscillator installed on board– 22.1184 MHz – configured by SFR

OSCXCN

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Internal Osc ConfigurationOSCICN

Missing clock detector enable

Internal Osc. frequency ready system clock

select0 = internal1 = external(internal bydefault)

Internal Osc. enable(enabled by default)

Internal Osc. freq. control bits00 – 2MHz01 – 4 MHz10 – 8 MHz11 – 16 MHz

Default Sysclk f = 2 MHzT = 0.5 s

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External Osc. ConfigurationOSCXCN

Crystal Osc. valid flag

External Osc. mode bits 00x: Off. XTAL1 pin is grounded internally.

010: System Clock from External CMOS Clock on XTAL1 pin.

011: System Clock from External CMOS Clock on XTAL1 pin divided by 2.

10x: RC/C Oscillator Mode with divide by 2 stage.

110: Crystal Oscillator Mode

111: Crystal Oscillator Mode with divide by 2 stage.

•External Osc. freq. control bits•Depends on frequency range of operation

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To use 22.1184 MHz external oscillator

110: Crystal Oscillator Mode 111: f > 6.7 MHz

Step 1. Enable the external oscillator.Step 2. Wait at least 1 ms.Step 3. Poll for XTLVLD => ‘1’.Step 4. Switch the system clock to the external oscillator.

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Instruction Timing

• C8051F020 – Pipelined architecture

• Machine cycle = clock cycle

• Most instructions take 1 or 2 clock cycles

• Total of 109 instructions

• Summary of instruction timing:

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Delay Loops

T = 45.211 nsExecution time = (acc) x (180.8 ns)

djnz acc, $ ; 3 cycles if no jump, ; 4 cycles if jump

# cycles (acc) x 4 Execution time = # cycles x (T)

With 22.1184 MHz External Osc.

T = 0.5 sExecution time = (acc) x (2 s)

With 2 MHz Internal Osc.

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Sample Configuration

• Use 22.1184 MHz external oscillatorMain: mov WDTCN, #0deh ; disable watchdog timer mov WDTCN, #0adh

mov OSCXCN, #67h ; enable external crystal ; oscillator at 22.1184MHz clr A ; wait at least 1ms djnz acc, $ ; wait ~510us (255 x 4 x 0.5us) = 510 us) djnz acc, $ ; wait ~510us

osc_wait: ; poll for XTLVLD-->1 mov a, OSCXCN jnb acc.7, osc_wait

orl OSCICN, #08h ; select external oscillator as ; system clock source

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Timers

• Original 8051 has 2 Timers, T0 and T1• Can think of timers as binary counters• Clock is derived from system clock (frequency is

configurable)• Timer registers can be read via mov instructions• Events (interrupts or flag bits set) occur when

timers overflow • Can be used to create waveforms, measure time

intervals, set frequency of events, etc.

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C8051F020 Timers

Size of timers can be configured.• Timers can count from arbitrary initial value with the

“Auto-reload” feature.• “Capture” allows the timer to be “frozen” when an event

occurs.• Timers 2 and 4 can be used to set baud rate for uarts.

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Timer Clock Sources

CKCON: Clock Control Register

Timer clock selects

0 = system clock 12 (for compatibility with original 8051, and for slow stuff)

1 = system clock

Timer4

Timer0

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Configuring Timers

• TCON and TMOD used to configure Timer0 and Timer1

TCON: Timer Control Register

Timer 1 Overflow Flag

Timer 1 run control0 = disable Timer 11 = enable Timer 1

These deal with external interrupts

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Configuring TimersTMOD: Timer Mode Register

Timer 1 Timer 0GATE1: 0 = timer enabled with TR1 only

1 = timer enabled only when TR1=1 and \INT=1

C/T1: 0 = timer incremented by clock input 1 = counter incremented by edge on external T1 pin

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Using Timers For Periodic EventsUsing Polling

• Set mode to be timer – use appropriate clock and timer size

• In main program – Check for overflow flag (polling)– When overflow flag occurs

• Do event• Reset timer overflow flag• Reset timer initial value (unless using auto-reload or

initial value of 0 is OK)• Continue checking

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Using Timers For Periodic EventsUsing Interrupts

• Set mode to be timer, use appropriate clock and timer size

• Set timer to interrupt on overflow

• In Interrupt Service Routine– Do event– Reset interrupt flag– Reset timer to initial value (unless using auto-

reload)– Return from interrupt

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Using Timers as Counter

• Set mode to be counter, with appropriate size (8, 13 or 16 bits)

• Initialize counter to zero

• Enable counter

• Counter can be read and reset by main program.

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Using Timers to Measure Time

Using Timers:– Configure timers with mode 0 or 1 (13 or 16-bit

timer) and desired system clock. – In main program, wait for initial event.– Start the timer.  – Each time the timer overflows, a register should

be incremented using an interrupt service routine.

– When the second event occurs, disable the interrupts and the timer in the main program.

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Using External RAM

• Used to hold large data sets

• Accessed with movx instruction

– MOVX A, @Ri Move external data to A register

– MOVX @Ri, A Move A to external data (8-bit address)

– MOVX A, @DPTR Move external data (16-bit address) to A

– MOVX @DPTR, A Move A to external data (16-bit address)

• Remember that the data pointer can be incremented, but not decremented.

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Digital to Analog Conversion

• Two general types– Weighted D/A Converter (4-bit example)

register

digital input4

Q3Q2Q1Q0

R

2R

4R

8R

Rout analog output

1111

1000

0100

0000

1100

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Digital to Analog Conversion

Ladder D/A Converter (4-bit example)

register

digital input4

Q3

Q2

Q1

Q0

2R

2R

2R

2R

R

analog output

1111

1000

0100

0000

1100R

R

2R

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DAC0CN: DAC Control Register

DAC Enable0 = disable1 = enable

DAC Mode00: DAC updates occur on a write to DAC0H.01: DAC updates occur on Timer 3 overflow.10: DAC updates occur on Timer 4 overflow.11: DAC updates occur on Timer 2 overflow.

DAC Output Scaling/Justification

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Conversion Synchronization

• Use Timer overflows to synchronize DAC when it is important to have smooth output waveforms.

Using software loops which may be interrupted.

Using timer overflows.

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Output Voltage Swing

Example: Vref = 3V

3V

4095 levelsRange = 0 to (3V-732.6 V)

0 to 2.999267= 732.6

Vlevel

0 Vref – 1 lsb

000h FFFh(4095)

analog range

digital range

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Configuring VREFDREF0CN

BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC or DAC).

0: Internal Bias Generator Off.1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.

REFBE: Internal Reference Buffer Enable Bit.0: Internal Reference Buffer Off.1: Internal Reference Buffer On.

REF0CN

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Analog to Digital Conversion

V

time

A/DConverter

GND

AnalogDigital (8-bit)

time

0111

1110

1011

0000

1011

1110

0111

1100

0111

1110

1111

1110

1110

1110

1111

1110

0111

0000

Digital value

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Analog to Digital Conversion

Basic idea is to compare analog input to value produced by DAC and use logic to adjust the digital output so that it properly represents the analog input.

A/D converters classified based on what logic is used.

DAC

n

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Successive Approximation

DAC

Starting at MSB, set each bit to 1, and if it trips the comparator, reset to 0. If not, hold at 1. Repeat for all bits. 100000000000110000000000101000000000.....

analog

100000000000

110000000000

101000000000

Example... first 3 bits

n

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Analog to Digital ConversionPrecision

A/DConverter

nAnalog Digital

Examples:Analog Range: 0V-4VDigital: n=4

Digital0000000100100011010001010110011110001001101010111100110111101111

Analog0.000.250.500.751.001.251.501.752.002.252.502.753.003.253.503.754.00

Precision:4 Volts

16 values .25 V/bit

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AMX0CF – AMUX0 Configuration Register

0 – single-ended analog inputs1 – differential pairs

Differential pair inputs:

+-

V

V can be positive or negative

AMX0CF

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ADC0CF – ADC0 Configuration Register

Bit7-Bit3: SAR Conversion Clock Period Bits

Bit2-Bit0:Internal Amplifier Gain000: Gain = 1001: Gain = 2010: Gain = 4011: Gain = 810x: Gain = 1611x: Gain = 0.5

ADC0CF

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ADC0CN – ADC0 Control RegisterAD0EN 0 = disabled

1 = enabled

AD0TM Track mode bitNormally 0

AD0INT 0 = conversion not completed (must be cleared by software) 1 = conversion has been completed

AD0BUSY 0 = conversion not in progress 1 = conversion in progressADC0CN

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ADC0CN – ADC0 Control Register

Bit3-2: ADC0 Start of Conversion Mode Select.If AD0TM = 0 (tracking mode on):00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.01: ADC0 conversion initiated on overflow of Timer 3.10: ADC0 conversion initiated on rising edge of external CNVSTR.11: ADC0 conversion initiated on overflow of Timer 2.If AD0TM = 1: Same as above except conversion takes 3 SAR clock cycles longer

Bit1: ADC0 Window Compare Interrupt Flag.This bit must be cleared by software.0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.1: ADC0 Window Comparison Data match has occurred.

Bit0: ADC0 Left Justify Select.0: Data in ADC0H:ADC0L registers are right-justified.1: Data in ADC0H:ADC0L registers are left-justified.

ADC0CN

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Selecting VREF, Gain• Maximum VREF = 3.3V (Vdd)

• Suppose analog range is about 0-3V– No Gain needed

– External VREF of 3V

or– Gain = .5 (so analog range becomes 0-1.5V)

– VREF from DAC0 of 1.5V

• Suppose analog range is low: 0-0.01V– Use max gain of 16 (so range is 0-0.16V)

– VREF from DAC0 or external, 0.16V)

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ADC0 Example 1

Vin+-

• Differential input (can be negative or positive) on AIN0 and AIN1 (channel select AIN0)• Convert on timer 2 overflow• Amplify by 4• Right justified data• Interrupt each conversion• External Vref = 2.0V

2.0V

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ADC0 Example 1Data Conversion:

n

VREF

GainVinCode 2

Gain = 4VREF = 2.0VNote: Vin limited to range of -.5V to +.5V

Vin ADC0H: ADC0L

+.5V 07FFh 00000111:11111111

+.25V 0400h 00000100:00000000

0 0000h 00000000:00000000

-.25V FC00h 11111100:00000000

-.5V F800h 11111000:00000000

n = 12 for single-ended inputs, n = 11 for differential

Values are sign-extended.

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ADC0 Example 2Vin1Vin2Vin3

• Single ended inputs (3 of them)• Convert on timer 2 overflow• Amplify by 2• Right justified data• Interrupt on conversion

mov AMX0CF, #060h ; AMUX Configuration Register mov AMX0SL, #000h ; AMUX Channel Select Register mov ADC0CF, #009h ; ADC0 Configuration Register mov ADC0CN, #08Ch ; ADC Control Register

Channel can be modified in the program

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Conversion Calculations

0 Vref – 1 lsb

000h FFFh(4095)

analog range

digital range

There are 4096 different digital values corresponding to 0-Vref.Find the voltage per least significant bit:

Now find analog value corresponding to some digital value Xd

Va = x Xd

Vref4096

Vref4096

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ADC0 Programmable Window Detector

• Set limits for Analog input value

• Analog value continuously compared to the limits

• System is notified if analog input is out of bounds.

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ADC0CN

AD0WINT: ADC0 Window Compare Interrupt FlagThis flag must be cleared by software.0: ADC0 Window Comparison Data match has not occurred since this flag

was last cleared.1: ADC0 Window Comparison Data match has occurred.

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Example – Detect Darkness• Using light sensor setup, with “dark”

corresponding to .25 * VREF• When “dark” is detected, use an interrupt service

routine to turn on the LED.• When it becomes light enough, (.5 VREF) turn

LED off

n

VREF

GainVinCode 2

ADC0GTH: ADC0GTL

ADC0LTH: ADC0lTL

AD0WInt = 1

1221

)25.0( VREF

VREFCode = 400h

AD0WInt = 1

1221

)5.0( VREF

VREFCode = 800h

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Example – Detect Darkness

cseg at 043h ; set the interrupt vector

ljmp adw_int

….

adw_int: clr AD0WINT ; Clear interrupt flag (ADC0CN is bit addressable)

mov a, ADC0H ; check MSB of ADC to see which condition it is

clr C

subb a, #04 ; Is it less than 04?

jnc off_light ; if not, must be time to turn light off

setb LED ; if so, turn on light and return

sjmp over

off_light: clr LED

over: reti

Page 68: The Silicon Laboratories C8051F020

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Temperature Sensor

• Selected with the AMX0SL register• Otherwise treated the same as other ADC inputs• Using above equation, and ADC0 settings and conversion equation, we can convert

temperature to digital value.

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The “Other” Timers

• Timer 3 – auto-reload feature, more clock sources• Timers 2 and 4 – almost identical to each other

– auto-reload feature

– capture feature

– baud rate generator for UART0 & 1 (serial interface)

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Timer 3

• Clock sources:– External oscillator 8 (allows for real-time clock input for timed

applications)– Sysclk or Sysclk 12 (like all other timers)

• Always 16-bit, auto-reload. – Write “reload” value to TMR3RLH : TMR3RLL– Defines the time between overflows

• Can be used to start ADC conversion• Can be used for SMBbus timing

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TMR3RL – Reload Register

mov TMR3RLH, #(F8h) ; init reload valuesmov TMR3RLL, #(30h)

or

SYSCLK EQU 2000 ; SYSCLK frequency in kHzTC_1ms EQU (SYSCLK)*1 ; number of timer counts in 1ms

mov TMR3RLH, #HIGH(-TC_1ms); init reload valuesmov TMR3RLL, #LOW(-TC_1ms)

Assembler can do these calculations

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Capture Mode to Measure Intervals

TEX2

RCAP2 Timer2 value,EXF2 flag goes high,Timer2 interrupt generated if enabled

RCAP2 Timer2 value,EXF2 flag goes high,Timer2 interrupt generated if enabled

80511 2

If time interval is less than FFFF counts, then ISR can just subtract captured value 2 from captured value 1 to find time interval. Otherwise ISR must also keep track of overflows.

time interval

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Programmable Counter Array

• The ultimate timer/counter!– SIX different possible clock sources

– SIX modes of operation• Capture modes (with 3 edge options)

• Software timer (Compare) mode (interrupt when timer register = compare register)

• High speed output : (output pin is toggled when timer register = compare register)

• Frequency output: (square wave produced at a specified frequency)

• 8-bit Pulse-Width-Modulation mode

• 16-bit Pulse-Width-Modulation mode

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PCA Control

• 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H.

• Reading PCA0H or PCA0L does not disturb the counter operation.

• PCA0MD and PCA0CN are the configuration registers.

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PCA0MD

Counter/Timer Idle ControlECF: PCA Counter/Timer Overflow Interrupt Enable.0: Disable the CF interrupt.1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.

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PCA0CN

CF: PCA Counter/Timer Overflow Flag. CCF4-0: PCA0 Module 4 to Module 0 Capture/Compare Flag –

set by hardware when a match or capture occurs.

CR: PCA0 Counter/Timer Run Control

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PCA Capture/Compare Modules

• 5 modules: each module can operate in one of the 6 modes

• Specified by SFRs PCA0CPM0-4 (PCA0 Capture/Compare Mode)

• PWM16n: 16-bit Pulse Width Modulation Select

• ECOMn: Comparator Function Enable

• MATn: Match Function Enable.

• TOGn: Toggle Function Enable.

• PWMn: Pulse Width Modulation Mode Enable.

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PCA0CPMn

ECCFn: Capture/Compare Flag Interrupt Enable. This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt in PCA0CN. 0: Disable CCFn interrupts.1: Enable a Capture/Compare Flag interrupt request when CCFn is set.

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PCA Capture Mode• Transition (positive, negative, or either depending on how

CAPPn and CAPNn bits are set) on CEX pin causes current timer value to be captured.

• CCF flag indicates capture has occurred (and causes interrupt if enabled and unmasked.)

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Frequency Output Mode

• Programmable frequency square wave on CEXn

• High byte of PCA0CPn holds counts between toggles

• Frequency defined as follows:

CPHnPCA

FF PCA

CEXn 02

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8 bit PWM mode

• Pulse Width Modulation

T

Tp

Duty Cycle = TpT

Pulse width modulation means varying the duty cycle.

“Average” value of signal isproportional to duty cycle.