The Search for Negative Impact of 3D Cu TSVs -...
Transcript of The Search for Negative Impact of 3D Cu TSVs -...
The Search for Negative Impact of 3D Cu TSVs
Jeff West Advanced Technology Development
Texas Instruments, Inc.
WIDEIO MEMORY
TI 28nm Logic
Fine-Pitch Cu Substrate
uPillar
Joint
TSV
Joint
4/30/13 UTD/IEEE HSIC
Outline
Introduction
Cu TSV-induced risks to product
Impact of intentional Cu contamination of 28nm CMOS
28nm transistors: A stressful situation • Test Structure Description
• Electrical Data
• Temperature Dependence of TSV Proximity Effects
• TSV-induced Strain Analysis (NanoBeam Diffraction)
• Impact of CESL/STI on TSV-induced Strain
DCTE related issues – Liner rupture, Cu Pumping
Conclusions
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Introduction
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High bandwidth IO for Logic-Memory applications
See J. West, et al, Practical Implications of Via-Middle Cu TSV-induced
Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect,
VLSI 2012.
Miniaturization and SiP integration
See R. Dunne, et al, Development of a Stacked WCSP Package Platform
using TSV (Through Silicon Via) Technology ECTC 2012.
Logic-Wide IO interface – TSV Benefit
• POWER: 500mW reduction (= longer battery
life J), primarily due to IO voltage reduction
of Wide IO vs. DDR memory solution.
• PERFORMANCE: 4 Bank Wide IO memory interface: 16 Gb/sec
@200MHz with migration plan to 50Gb/sec.
• Non-TSV alternative: Requires two 2-channel DDR memories to compete;
Requires ~180 extra balls on package. Increases PCB layout overhead,
routing issues, ultimately increases board/phone size.
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QFN WCSP
New Package or Module Platforms Possible with TSVs at reduced form factors
Stacked WCSP
CSP BGA
Current Package or Module Platforms
Face-up WCSP
Replace Ground Downbonds
QFN die stack, no wirebonds
or
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TSV Potential Applications
Outline
Introduction
Cu TSV-induced risks to product
Impact of intentional Cu contamination of 28nm CMOS
28nm transistors: A stressful situation • Test Structure Description
• Electrical Data
• Temperature Dependence of TSV Proximity Effects
• TSV-induced Strain Analysis (NanoBeam Diffraction)
• Impact of CESL/STI on TSV-induced Strain
DCTE related issues – Liner rupture, Cu Pumping
Conclusions
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Embedded TSV
Tips
Device side of wafer
Wafer backside
Cu Contamination Risk
Backgrind
. . . . . . . . . . . . . . . .
. .
.
. . . . . . . . . .
Any process that simultaneously exposes backside Si and Cu TSVs is inherently
at risk of permanent contamination of the bulk Si and the associated risks of impacting
device performance.
Risk of Cu contamination is high…drives alternate TSV backside reveal schemes
TSV Backside Reveal Processing
“Hard Reveal”
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(Animated slide)
8
To avoid the risk of Cu contamination, a SOFT REVEAL
approach has been adopted by many:
WBG
+CMP
Si remains over all TSVs
Si Etch
Etch Si to protrude TSV
tips As-received TSV wafer
wafer backside
CMOS Front side
Deposit Inorganic
passivation (e.g., SiN)
CMP to expose Cu
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Device Side
1. Process 28nm devices w/Via MiddleTSVs; Probe SRAM/Parametric modules
2. Bond device wafer to Carrier Wafer
3. Backgrind Device wafer to 50um (into TSV tips)
4. Sputter 200A Cu onto device wafer backside
5. Spin on & cure 8um polymer at 200C (to drive Cu into Si substrate)
Carrier 1
Intentional Backside Cu contamination of 28nm CMOS wafers
6. Attach 2nd wafer carrier, remove 1st wafer carrier, flip
Carrier 2
Carrier 2
7. Reprobe SRAM/Parametric modules
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(Animated slide)
Electrical impact of intentional backside Cu contamination
did not impact SRAM/Parametric probe!
1) No significant (4Mb) SRAM yield shift observed
2) No significant shift in Iddq post MEOL processing.
3) No significant impact to Diode Leakage or GOI modules
4) No significant impact to Bipolar Hfe at room temp or 125C.
Also see Effects of Deliberate Copper Contamination from the Plating Solution on the Electrical
Characteristics of MOSFETs, K.C. Tee, K. Prasad, C.S. Lee, H. Gong, C.L. Cha, L. Chan, and A.K. See,
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 2, MAY 2001
Authors theorized that despite published high
diffusion rate of Cu into bulk Si, formation of Cu3Si
on wafer backside may have retarded diffusion
into bulk Si.
“As a result, both the junction leakage current
& MOSFET parameters are not affected even
though the backside of the wafer is contaminated
with Cu.”
Cu conc after
5 hr/400C anneal
Wa
fer
ba
cksid
e
SIMS profile
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Bulk Si Intrinsic Gettering Layer
Contamination impact could be suppressed by Si Intrinsic Gettering Layer?
Cross-section through Si substrate
~3um
Outline
Introduction
Cu TSV-induced risks to product
Impact of intentional Cu contamination of 28nm CMOS
28nm transistors: A stressful situation • Test Structure Description
• Electrical Data
• Temperature Dependence of TSV Proximity Effects
• TSV-induced Strain Analysis (NanoBeam Diffraction)
DCTE related issues – Liner rupture, Cu Pumping
Conclusions
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Longitudinal
stress
Transverse
stress
Sensitivity of channel mobility to applied stress
N & PFET carrier mobility respond to stress differently:
Y. Choi et al, IEEE TED 2006
1GPa compressive
longitudinal stress
increases mobility of
PFET 72%
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Concern over
disruption in
engineered stress
by nearby TSVs
14
There are many sources of variation for 28nm transistor
performance
TI’s 28nm SPICE model captures various context-dependent
(layout variation) effects Dual stress liner (DSL) boundary effect
LOD (length of diffusion, a.k.a. STI proximity effect)
WPE (well proximity effect)
APE (active proximity effect)
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Test Structure Description
Dummy poly gates Dummy poly gates
Target transistor Logic MOSFETs
[1-10]
[110]
Analog IO (Wide/Long) MOSFETs
Analog Friendly HVG components (W/L=2/0.12 um)
Drain Extended MOS components (W/L=5/0.36um)
Poly direction
Horizontal = [110]
Vertical = [1-10]
Transistor designed to mitigate any process related issues
(ex. poly micro-loading and local STI stress effects)
C28.M transistor layout
Gate Pitch = 118nm/Poly-to-Poly Space = 82nm
W/L=0.2/0.032um
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Test Structure Description (cont’d)
TSV
“Diagonal”
[1-10]
[001]
TSV proximity
to device
Device location relative to TSV Transistors are much smaller than shown!!
TSV types Isolated TSV
JEDEC TSV array (40mmX50mm pitch)
“Horizontal”
TSV
TSV TSV TSV TSV TSV
TSV TSV TSV TSV TSV
TSV TSV TSV TSV TSV
TSV TSV TSV TSV TSV
40um 50um
Dense Array TSVs (35X35mm pitch)
[110]
“Vertical”
10mm diameter TSV, formed
between Contact and MET1
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10um diameter TSV Proximity Effect (Horizontal Isolated TSV) to devices
with W/L=0.2/0.032um
No significant TSV proximity effect (< ~2.5%) in device performance
or variation when TSV to device space is ~4um
Electrical Data (300mm full thickness wafers)
400
500
600
700
800
900
ION
NO
MC
Mx
ID
3 7 10 15 30
Proximity
ION
NFET
4
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400
500
600
700
ION
NO
MC
Mx
ID
3 7 10 15 30
Proximity
ION
PFET
4
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Electrical Data Summary (Horizontal TSV proximity effect)
Poly
direction
Channel
direction Device
Change in |Ion| @ 4um TSV proximity,
relative to reference devices
Iso JDEC Array
(40umX50um)
Dense Array
(35umX35um)
Logic device
W/L=0.2/0.032 [1-10] [110]
NFET < 1% < 1.5% < 1%
PFET < 1% < 2.2% < 1.8%
Analog device
W/L=2/0.12
[1-10] [110] NFET < 1% < 0.6% < 1.5%
PFET < 0.6% < 0.4% < 1.5%
[110] [1-10] NFET < 0.5% < 0.9% < 0.4%
PFET < 1.2% < 0.8% < 1.9%
Compare this with other context-dependent sources for typical 28nm layout:
DSL effect ~10%
LOD effect ~ 8%
WPE effect ~ 6%
Vertical and diagonal orientations similarly insensitive to TSV proximity at 4um
Other components evaluated (DEMOS) also show insensitivity to TSV proximity
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Temperature Dependence in Arrayed TSV Test Structures
-3
-2
-1
0
1
2
3
0 3 6 9 12 15
ION
(%
)
TSV proximity to NFET (um)
Horizontal_105 Horizontal_RT
-3
-2
-1
0
1
2
3
0 3 6 9 12 15
ION
(%
)
TSV proximity to PFET (um)
Horizontal_105 Horizontal_RT
NFET
105°C
vs R.T.
R.T. 105 °C shows 1~2% change in ION as a function of TSV proximity,
Still insignificant compared to other context-dependent sources (ex. DSL effect ~ 10%).
PFET 105°C
vs R.T.
4 7 10 13 16
7 10 13 16
T- test for R.T. vs 105°C @4um TSV proximity
580
590
600
610
620
630
640
650
ION
(uA
/um
)
25 105
Measured Temp.
Each Pair
Student's t
0.05
IO
N (m
A/m
m)
105C 27C
Test Temperature
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NBD TSV Proximity Scans
Near-TSV Strain
on near-surface
Si is dramatically
reduced just
below tensile
contact ESL
4/30/13 UTD/IEEE HSIC
Outline
Introduction
Cu TSV-induced risks to product
Impact of intentional Cu contamination of 28nm CMOS
28nm transistors: A stressful situation • Test Structure Description
• Electrical Data
• Temperature Dependence of TSV Proximity Effects
• TSV-induced Strain Analysis (NanoBeam Diffraction)
• Impact of CESL/STI on TSV-induced Strain
DCTE related issues – Liner rupture, Cu Pumping
Conclusions
4/30/13 UTD/IEEE HSIC
0C
100C
Device
Operating
Range
200C
300C
400C
To
TSV is
TENSILE
TSV is
COMPRESSIVE BEOL
Temperature
Range
Embedded TSV stress vs. Temperature
Cu
migration
Liner Rupture
Bottom of TSV
embedded in Si
TSV
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TSV liner requires
optimization to
avoid this issue!
TSV post plating anneal strategy:
CMP away intentionally extruded
metal before entering the BEOL
Post ILD1 Post ILD2
Top-down optical inspection
of TSV cover
MET1 MET2
TSV 350/10’
ECP Anneal
(condition A)
Pumping
Region
xSTEM
10um TSV
…and causes Cu “pumping” into the overlying BEOL
Higher TSV Anneal Temperature
Reduces Cu Pumping - Good for BEOL mechanical integrity
Increases tensile stress in TSV Can cause surface pits at GBs
Creates topographic anomalies that disrupt interconnect formation
Preferential pit
formation at GBs
Resolve issue by implementing MET1 & 2 TSV CAP Superstructure.
M2 routing over TSV not permitted
M2 over TSV FIB Images
IMPACT OF TSV ANNEAL
Post-TSV CMP
& SiCN ES Cap
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Conclusions Various risks of integrating 3D Cu-TSVs were anticipated and studied.
Impact of intentional backside Cu contamination was found to be a non-issue
Stress impact of 10mm TSVs was found to be negligible for 28nm
CMOS/Analog transistors placed beyond 4um, compared to the variation
induced by other context-dependent/layout effects.
TSV stress impact is suppressed by tensile-CESL & compressive STI
and can be intentionally incorporated into TSV environment.
1st known use of NBD technique to characterize TSV-induced strain on
Si, which allows ~3nm resolution measurements within fully processed
wafers.
Liner Optimization is required to avoid rupture during thermal expansion.
Design rule modifications for routing near/over TSVs can provide margin
against Cu pumping and pitting.
TI has successfully integrated TSVs into both CMOS and Analog applications
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Backup (for Q & A)
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Dual Stress Liner Boundary effect at 28nm node
Y. Choi et al, IEEE TED 2010
TEM X-section strain
analysis (GPA)
No DSL boundary
DSL boundary = 0.05um
Horizontal DSL boundary effect can
cause degradation of:
~30% in mobility
~10% in ION
Compressive
strain
DSL boundary = 0.05um No DSL boundary
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Impact of CESL/STI on TSV-induced Strain
1) ESTI < ESi
STI can absorb
TSV-induced stress
2) Tensile CESL (~GPa)
counters TSV-induced
tensile strain for near-
surface Si
Young’s Modulus “stiffness” of an elastic material
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NanoBeam Diffraction (NBD) Analysis
2d
2d0
Dd
663pix.
671pix.
gate
plug plug
Nano-diffraction pattern
( Si[011] incident beam )
200
200 022
022 111
111
111
111
horizontal
vertical
Small, nearly parallel beam creates sharp diffraction spots; shift in the distance between
spots is used to calculate d-spacings between Si planes
• ± 0.2% strain resolution (125 MPa stress sensitivity).
• 3 nm spot size (much smaller than m-Raman technique [~1mm])
• Strain measurement with actual process stressors, such as CESL and STI
(Raman technique typically performed with exposed TSV/Si top surface)
STI STI
Reference
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Focused Ion Beam (FIB) Thin Area of Interest
H-bar
e- beam
Achieve large area xTEM
specimens in 4-6hrs
NBD Sample Generation 4/30/13 UTD/IEEE HSIC
MET7
TSV
Cross-section SEM through 7LM testchip (North-South Cut)
TSV Unit cell design anticipates Pumping/Pitting/Si Strain Places MET1 & MET2 covers over TSV with slotted vias between
Circumscribes TSV with mini-scribeseal below MET2
Crack & Cu migration containment
Relaxed pitch routing required at MET3-7 over TSV
VIA2-MET7 “reinforcing structure” to extend TSV through brittle OSG layers
8LM BEOL
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IMD
2 P
um
pin
g (
A)
TSV Diameter (60um depth)
Reduced diameter, however, drives higher aspect ratio TSV and
generates new defect issues such as “hydraulic pumping.”
~30% reduction
Pumping magnitude reduces with TSV diameter
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• Subsequent designs utilize available space more efficiently.
ESD
Protection
(red blocks)
TSV cell
DCAPs
Example Layout Early testchip
Practical TSV Design Considerations for CMOS
Wide IO application with centralized 40x50um pitch TSV array requires ESD &
decoupling capacitors (DCAPs) that are placed in the immediate vicinity of TSVs
NO NEED to place transistors within 4um of TSVs.
4/30/13 UTD/IEEE HSIC