The preliminary design for BESIII MDC electronics Yubin Zhao
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Transcript of The preliminary design for BESIII MDC electronics Yubin Zhao
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The preliminary design
for BESIII MDC electronics
Yubin Zhao
On behalf of MDC electronics group
Sep. 17, 2002
IHEP, Beijing
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I. Design goal
II. Design considerations
III. Design scheme
IV. Summary
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I. Design goal
● Charge measurement
dE/dx particle identification● Drift Time measurement track / momentum.● To provide fired information Trigger .
BESIII MDC: 9008 sense wires.
dE/dx and momentum measurement required.
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● charge measurement ▲ charge resolution ENC
e = 6% for chamber plus electronics
ee (electronics) = 15% × de (MDC itself)
So ee = 0.9% There are 47 layers of sense wires and assume 70% truncation, So for a single electronics channel’s resolution :
ENC = 5.2% For MIP , most probable energy loss = 100 fc
So ENC = 5 fc
▲ Charge dynamic range : 15fc—1800fc▲ Charge INL : 2% (15fc--1800fc)
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● Time measurement
▲ time resolution t The “chamber + electronics” spatial resolution:
p = 130m
A single wire: dp ≤ 125 m So for a single electronics channel:
ep = 35.7m For MDC, electron drift velocity ≈ 30m/ns. The time resolution for a single channel will be:
t ≤ 1.2 ns
We take t ≤ 0.5 ns
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Which factors contribute to the t ? ① The length of e- and e+ bunches in Z direction. z = 1.5cm Uncertainty of collision moment :
C
cm
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5.1
② The timing error caused by time walk . t2 ≤ 1ns It can be corrected by off-line using charge value. ③ The time measurement error t3 of TDC.
It is possible to get t3≤0.5ns using CERN HPTDC. .
35 ps Negligible !t1
▲ Time range : 0 -- 400 ns
▲ Time INL: 0.5%
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II. Design consideration ● BEPCII Multi-bunch running.
Bunch crossing = 8ns. L1 = 3.2 s. Pipeline technique must be used .
● BEPCII Lum = 1×1033/cm2/s
Large quantity data to be acquired;
Multi-stage parallel processing must be adopted,
So as to reduce system dead time. ● MDC: small cell configuration. size ~ 14mm×14mm. Simulation shows : ■ Max. drift time: td_max = 400 ns
Max. signal width: tw_max = 650 ns
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● The output signal of sense wire is a pile-up of a number of 1/t waveforms formed by a single ionized electron.
● The signal rate for a single wire : 30K / S
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III. Design scheme
Four types of modules/cards:
1. Preamplifier cards;
2. SDQT modules;
3. Calibration modules;
4. Logic control modules.
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Simplified MDC electronics block diagram
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1. Preamplifier ① A transimpedance type.
Band width : 70MHz—80MHz 。 ② Low power dissipation. < 30mw.
③ Differential output, capable of driving long cable(18m).
④ A piece of hybrid per channel.
⑤ 8 ch / card ( ~ 10cm×6cm).
Most cards will be directly mounted on endplate.
Some cards for inner chamber will be mounted 0.5m-1m away
from endplate.
⑥ Use BESII MDC preamplifier as baseline design with some
modifications.
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2. SDQT Module⑴ 《 Amplification+Shaping+discrimination 》 circuitry
▲ To split the signal into two branches. ▲ Time branch: using leading edge discrimination to give the arrival time ▲ Charge branch: signal shaping to fit the charge measurement.
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How to shape the signal ? It depends on the scheme used for Q measurement. A numeric integral method based on FADC will be used for Q measurement:
Successively digitize the analog signal with FADC, Make a numeric integral over digitized data; The result represents the charge of waveform.
How to determine the integral width? It depends on the pile-up probability of signal. The signal rate (fired rate) of a single wire ~ 30k/s. According to Poisson probability formula
etn
N
N
tntNP
!
)(),(
We get a relation between pile-up and interval t :△
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The integral width can be setup to be 1μs,
the pile-up probability : < 3 % .
“drift time + shaped signal width ” 1μs
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⑵ Charge measurement circuitry
FADC-based pipeline scheme.
Numeric Integral to acquire charge value.
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Block diagram for Q measurement
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129125
2.31
_
_
ns
us
periodclock
latencyTriggerL
Pipeline length:
Where +1 is for getting pedestal value just prior to t = t
One Local FPGA can treat with 4 or 8 channels.
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ClockTrigger
A preliminary prototype for Q measurement
Receiver & Driver FADC
Differential Signal from MAMP
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Hit Flag FIFO
Local FPGA
Receiver & Driver FADC
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Receiver & Driver FADC
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Receiver & Driver FADC
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CH 1
CH 4
CH 3
CH 2
8Four ChannelsFour Channels
VA[8..23]
Trigger Counter
Trigger FIFO
VME Control
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DelayWrite
VME_ResetCheck Trigger NumberClear Trigger FIFORead Trigger FIFO
VD[0..11]
VD[0..11]
x 8
Rea
dR
ST
Read FlagW
rite
Fla
g
Global FPGAGlobal FPGA
Wor
k M
ode
JTAG
VD[0..31]
VD[0..15]
VA[8..15]
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Hit
F
lag
Reset
Download PROM
VD1
VA1
VCAS,D0,D1,AM[0..5],Write,DTACK, et. al.
8 bits DIP Switch
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Write_inRead_out
Download PROM
VME
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9U VME module with 32ch.
40MHz FADC, 10bit
Pedestal stability: 0.5LSB
INL: 0.2%
DNL: 0.1%
Crosstalk: 0.1%
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⑶ Time measurement circuitry To measure the time interval between t and the arrival time
of wire signal.
It covers three sub-intervals : ① Flight time of particle from collision point to a drift cell.
A random value.
② The drift time of ionized electron which is nearest to a sense wire.
This time is exactly one we need to measure.
③ The transfer time of signal from the avalanche point on wire
to the input of preamp.
A random value too.
The contributions from and will be given by offline correction.① ③
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Scheme for time measurement :Using CERN HPTDC as key component. □ Dead time free.
□ 32 channels/chip 。 Size ~ 2.7×2.7 cm2 。□ External clock : 40MHz 。 Synchronized to bunches.
□ Time resolution : ~ 250ps RMS low resolution mode
~ 70ps RMS medium resolution mode
~ 35ps RMS high resolution mode
~ 15ps RMS very high resolution mode (8ch per chip) 。□ Double pulse resolution : 5ns (typical); 10ns (guaranteed).
□ Separate leading or trailing edge measurement;
Simultaneous measurement of leading edge and pulse width
(not true for very high resolution mode).
□ Zero suppression and address assembly inside chip.
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How does the HPTDC work? HPTDC covers: a coarse time counter, a fine time counter
a PLL, a DLL.
◆ PLL performs multiplication of external 40MHz clock to
40MHz, 160MHz, 360MHz. ◆ Coarse time counter choose one of above three clocks as
its working clock to record the integer number N of clock between t and hit signal.
◆ DLL turns the working clock into a high frequency clock . ◆ Fine time counter works on high frequency clock and
performs measuring the fractional part f of a clock . ◆ ( N+f ) delivers the drift time being measured.
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The R&D work based on HPTDC is under going.
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How to readout Q and T data ? ◆ To design the SDQT module according to
9U-VME64x standard.
◆ To set up a Global buffer to store Q and T
data in each SDQT module.
◆ To implement the function of Global buffer
using a FPGA called as Global FPGA.
◆ To adopt BLT readout mode.
◆ To read out the data from the Global buffer
every other 256 Triggers.
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Data readout from SDQT module
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3. Calibration modules.
Used to calibrate the whole system.
4. Logic control and fan out / fan in modules.
Used to make the system working in order.
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IV. Summary● System consists of 4 types of modules/ cards:
Preamp., SDQT, Calibration, Logic control.
● The SDQT module covers : 32 ch. of “amp. + shaping +Disc” ; 32 ch. of Charge measurement circuit ; 32 ch. of time measurement circuit;
A programmable threshold voltage generator.
● The numeric integral is used for Q measurement.
Use of FPGA makes the charge extraction and zero
suppression much simple.● CERN HPTDC chip: for T measurement.
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Thank you!