1

The Once and Future CAD

February 21, 2014 CCC/SIGDA Workshop on

Extreme Scale Design Automation Tampa, Florida

William H. Joyner, Jr Semiconductor Research Corporation

Who

Director, Computer-Aided Design and Test Sciences Semiconductor Research Corporation

The Title

The Once and Future CAD

HIC IACET ARTHVRVS, REX QVONDAM, REXQVE FVTVRVS

  “Give your observations on the EDA community (especially the value of interactions between industry and academia), and make suggestions for what can be improved.”

  “Discuss the history of EDA, suggest what can be done, what should be done and what should not be done, stir as much controversy as possible.”

  “Focus on the SRC philosophy for EDA funding and in particular the interaction with NSF for joint funding projects, and some insight on what SRC and SRC companies feel is important in EDA research.”

  “We are not restricting keynoters to any particular topics and are interested in their big-picture views on EDA.”

The Content

6

Semiconductor Research Corporation

  1982: established as a consortium of US semiconductor companies to fund and manage university research

Since 1982: $800M member investment, 9000 students, 2000 faculty, 250 universities

  2007: Awarded National Medal of Technology “for building the world’s largest and most successful university research force to support the semiconductor industry”

Erich Bloch, NSF Director

Robert Noyce, Intel founder

Jack Kilby, Nobel Laureate

The Handshake

The Medal

The Whisper

More money for DA research!

7

SRC GRC Members and Partners

8

GRC: Global Presence about 400 research tasks at >100 universities worldwide

USA

Canada

Sweden

Japan

Netherlands

India

Poland

China

Singapore

Italy Qatar

Taiwan Israel

Switzerland

Colombia

Finland

Russia

Austria

Spain

Australia

Brazil

86 Projects in 26 different countries outside of USA since 2000

Ireland

Korea

UAE

Scotland

UK Germany

10

SRC GRC Research Program Structure

  CADTS - Computer-Aided Design and Test Sciences   Logic and Physical Design   Test and Testability   Design Verification

  ICSS - Integrated Circuit and System Sciences   Integrated Systems Design   Circuit Design

  DS - Device Sciences   Digital CMOS   Non-Classical CMOS   Memory Technologies   Modeling and Simulation   Compact Modeling   Analog and Mixed-Signal

  NMS - Nanomanufacturing Sciences   Nano-Engineered Materials   Patterning   Metrology   ESH

  IPS - Interconnect and Packaging Sciences   Packaging   Back-End Processes

  CSR - Cross-Disciplinary Semiconductor Research   Small, very forward looking,

one year research grants   Special projects

SRC GRC: Numbers

  Cumulative:   Involvement with 274 universities in 26 countries   1840 faculty   7561 students   330 patents

  Current:

  383 contracts with 116 universities worldwide   390 faculty investigators   670 graduate students;

  2013 investment/leverage:   $24 M member contributions   $15 M government leverage

11

12

TxACE: Texas Analog Center of Excellence

  Primary focus on design/CAD with UT-Dallas in a lead role

  71 tasks in Circuits, Systems, LPD, Test, and Verification

  Startup funds from state, university, TI, private donor

Prof. Ken O, Director

ATIC-SRC ACE4S Center of Excellence for Energy-

Efficient Electronic Systems Prof. Mohammed Ismail, Prof. Ibrahim Elfadel

13

CADTS Mission and Organization

Computer-Aided Design and Test

Logic and Physical Design

Test and Testability

Verification

95 tasks 47 universities 95 faculty 155 students

39 tasks

37 tasks

19 tasks

Promote excellent and relevant university

research to strengthen member leadership in

computer-aided design and test through tools

and techniques that:   reduce cost and time-to-market through productivity improvement and correctness assurance   enable high level/high value design   take full advantage of technology advances through linkages to manufacturing   anticipate future CMOS and post-CMOS CAD challenges

Leveraged by strategic partnerships and funding

sources, and

producing highly qualified graduate students

who can fill key positions in member

companies 14

SRC GRC: University Technology and Talent

  Effective   Early influence on/access to research   Quality, organized interactions with industry members   Early access to sponsored students   Interaction with peers/competitors, suppliers/customers   Rich interactions between faculty, industry, and students   IP portfolio – freedom of use/defensive publications

  Efficient   Leverage of research dollars (members, government)   Experienced management of research contracts   Rich website repository for research results   Up to date info on students

15

16

SRC/NSF Joint Programs

  Joint needs development, solicitation, and selection of projects

  SRC, NSF form expert panels to evaluate proposals using NSF process

  Single statement of work for each proposal; two funding instruments

  US universities

  Each project is reviewed annually by members, along with similar research

17

NSF Proposals

  Intellectual merit

  Broader impact

  Panel review

  Transformational

  Translational

18

SRC/NSF Joint Programs

  Mixed-Signal Electronic Technologies   16 tasks from 14 universities with 26 faculty

  $6.2M over 3 years, 2001-2004

  Multicore Design and Architecture (MCDA)

  28 tasks from 27 universities with 43 faculty

  $10.2M over 3 years, 2009-2012

  Failure-Resistant Systems (FRS)

  23 tasks from 18 universities with 29 faculty

  $6.0M over 3 years, 2013-2016

19

T3S: Trustworthy and Secure Semiconductors and Systems

New SRC Initiatives

SemiSynBio: Semiconductor Concepts from Synthetic Biology

Computer-Aided Design and Test Strategic Plan 2015-2019 March 4, 2013

Mahesh Sharma AMD SACC Chair Mukesh Ranjan Intel SACC Vice Chair William Joyner SRC Director LaTanya Holmes SRC Administrative Assistant

21

Two Big Things

  Complexity  Bigger more of everything  More factors to be concerned about

  Changing paradigms  Homogeneous digital heterogeneous  Monolithic IP IP from multiple sources  Single chip design 3D stacks, chip becomes board

  Verification, Test, and Logic-Physical Design – all must take these factors into account   Innovation, not incremental improvement, is needed!

22

Complexity

“The complexity of things – the things within things – just seems to be endless. I mean nothing is easy, nothing is simple.”

– Alice Munro Nobel Prize in Literature, 2013

“We academics love complexity. You can write papers about complexity, and since complexity is fundamentally intractable in many ways, you're not responsible for outcomes.” – George Whitesides Harvard chemist

23

Changing Paradigm

“In order to change an existing paradigm you do not struggle to try and change the problematic model. You create a new model and make the old one obsolete.”

– R. Buckminster Fuller

“Ideas that require people to reorganize their picture of the world provoke hostility.”

James Gleick American journalist

Num

ber

of T

rans

isto

rs

Functionality Functionality + Analog Functionality + Analog + Testability Functionality + Analog + Testability + Power Functionality + Analog + Testability + Power + SI Functionality + Analog + Testability + Power + SI + DFM Functionality +Analog + Testability + Power + SI + DFM + 3D Functionality +Analog+ Testability + Power + SI + DFM + 3D + Reliability

Design Complexity / Changing Paradigm

1K

10K

100K

1M

10M

100M

1B

10B

CAD enables the management of

ever more complex phenomena

Tool capacity and/or productivity limits constrain

achievable complexity

24

25

CADTS Ecosystem

  Design and CAD must extract the highest performance from each technology node!   CAD poised on “cutting edge” to leverage new technologies.   CAD needed to squeeze even more out of older technologies.

  Tools are both the enabler and limiter of design, test and verification.   Tools enable by comprehending more and more complex factors.   But complexity exacerbates capacity limits, especially for analog/mixed signal.

  Pre- and post-silicon validation an increasing focus due to time- to-market, lower average selling price, complexity factors.

  3D CAD challenges increase with finer-grained 3D integration; more challenges, more important below 22nm.

Universities

IDM

/ F

able

ss

EDA Industry

Fabless and Startups

Trends in SRC CADTS Funding

  ~5 years ago: 50% Logic/Physical Design

25% Test 25% Verification

  Now: 40% Logic/Physical Design 30% Test 30% Verification

26

Trends in SRC CADTS Funding

  Members have been consistent in support of CADTS

  Up: Analog/mixed-signal

Resilience; failure resistance Post-silicon validation Interconnect

  Steady: Power reduction/analysis DFM: tools at the manufacturing interface System-level

  ? New technologies 27

Priorities

28

“I have this really high priority on happiness and finding something to be happy about.”

– Taylor Swift

“I would like to be remembered as a guy who had a set of priorities, and was willing to live by those priorities.”

– George W. Bush

ETAB Priorities

  Scaling CMOS to the practical limits   Analog/mixed-signal   Alternative and ultimate scaling of memories   Energy management   3D IC architecting   Multicore/ HW-SW systems   Reliable, resilient and robust circuits and systems   ESH   I/O architectures   Emerging materials and processes

29

= CADTS related

Strategic Plans

30

“I don’t know the secret to success. But I do know the secret to failure is trying to please everybody.”

― Bill Cosby

“We must ask where we are and whither we are tending.”

― Abraham Lincoln

31

SRC continues to increase relevance, value, and leverage to investigators

  Funding students and professors on research projects

  Providing real-world examples to researchers

  Enabling student internships and employment

  Engaging member design community across the globe

  Facilitating inter-university collaboration

  Providing infrastructure for research progress and reviews

  Focusing on applications of interest to members

  Supporting liaisons between members and researchers

Funding for University Research: What Industry Wants and How to Get their Money

William H. Joyner, Jr. Director, Computer-Aided Design and Test Global Research Collaboration

Semiconductor Research Corporation University of California, Riverside April 4, 2011

All faculty will love you when you go to SRC!

Myth vs Reality

Myth Reality

L ≈10% H ≈ 90%

Agents

36

Why Would Companies Join SRC?

  Leverage (industry and government)   Solicitation and selection competitive process   Focus on “deliverables”   Students and student programs   Research administration   Awareness   Broad coverage

SRC Funding Opportunities www.src.org

Type Funding here or click here

37

SRC Funding Opportunities www.src.org

38

SRC GRC Member-Driven Research Selection and Funding Process

  Member-driven creation of needs document

  Request and submission of white papers

  Member review of white papers

  Request for proposals

  Member review and selection of proposals to fund

  Internal SRC Research Management Committee review

  Three-year contract start

  Annual member reviews of progress

  Submission of reports and “deliverables” by researchers

  Members select “custom” projects with 20% of their funds

39

Research Selection – Member Driven

  We get hundreds of white papers   We end up funding fewer than 10% of them   How can we improve this process?

  How do we assure “forward-looking” research and research of relevance and value to members?

40

Proposals to Industry Funding Agencies

  What is industry looking for?

  How are proposals evaluated?

  What helps and what doesn’t?

  Working with industry

41

What Is Industry Looking For?

  Connections with industrial contacts

  New tools, techniques, methods (better)

  Comparison with what exists now

  Method for transferring university work into industry

  Students to work in summers and permanently

  Work meeting industry needs

  Cost effectiveness

  Work members should be worried about but aren‘t

  Researchers bringing their own leverage

42

Industrial Contacts

Faculty Member

Faculty Member’s Industry Colleague

Industry’s SRC Board Member

SRC

?

43

?

Proposals and “BIP”

Are you aware of any blocking background intellectual property needed to practice the expected results of the research that will not be made available royalty-free to SRC Members? ___No___Yes

Please explain __________________________________ __________________________________

44

White Papers

“Please use fonts of 10-point size or larger” “Proposals should be for no more than

$xxxK annually”

45

White Papers

46

Revised Importance Criteria

10. This PI is our former CTO

9. My company also funds this guy under the table

8. We also have people working on this, but they’re idiots

7. Maybe I can get a job at this university when I retire

6. We’re about to go belly up, so let’s give it a shot

5. Below the threshold for a trip to Urbana-Champaign

4. Our competitor wants to customize this; maybe it’s good

3. On our list of top 100 problems, this doesn’t appear

2. When this work was presented here, nobody came

1. This PI was fired by my company last year 47

Revised Satisfaction Criteria

10. PI walks high above water

9. PI walks on water

8. Students get jobs with SRC members

7. Students become founders of startups using SRC IP

6. PI purchases Palo Alto home with SRC money

5. TAB funds PI only after hand recount of members

4. Deliverables found to be already patented by ______

3. Students all deported for visa irregularities

2. PI sinks even on dry land; sends students to review

1. PI is already six feet under; cannot attend review 48

Industry Interaction

49

Good: “I am working with ______, _______, _______ among your member companies.” Bad: “I am working a lot with _______.” (not an SRC company). Worse: “My students are all joining

a) SRC competitors b) my start-up”

Access to fabrication Access to real designs

50

George Santayana (1863-1952)

•  “Those who cannot remember the past are condemned to repeat it.”

•  “History is a pack of lies about events that never happened told by people who weren't there.”

History

The Brave New Old World of

Design Automation Research

Ralph K. Cavin III Semiconductor Research Corporation William H. Joyner, Jr. Semiconductor Research Corporation Walden C. Rhines Mentor Graphics Corporation National Science Foundation Workshop on Electronic Design Automation – Past, Present, and Future July 8, 2009 Arlington, Virginia

The Brave New Old World of Design Automation Research

“Community, Identity, Stability” – Aldous Huxley, Brave New World, 1932

•  A community of experts from industry and universities, representing multiple disciplines

•  Renewed identity as an exciting research area

•  Stability of support for research and education

Old “Productivity Gap” Chart

Source: various attributions

57

Old “Quadruple Whammy” Chart

Source: Kurt Keutzer 20th century

Tall Thin Designers

Tall Thin Designers Behavioral Design

Logic Design

Place and Route

Layout

Tapeout

Short Thin Designers Behavioral Design

Logic Design

Place and Route

Layout

Tapeout

Tall Fat Designers Behavioral Design

Logic Design

Place and Route

Layout

Tapeout

What Happened

NSF 2006 Forum on Future Directions in Design Automation Research

63

SRC/NSF Forum

  Held October 30-31, 2006, at NSF in Arlington, Virginia   Leading researchers and engineers assembled:

  12 faculty from leading universities   11 industry researchers   8 NSF participants

  Panels, presentations helped develop findings

Source: 2006 Forum

64

Three Grand Challenges in Design Automation

Challenges in design automation are many, but they can be grouped into three areas:

  System-level design is needed at the top to increase the productivity of designers – otherwise efficient use cannot be made of advanced devices and materials

  Robust optimization in the middle is necessary to contain the exploding complexity of systems and to offset the diminishing returns afforded by feature size shrinkage

  Design for manufacturing at the back end (and throughout the flow) is critical to assure that we can produce products using new technologies Models and abstractions are key at all levels of the design process

Source: 2006 Forum

65

System-Level Challenges

  System level techniques are needed to achieve shorter design times with higher quality to address system level problems: clock, power management, interconnection, fault tolerance, …

  Design tools must extend to where design is going, including the software level

  A compositional method of designing and connecting modules such that the functionality and performance are predictable is needed; it must be aware of implementability, verification, test, and reliability

  A design flow and methodology must enable more sophisticated handoffs; a collaborative framework must focus on the interfaces between abstraction levels to allow stable robust, reusable design IP

  We must be able to implement hybrid systems efficiently - model, explore, design, optimize, and integrate non-digital functionality (MEMS, NEMS, analog/RF, sensors/transducers, photonics, biological, …)

Source: 2006 Forum

66

Ever Increasing Design Flow Complexity

  Expansion of traditional RTL-to-layout DA support   Upwards: System

specification, transaction level modeling, behavioral synthesis

  Downwards: RET, OPC, yield optimization through post-layout manipulations, etc.

  In between: more and more complex optimizations

System Level Register Transfer Level

Gate Level Transistor Level

Layout Level Mask Level

Des

ign

Verif

icat

ion

Source: Andreas Kuehlmann 2006 Forum

67

Most of Design Automation Today Focuses on the “Middle”

Verification Synthesis

Place & Route DFM

Analysis & Optimization

C O R E

Software System

Manufacturing

E D A

RTL Spec

GDSII

Source: Andreas Kuehlmann 2006 Forum

68

Optimization Challenges

  Optimization algorithms must be what many of today’s design automation techniques are not: stable, scaleable, and robust

  Design automation must leverage optimization technology – casting problems in optimization terms opens a new resource of partnerships in cross-disciplinary research that can lead to better optimization engines

  Optimization algorithms need to handle multiple objectives simultaneously to address critical power, variability, manufacturability,

  Techniques must globally optimize performance across layers of abstraction and diverse technologies

Source: 2006 Forum

69

Technology/Manufacturing Challenges

  Design for manufacturing must move from handling variability to robust operation in the face of failures from multiple sources

  Design tools must comprehend multiple options associated with new devices, new materials, fabrics and 3D stacking

  Communication between layout/design must go beyond sets of rules to process/manufacturing understanding at all levels.

  Tools must comprehend hybrid devices and materials as well as emerging nontraditional applications (bio, sensor, medical, etc.)

  Design techniques addressing these late-CMOS technology challenges must bridge to beyond-CMOS nanotechnologies as well

Source: 2006 Forum

70

Recommendations

  Since design automation is critical to advancing our computing capability for the 21st century:

  NSF should support a collaborative platform for design automation research pushing towards beyond-CMOS technologies

  NSF must establish and support multidisciplinary partnerships to enable the design technology work necessary for 21st century leadership:

 enabling system-level design in partnership with the software and architecture areas

 with larger-scale, more robust optimization to provide more complex systems and keep on Moore’s Law pace

 at the nanoscale to take design technology from novel devices to system-level applications

Source: 2006 Forum

71

Why Should NSF Worry about Design Technology?

  Design will be a key differentiator for US competitiveness and national security.   US must have the most productive designers   Design costs dominate – they need to be dramatically reduced in terms of

team size, design time, etc. to maintain US lead

  National support for design research is diminishing in US, increasing elsewhere.   China, Europe, Taiwan, and Canada all support university-based design

research infrastructure   National strategy in design needs to match national investment in

materials and technologies   Education funding must help supply trained scientists and engineers

  Moore’s Law is a critical enabler for advances in computing and its future depends on design   Materials and process technology alone cannot keep us on the Moore’s

Law curve.   Advanced applications – DNA sequencing, astrophysics, cryptography –

rest on this computational foundation Source: 2006 Forum

The 2006 Forum – A Report Card A National Design Initiative (NDI)

System design science Robust optimization methodologies Interface to manufacturing

Collaborative research framework: Access to leading edge fabrication technologies A computational discovery environment Opportunities for design of innovative integrated electronic systems $50M per year for five years through a cross-directorate initiative by NSF

INC INC

INC

INC

B

B

?

C

INC

What’s New (Well, Not Really New)

•  New emphasis on parallelism

•  New ITRS design and software emphasis

•  New focus on applications

•  New post-CMOS technologies

•  New (old) predictions about the death of EDA

The Sequential Peril Cores not faster + no parallel improvement

SW not faster no new PC sales

except for wearout sales drop 250M

50M

Source: Dave Patterson, SRC, 2004

0

50

100

150

200

250

1985 1995 2005 2015

Millions of PCs / year

75

Compelling Laptop/Handheld Apps   Health Coach

  Since laptop/handheld always with you, Record images of all meals, weigh plate before and after, analyze calories consumed so far

  “What if I order a pizza for my next meal? A salad?”

  Since laptop/handheld always with you, record amount of exercise so far, show how body would look if maintain this exercise and diet pattern next 3 months

  “What would I look like if I regularly run 2 miles? 4 miles?”

  Face Recognizer/Name Whisperer   Laptop/handheld scans faces, matches image database, whispers name in ear (relies on Content Based Image Retreival)

Source: Dave Patterson, SRC, 2004

What Next

•  Strengthen the links between theory of computation and design automation

•  Maintain strong industry/university/government partnerships

•  Grow support for design and design automation as increasingly important contributors to the roadmap forward

The 2009 Report NSF Workshop on EDA:

Past, Present, and Future

Bob Brayton Jason Cong

The 2009 Report NSF Workshop on EDA:

Past, Present, and Future IEEE Design & Test of Computers

March/April 2010 May/June 2010

The 2009 NSF Workshop on EDA: Past, Present, and Future

Recommendations – five new research programs for NSF:

1.  Mid-scale or large-scale research efforts that couple design withEDA. support innovative design projects and couple them with leading-edge DA researchers.

2.  Joint research programs between research groups from universities, commercial EDA companies, and large systems houses.

3.  Shared infrastructure for design and DA.

4.  Exploration of DA for emerging areas.

5.  Interaction between DA and theory communities, as well as interaction between DA and mathematical sciences.

The 2009 NSF Workshop on EDA: Past, Present, and Future

Recommendations – three new education efforts:

1.  Support for development of a senior-level EDA course.

2.  Support from NSF to develop shared courseware infrastructure in EDA.

3.  An increased post-doc program to alleviate the lack of research positions for new graduates.

The 2009 NSF Workshop on EDA: Past, Present, and Future

Recommendations – four programs for industry / academic collaboration:

1.  An enhanced program to support longer-term faculty/industry interactions.

2.  An enhanced program to support summer students working at EDA companies.

3.  A program to help faculty members and graduate researchers spin off start-ups to commercialize successful research projects.

Net of all: 2.5x increase in US funding for EDA (from estimated $20M at the time)

Predictions

“ Those who have knowledge, don't predict.

Those who predict, don't have knowledge. ” - Lao Tzu, 6th Century BC

“ Prediction is very difficult,

especially about the future. ”

- Niels Bohr, 20th Century

82

Jim Hogan’s Predictions (from Lee PR interview, reported by John Cooley 01/30/14)

  Design for maximum efficiency (in terms of the SW apps that will run on these devices) rather than maximum performance.

  Differentiation will be in the software. Hardware IP or blocks will become commodities.

  Increasingly complex designs (hundreds of SW application processors per SoC).

  Overall fewer design starts, but sub-90nm starts will increase.

  100's of IP blocks per chip.

  70%+ IP re-use and majority will be 3rd-party commercial IP.

  More than 60% of chip design effort will be in software.

  Chips will have majority dark silicon with an always-on sentry.

Jim Hogan’s Predictions

  Differentiation will be in the software. Hardware IP or blocks will become commodities.

  A lot more sensors, more mixed-signal content to engage IoT

  Each major system company will make their own application-specific SoC.   As designs get more complex, managers will have to keep

buying more companies to get more engineers and IP.

  Bigger SoC and system companies will continue to acquire specialized and ongoing businesses.

  Reliance on verification at RTL won't scale.   Greater reliance on High Level C-to-RTL Synthesis (HLS)

Jim Hogan’s Predictions (continued)

86

Leon Stok, DAC 2013

87

Marching towards the end of Moore’s law, what are the three most important technology trends that will determine what type of EDA tools will be needed in the next 25 years?

Leon Stok, DAC 2013

88

Designer VisionEDA OfferingsOver-generalizedHigh complexityBut still “usable” Leon Stok, DAC 2013

89

Next Gen ProductWins the “Feature Wars”

Technically Superior in almost every wayBut no longer fits in your pocket or your hand Designer Vision is Lost

Leon Sto

Leon Stok, DAC 2013

90

What will affect your Design Environment in next 25 yrs?

Leon Stok, DAC 2013

91

Conclusions

 In the next EDA era…it is all about the DATA, much less about the algorithms

 We need to put out a bold new vision on what the next generation DATA-driven EDA era will look like.

– Only that will allow us to attract the talent to build the platforms to do this.

Leon Stok, DAC 2013

92

1989-Now: 25 Extraordinary, Successful Years

  Future: Optimistic.   One reason: I just taught world’s first EDA MOOC.

Slide 92 © Rob A. Rutenbar, 2013

Predictions

  Essential advances in EDA needed for correctness, yield, resilience, power reduction, cost containment, . . .

  Designs (and tools) will be increasingly use/application focused.

  More data that everyone wants immediately, all the time, everywhere.

  DA has a lot to bring to the table, in electronic design and elsewhere

93

From Spreadsheets to Watson

94

Ronald Reagan: The state of our union is strong. George H.W. Bush : The state of the union will remain sound and strong. Bill Clinton: The state of our union is strong. George W. Bush: The state of our union is strong, and together we will make it stronger. Barack Obama: The state of our union will always be strong.

George W. Bush: The state of our union is strong, and together we will make it stronger.