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The Off-Detector Opto-electronics for the Optical Links of the ATLAS SemiConductor Tracker and Pixel

Detector

M.L. Chu, S.-C. Lee, D.S. Su, P.K. Teng Institute of Physics, Academia Sinica, Taiwan

M. Goodrick

Cavendish Laboratory, Cambridge University, UK

N. Kundu, A.R. Weidbergi Physics Department, Oxford University, UK

M. French, C.P. Macwaters, J. Matheson

Rutherford Appleton Laboratory, UK

Abstract

The off-detector part of the optical links for the ATLAS SCT and Pixel detectors is described. The VCSELs and p-i-n diodes used and the associated ASICs are described. A novel array packaging technique is explained and an analysis of the performance of the arrays and the overall system performance is given. The proposed procedure for the set-up of the optical links in ATLAS is described. PACS: 42.88, 04.40N, 85.40, 85.60. Keywords: LHC; Optoelectronics; Data transmission; ASICs.

1. Introduction Optical links will be used in the ATLAS SemiConductor Tracker (SCT) and Pixel detector[1,2] to transmit data from the detector modules to the off-detector electronics and to distribute the Timing, Trigger and Control (TTC) data from the counting room to the front-end electronics[3]. This paper describes the performance of final prototypes of the off-detector opto-electronics. The main aim of this work was to verify the performance of the full system before starting the final production and to understand the procedures required to set up the optical links at the start of ATLAS operation. The on-detector components are described in references [4,5,6,7]. The overall system architecture of the SCT optical links is reviewed briefly in Section 2. The specifications for the VCSELs and p-i-n diodes are given in Section 3. The array packaging is a custom development, since no commercial MT coupled arrays are currently available. This development is therefore of potential interest to other applications involving many channels of fibre readout. The array packaging is described in Section 3. The ASICs used in the optical links are briefly reviewed in Section 4. The performance of the arrays and the combined performance of the arrays i Corresponding author. Email: t.weidberg1@physics.ox.ac.uk

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and ASICs were studied and the results are discussed in Section 5. The operation of the VCSEL driver ASIC to allow the minimisation of the jitter of the recovered 40 MHz bunch crossing signal is described. The proposed procedures to be used for the set-up of the system when installed in the ATLAS detector are described in Section 6. Finally some conclusions are given in Section 7.

2. System Architecture and Specifications The overall architecture of the SCT optical links is described in [1] and [3] and is briefly reviewed here for convenience. The system is illustrated schematically in Figure 1 below.

Figure 1 The ATLAS SCT optical links system architecture.

The links are based on GaAs VCSELsi emitting light around 850 nm and epitaxial silicon p-i-n diodes. There are 12 ABCD ASICs[8] on each SCT[1] module and each ABCD reads out the signals from 128 channels of silicon strips. The ABCD ASIC consists of 128 channels of preamplifiers and discriminators. The binary data from each channel is stored in a pipeline memory and the binary data corresponding to a first level trigger (L1) signal is read out. Two data links operating at 40 Mbits/s transfer the data from the ABCD ASICs on each SCT module to the off-detector opto-electronics. The ABCD ASICs[1] send the data to the VDC ASIC[6] which drives two VCSEL channels[4]. The data is sent in NRZii format via radiation hard optical fibre[7] to the p-i-n diode arrays in the Back of Crate (BOC) cardiii in the counting room. The electrical signals from the p-i-n diode arrays are discriminated by the DRX-12 ASIC which provides LVDSiv data used in the SCT Read Out Driver (ROD).

i Vertical Cavity Surface Emitting Lasers. ii Non Return to Zero. iii The BOC card provides the interface between the optical signals and the off-detector electronics in the ROD. iv LVDS: Low Voltage Differential Signals for Scalable Coherent Interface (SCI) Draft 1.3 IEEE P1596.3-1995.

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Optical links are also used to send the TTC data from the RODs to the SCT modules. The BPM-12 ASIC uses biphase mark (BPM) encoding to send a 40 Mbits/s control stream in the same channel as the 40 MHz Bunch Crossing (BC) clock. The outputs of the BPM-12 ASIC drive an array of 12 VCSELs which transmit the optical signal into 12 radiation hard fibres[7]. The signals are converted from optical to electrical by the on-detector p-i-n diodes[5]. The electrical signals from the p-i-n diodes are received by the DORIC4A ASIC[6] which discriminates the signal and decodes the BPM data into a 40 MHz BC clock and a 40 Mbit/s control data stream. The output stages translate the BC clock and control data into LVDS signals. The architecture of the optical links for the Pixel system is described in Ref.[2]. The Pixel system uses essentially the same components for the off-detector end of the optical links as the SCT. The one minor difference is that the Pixel system will use 8- way arrays, whereas the SCT uses 12-way arrays. The data links for the innermost layer (“B layer” ) of the Pixel system will be operated at 80 Mbits/s while the other layers will be operated at the same speed as those for the SCT. The studies described in this paper focussed on the SCT operation at 40 Mbits/s, although given the measured speed of the links the operation at 80 Mbits/s is not expected to pose any problems.

2.1 System Specifications Single bit errors will cause the loss of valid hits from the silicon detectors or the creation of spurious hits. The upper limit on the Bit Error Rate (BER) is specified as 10-9, as an error rate at this level would give a negligible contribution to the detector inefficiency or to the rate of spurious hits. In practice the error rate in the system has been measured to be much lower than this value (see Section 5.1.2). Since the system involves 8176 data links, it should be simple to set-up and operate with minimum adjustments. Therefore, it is important that the system should work with low BER over a wide range of the adjustable parameters. The specifications for the TTC links from the ROD to the detector are given in Table 1 below.

Table 1 Specifications for the TTC links.

Parameter Minimum Typical Maximum Units BER - <10-11 10-9 - Jitter of recovered clock (RMS)

- 0.1 0.5 ns

Single bit errors can cause a loss of level 1 triggers and it has been evaluated that a BER of 10-9 would cause a negligible loss of data[9]. At high luminosity a BER of ~ 10-10 is expected due to Single Event Upsets[9]. The actual BER for the TTC links have also been measured to be much lower (see Section 5.3.3). The requirement on the jitter of the recovered clock is based on not degrading the efficiency of the binary system used for the readout of the SCT detectors[1]. The tight specification on the timing jitter of the recovered bunch crossing clock arises from the need to assign hits

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in the detector to the correct bunch crossing while allowing for the time walk of the signal from the front-end electronics. As for the data links, it is important that a low BER can be achieved for the TTC links, over a wide range of the adjustable parameters.

3. VCSEL and p-i-n arrays

3.1 p-i-n Arrays Arrays of silicon p-i-n diodes are used to receive the readout data from the front end modules. Epitaxial silicon p-i-n diodesi are used because the i layer provides a thin active layer allowing for fast operation at low p-i-n bias voltage. The manufacturer’s specifications for the p-i-n array are given in Table 2 below.

Table 2 Specifications for the p-i-n arrays.

Character istics Min. Typical Max. Units Operating wavelength 820 840 860 nm Input optical power 1 3 mW Responsivity @ 820 –860 nm and 5V bias

0.4 0.5 A/W

Dark current <1 2 nA Reverse voltage 5 10 V Breakdown voltage 15 20 V 20%-80% Rise/Fall time at 5V bias

1 2 ns

Temperature range 10 20 50 °C (condition for package not chip)

The active area of each individual p-i-n diode is circular with a diameter of 130 µm

and the depth of the i region is 35 µm.

3.2 VCSELs VCSELs [10] are used to transmit the TTC signals to the front end modules optically. The main advantages of VCSELs are that they provide large optical signals at very low currents and have fast rise and fall times. In order to lower the laser threshold current, VCSELs use ion implants to selectively produce a buried current-blocking layer to funnel current through a small area of the active layer[11]. In older VCSELs this current confinement was achieved with proton implants. The VCSELsii used in this study have an oxide implant to achieve the current confinement, which is becoming the standard VCSEL technology as it produces lower thresholds and higher bandwidth. The one disadvantage for this application with the oxide confined VCSELs was the relatively large opening angle (the FWHM of the emitted radiation for these VCSELsiii is 150). This results in a very low coupling efficiency into the 50

i Designed by Truelight, Taiwan, manufactured by Episil ,Taiwan. ii TSA-8B12-00 Truelight, Taiwan. iii This was measured at a drive current of 6 mA.

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µm core step index multi-mode (SIMM) fibre if no lens is used. In order to achieve a higher coupled power into the SIMM fibre without the complication of the use of a lens, a special production run was made with a lower reflectivity of the emitting surface which results in a slightly higher threshold but a much larger slope efficiency. The threshold increase was rather small (~ 1mA) but there was a big increase in slope efficiency which results in a much higher optical power at a nominal drive current of 10 mA. Therefore, it was possible to obtain a typical fibre coupled power of greater than 1 mW at a drive current of 10 mA. This optical power at 10 mA is sufficient to give a noise immunity of 6.2 dB and an additional safety factor of about 1.8 dB can be obtained by running at slightly higher current. A larger amplitude optical signal also reduces the Single Event Upset (SEU) rate in the TTC system and an amplitude of 1 mW for the optical signal ensures that the resulting BER is always less than 10-9[9]. A fast rise and fall time is required for the VCSELs because the amplifier for the p-i-n diode receiver on the detector (DORIC4A) is AC coupled. The fast rise and fall times achievable with the VCSELs also helps to minimise the jitter of the recovered BC clock. The manufacturer’s specifications for the VCSEL arrays are given in Table 3 below.

Table 3 Specifications for the VCSEL arrays.

Character istics Min. Typical Max. Units Wavelength 820 ~840 860 Nm Output power coupled into 50µm core SIMM fibre @ BPM DAC setting of 165 (equivalent to 10 mA).

0.7 1.2 - mW

Threshold current 3 6 mA Forward voltage @ 10mA 2 2.5 V Reverse voltage 2 V 20%-80% Rise/Fall time 1 2 ns Temperature range 10 20 50 °C (condition for package not

chip)

3.3 Array Packaging The parts for the opto array sub-assembly are shown in Figure 2 below. An identical design is used for VCSEL and p-i-n array sub-assemblies, except for the opto array chip. The location of two precisely machined guide pins defines the alignment of fibres in an MT connector when the connector is inserted. The array chip is placed precisely on the base PCB with respect to the guide pins. The precise location between guide pins and opto array chip guarantees the alignment of the active elements of the opto array chip to the optical fibres. The opto array chips are wire bonded to the base PCB and the connection from the base PCB to the TX or RX PCBs is done via the lead frames as shown in Figure 2. The upper lead frame is used for the connections

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from the 12 individual anodes and the lower lead frame is used for the common cathode connections. A photograph of a VCSEL array mounted on a TX PCB is shown in Figure 3.

Figure 2 Schematic view of opto array package assembly

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Figure 3 Photograph of a VCSEL array mounted on a base PCB with the MT guide pins.

4. Off-Detector ASICs

4.1 DRX-12 The DRX-12 ASIC is used to discriminate the electrical signals from the p-i-n arrays to reproduce the data signals from the SCT modules (see Figure 1). The ASIC contains 12 channels, each of which consists of a comparator with an LVDS output driver. The DRX-12 was fabricated in the AMS 0.8 µm BiCMOS process using npn bipolar transistors[6]. The basic units for the design were copied from the DORIC4A[6] ASIC. The input comparators are DC coupled to allow for the NRZ data stream. Each channel of the DRX-12 has an individually adjustable threshold which can be set by an external reference voltage to correspond to an input signal amplitude in the range 0 to 255 µA. The other change to the comparators compared to the DORIC4A is that there is no hysteresis, as this is not required for a DC coupled link.

4.2 BPM-12 The BPM-12 ASIC is used to combine the 40 MHz BC clock and the 40 Mbits/s command data stream (see Figure 1). It consists of 12 channels of biphase mark encoding and VCSEL drive circuitry. Each channel has an input 40 Mbits/s data stream and there is also a common input 40 MHz system clock for all channels. The biphase mark encoding scheme is a DC balanced code which creates extra transitions to encode data “1”s as illustrated schematically in Figure 4 below. The latency between the input and output data must not be too long because of the fixed pipeline depth of the front-end electronics. The measured latency was 60 ns. The BPM-12 ASIC was also fabricated in the AMS 0.8 µm BiCMOS process but used only CMOS transistors.

Clock Input

Data Input

BPM Output

25nS

25nS

Figure 4 I llustration of the biphase mark Encoding Scheme. The top trace shows the input clock signal and the middle trace shows the input data. The bottom

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trace shows the resulting biphase mark encoded data. The data “ 1” is encoded as an extra transition in the output.

4.2.1 VCSEL Driver circuits A very simple CMOS circuit is used to drive each VCSEL. A schematic diagram of one channel of the VCSEL driver circuit is shown in Figure 5 below. An external voltage (bias) drives current through a 2kΩ resistor which is then amplified by two current mirrors each with a current gain of 4. The current to the VCSEL is switched on or off by a logical level which corresponds to the biphase mark encoded data for that channel. A small “bleed” current of around 1 mA is sent to the VCSEL during the off period in order to ensure a fast turn-on of the VCSEL. The current to the VCSEL for each channel is adjustable in the range 1 to 18 mA by means of an external voltage.

VCSEL Driver

Output

Input

Return

Bias

VddBle

ed

Figure 5 Schematic diagram of the VCSEL dr ive circuit.

4.2.2 BPM-12 Adjustments It is essential in the SCT pipelined system that the correct data for the event corresponding to a given L1 trigger is read out from the ABCD pipeline. This means that the L1 trigger must arrive at the ABCDs at the right time. This is achieved by setting the BPM-12 coarse delay register which delays the L1 signal by an integral number of clock cycles. This is performed by sending the data through flip flops clocked by the 40 MHz BC clock. It is also necessary to adjust the delay of the 40 MHz BC clock so that the phase is correct with respect to the signals generated by particles crossing the detector module. A delay can be set for each BPM-12 channel by means of a 7 bit fine delay register which changes the delay in the range 0 to 35 ns (i.e. it covers the entire 25 ns period). This delay is generated by passing the signal through a selectable number of pairs of inverters. In order to obtain an equal mark to space ratio (MSR) for the optical output, (this is necessary for the on-detector system to create a low jitter BC clock as discussed in Section 5.3.5) a MSR adjustment has been implemented which allows for the

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adjustment of the MSR of the BPM encoded data. The schematic diagram of the MSR adjustment is shown in Figure 6 below. The MSR of the signal is first reduced by connecting it to one input of an AND gate where the other input is a delayed version of the same signal. This signal is then fed to one input of an OR gate where the other input is a delayed version of the same signal. The delay for the second signal is adjustable by means of a register which controls how many pairs of inverters the signal is passed through. The effect of the OR gate is to stretch the width of the pulse so that the MSR is controlled by the length of this adjustable delay.

Fixed delay

Variable delay

AND

Delay registers

Input pulse

OR Output pulse

Mark/Space change

Figure 6 Schematic diagram of the mark to space ratio adjustment circuit in BPM-12.

4.3 RX and TX Plug-in PCBs Each RX PCB consists of a 12 channel p-i-n array with the precision mounted MT guide pins and a DRX-12 ASIC. The PCB also contains a multi-DACi for setting the thresholds for each channel. The RX PCB has a 40 pin connector to allow it to be connected to the BOC card. Similarly each TX PCB consists of a 12 channel VCSEL array and a BPM-12 ASIC. The TX PCB also contains a multi-DACi for setting the voltages which control the VCSEL drive current.

5. Array and ASIC Performance

5.1 p-i-n and p-i-n plus DRX-12 Measurements

5.1.1 Analogue measurements The rise and fall times of the bare p-i-n arrays were measured by feeding the signal from each channel of the array into a 50 Ω resistor and displaying the voltage across the resistor on an oscilloscope. The rise and fall times as a function of p-i-n bias voltage, for one channel of one array are shown in Figure 7 below and the results from other channels on this array and other arrays were very similar.

i DAC LTC1665.

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Figure 7 p-i-n 20%-80% r ise and fall times as a function of p-i-n bias.

Figure 7 shows as expected that a fast response could be obtained for a p-i-n bias voltage of 5V. The p-i-n responsivity was measured at a p-i-n bias of 5V and the resulting distribution of responsivities is shown in Figure 8 below. The distribution of the responsivities measured on the bare die array is very uniform, so the measured spread is probably due to the MT optical connector.

PIN Responsivity

0

5

10

15

20

25

30

0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 More

Responsivity (A/W)

Freq

uenc

y

Figure 8 Distr ibution of p-i-n responsivities at a p-i-n bias voltage of 5V.

PIN Rise and Fall Times

0

1

2

3

4

5

6

7

8

0 2 4 6 8 10 12 PIN Bias (V)

Time (ns)

Rise Time Fall Time

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5.1.2 Digital p-i-n/DRX-12 Measurements In order to measure the performance of the combined p-i-n diode/DRX-12 system a series of Bit Error Rate (BER) measurements were performed using a prototype SCT opto-harness as the source of 12 data streams. The opto-harness consists of 6 opto-flex cables connected to 6 low mass aluminium power tapes. An opto-package containing two VCSELs and one p-i-n diode[12,13], a DORIC4A and a VDC ASIC are mounted on each opto-flex cable[14]. The performance of the system was studied as a function of p-i-n bias voltage in order to determine the lowest voltage that gave good performance. This was required in order to define the scheme used to apply the p-i-n bias voltage in the final ATLAS configuration with the BOC. Scans of BER versus RX threshold DAC value were made at different p-i-n bias voltages. Measurements of the number of errors as a function of the time delay between the recovered data stream and the reference data stream were also performed. The BER measurements done at this stage were just used to determine the width of the possible operating range. The BER at each scan point was determined from sending 32k bits of pseudo-random data. Later measurements were performed to determine the BER after the optimised values of the parameters had been set. The results of the BER scans versus RX DAC value for p-i-n bias voltages in the range 0 to 4V are shown in Figure 9 to Figure 11 below. The results of scans with higher p-i-n bias voltages looked very similar to the results obtained at 4V.

BER Scan PIN Bias 0V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 50 100 150 200 250 300

RX DAC

BE

R

channel 1

channel 2

channel 3

channel 4

channel 5

channel 6

channel 7

channel 8

channel 9

channel 10

channel 11

channel 12

Figure 9 BER versus RX DAC value for p-i-n bias of 0V for different data channels on one RX PCB.

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BER Scan PIN Bias 2V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 50 100 150 200 250 300

RX DAC

BE

R

channel 1

channel 2

channel 3

channel 4

channel 5

channel 6

channel 7

channel 8

channel 9

Figure 10 BER versus RX DAC value for p-i-n bias voltage of 2V for different data channels on one RX PCB.

BER Scan PIN Bias 4V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 50 100 150 200 250 300

RX DAC

BE

R

channel 1

channel 2

channel 3

channel 4

channel 5

channel 6

channel 7

channel 8

channel 9

Figure 11 BER versus RX DAC value for p-i-n bias of 4V for different data channels on one RX PCB.

The errors observed at low DAC values are caused by the finite rise and fall time for the p-i-n diode signal and are therefore more frequent at lower values of the p-i-n bias voltage. The errors observed at high DAC values for one channel correspond to the threshold becoming larger than the magnitude of the signal. This was a result of a lower level of incoming light signal for that channel. Not surprisingly, there is a clear improvement in going from a p-i-n bias of 0V to 2V. There is a slight improvement in going from 2V to 4V but after that there is no clear evidence of any further improvement. In order to summarise the data in one figure the

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results of the BER measurements versus RX DAC value for one channel, at different p-i-n bias voltages, are shown in Figure 12 below.

BER Scans vs PIN Bias

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.00 50.00 100.00 150.00 200.00 250.00

RX DAC

BE

R

0V

2V

4V

6V

8V

10V

12V

14V

Figure 12 BER scans versus RX DAC value for channel 0, at different p-i-n bias voltages.

5.2 2D Scans There was no analogue output from the DRX-12 ASIC. Therefore, in order to understand further the system performance, the BER measurements were made as a function of RX DAC value and the relative delay between the reconstructed and reference data. The range of time delays with no bit errors was determined and this width is plotted as a function of p-i-n bias voltage, for one channel of an RX PCB and for two different values of the RX threshold DAC, in Figure 13 below.

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Width of 0 Errors vs PIN Bias Voltage

0

5

10

15

20

25

0 2 4 6 8 10 12 14 16

PIN Bias (V)

Wid

th (

ns)

DAC=255DAC=104

Figure 13 Width of the region in the timing scan with 0 bit er rors as a function of p-i-n bias voltage for two different settings of the RX DAC value.

The results of a 2D scan of BER versus RX DAC value and timing setting are shown in Figure 14 below.

5 10 15 20 25 30

50

100

150

200

250

PIN Bias 2V

Timing (ns)

RX

DA

C V

alue

0

1.000

4500

6750

9000

1.125E4

1.35E4

1.575E4

1.8E4

Figure 14 Number of bit er rors versus RX DAC value and timing setting for array C000 channel 0 at a p-i-n bias of 2V.

The figure shows that the range of the time delay values which result in no bit errors is greatly reduced at low DAC value, compared to higher DAC values. This corresponds to the slow tail in the analogue signal at low p-i-n bias voltage. The equivalent plot for a p-i-n bias of 4V is shown in Figure 15 below and shows a much better performance.

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There was no clear improvement in the plot as the p-i-n bias voltage was increased above 4V.

5 10 15 20 25 30

50

100

150

200

250

PIN Bias 4V

Timing (ns)

RX

DA

C V

alue

0

1.000

4500

6750

9000

1.125E4

1.35E4

1.575E4

1.8E4

Figure 15 Number of bit er rors versus RX DAC value and timing setting for array C000 channel 0 at a p-i-n bias of 4V.

In order to compare the performance more quantitatively, the range of the delay values in which there were no bit errors was calculated as a function of RX DAC value. The results for one channel are shown for different p-i-n bias voltages in Figure 16 below.

C004 channel 0

0

5

10

15

20

25

0 50 100 150 200 250 300

RX DAC

Ran

ge

of

0 E

rro

rs (

ns)

2V4V6V

Figure 16 Range of timing scan with no bit er rors as a function of RX DAC value for array C000, channel 0 at different p-i-n bias voltages (see legend).

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These results show a clear improvement in performance when increasing the p-i-n bias voltage from 2V to 4V, but there is no evidence for any further improvement at higher p-i-n bias voltages. In order to summarise the performance for a given array at a particular p-i-n bias voltage, the number of bins in the 2D scan with no bit errors was counted. The results are shown for the sample of 10 p-i-n arrays used in Figure 17 below.

Number Zero Error Bins

0

500

1000

1500

2000

2500

3000

3500

4000

4500

0 2 4 6 8 10 12 14 16

PIN Bias (V)

Nu

mb

er b

ins

C001-c0C001-c6C002-c0C003-c0C004-c0C005-c0C006-c0C007-c0C008-c0B000-c0B001-c0

Figure 17 Number of bins in the 2D scan of BER versus RX DAC and timing setting with no bit er rors as a function of p-i-n bias voltage, for selected channels of the 10 p-i-n ar rays used.

For all the p-i-n arrays the performance improves with p-i-n bias voltage but no further improvement is observed for a p-i-n bias above 6V. There is some variation in the performance of the devices at low p-i-n bias voltages but the performance for all devices is very similar for a p-i-n bias above 6V. The BER was then measured for the data links at a p-i-n bias voltage of 7.9V and optimised values for the timing and RX DAC settings. No errors were recorded during a readout time of 10 minutes for each of the 12 data streams on 60 production opto-harnessesi. Therefore, the 90% c.l. upper limit on the BER is 1.3 10-13, which is comfortably below the system specification of 10-9.

5.3 VCSEL and BPM-12 measurements

5.3.1 Optical Power Measurements The power output of the VCSELs as a function of drive current is approximately linear from the threshold around 4 mA up to 10 mA and then starts to saturate and reaches a maximum at a current around 18 mA. The mean time to failure (MTTF) of the VCSELs decreases with the operating current. Therefore the nominal current for

i These longer measurements were done with two RX PCBs and the data was accumulated over several data sources during testing of production opto-harnesses.

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the VCSELs was chosen to be 10 mA but an additional 50% of power can be obtained if required by operating at a current of 18 mA. The amplitude of the optical signal is a critical parameter, as discussed in Section 3.2. The distribution of the amplitudes with the lasers coupled to 50 µm core SIMM fibre and with the drive currents set at 10 mA is shown in Figure 18 below.

VCSEL Power

0

1

2

3

4

5

6

7

8

700

900

1100

1300

1500

1700

1900

2100

2300

2500

2700

2900

More

Coupled Power (µµµµW)

Fre

qu

ency

Figure 18 Distr ibution of coupled optical power for all channels of a sample of 7 VCSEL arrays with a dr ive current of 10 mA.

There is a very broad distribution of optical power but all channels gave an optical power above 700 µW at 10 mA. Some of the spread is due to the efficiency of the coupling of the light from the VCSEL into the fibres.

5.3.2 Speed Measurements It is essential to have fast rise and fall times for the optical pulses in order to minimise the jitter on the resulting recovered 40 MHz BC clock. The outputs of the VCSELs are guaranteed to be very fast from the manufacturers specifications. The electrical outputs of the BPM-12 were designed to give rise and fall times of 1 ns and this was verified with electrical measurements. It is however still essential to ensure that the rise time of the optical signal resulting from the combined BPM-12 and VCSEL system was still sufficiently fast. The measurements of the rise and fall times were all done using a fast optical probei, with an optical attenuator to ensure that the signal was well below the saturation level

i Tektronix O/E converter P6701B.

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for the probe. The measurements were not corrected for the bandwidth of the probe (700 MHz) nor of the oscilloscope (300 MHz). The distributions of the rise and fall times are shown in Figure 19 and Figure 20 below. The distributions show that the rise and fall times are peaked around 1 ns, and are well below 2 ns.

Rise Time

0

5

10

15

20

25

30

020

040

060

080

010

0012

0014

0016

0018

0020

00

Time (ps)

Fre

qu

ency

Figure 19 Distr ibution of 20%-80% r ise times for all VCSEL channels dr iven at 10 mA.

Fall Time

05

1015202530354045

020

040

060

080

010

0012

0014

0016

0018

0020

00

Time (ps)

Freq

uenc

y

19

Figure 20 Distr ibution of 20%-80% fall times for all VCSEL channels dr iven at 10 mA.

Some channels had an apparently slower rise time, but the significance of this is not so obvious as the signals always had a fast component and then a slow tail. Examples of two cases are shown in Figure 21 and Figure 22 below. Figure 21 is for a channel for which the rise and fall time were below 1ns and Figure 22 is for a channel with a rise time above 1ns.

TD007 Fibre 4

0.0E+00

1.0E+02

2.0E+02

3.0E+02

4.0E+02

5.0E+02

6.0E+02

7.0E+02

0 10 20 30 40 50 60 70 80 90 100

Time (ns)

Ou

tpu

t (a

.u.)

Figure 21 Oscilloscope picture of optical signal for fibre 4 of TD007 (r ise time = 0.64 ns, fall time = 0.86 ns).

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TD001 Fibre 4

0

100

200

300

400

500

600

700

800

900

0 10 20 30 40 50 60 70 80 90 100

Time (ns)

Ou

tpu

t (a

.u.)

Figure 22 Oscilloscope picture of optical signal for fibre 4 of TD001 (r ise time = 1.60 ns, fall time= 0.86 ns).

Since the DORIC4A is ac coupled with a threshold close to 0, we might well expect that the digital performance will still be very good even for the apparently slower channels.

5.3.3 BER Measurements The central 6 channels of 9 VCSEL arrays were used to perform BER measurements as a function of laser DAC setting using the same prototype opto-harness as used previously (see section 5.1.2). As for the data links, quick scans were first performed to determine the region of parameter space in which the links worked. The BER at each scan point was determined from sending 32k bits of pseudo-random data and comparing the data read back with the data sent. Later measurements were performed to determine the BER after the optimised values of the parameters had been set. The parameters that were studied were the value of the DAC setting for the TX (this controls the current in the VCSEL) and the time delay between the recovered 40 Mbit/s data stream and the reference data. All channels worked very well on all arrays. The range of timing delays which gave no errors was typically 20 or 21 ns (compared to a maximum possible value of 25 ns for a 40 Mbit/s data stream) and was never less than 19 ns. The results of the BER measurements for the TTC links for the 6 central channels of one of the arrays are shown in Figure 23 and the other 8 arrays showed very similar performance.

21

BER Scan TD000

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 50 100 150 200 250 300

TX DAC

BE

R

VCSEL 4VCSEL 5VCSEL 6VCSEL 7VCSEL 8VCSEL 9

Figure 23 TTC BER scan versus TX DAC value for TX TD000.

From these BER data it can be seen that all 6 channels tested work very well. The turn on of the system at around a TX DAC setting of 100 corresponds to a VCSEL drive current of about 5 mA. This is above laser threshold for these arrays but corresponds to the minimum value for which the BPM-12 driver circuit gives a reasonable output signal. The channels which have non-zero BER at high TX DAC values correspond to channels with a coupled power above 2 mW. The power reaching the p-i-n diode during ATLAS operation will be lower by about 2 dB because of the attenuation in the fibre and the extra MT connector in the routing between the detector and the counting room. Therefore, the errors occurring at very high DAC value would not be seen in ATLAS operation. The BER was then measured for the TTC links using optimised values for the timing and TX DAC settings. No errors were recorded during a readout time of 10 minutes for each of the 6 TTC data streamsi on each of 60 production opto-harnesses. Therefore, the 90% c.l. upper limit on the BER is 2.7 10-13, which is comfortably below the system specification of 10-9.

5.3.4 Mark to Space Ratio The MSR of the VCSEL optical signal needs to be close to 50:50 in order to maintain a low clock jitter. With biphase mark encoded data, the DORIC4A creates clock pulses from both edges of the 20 MHz clock. Therefore, if the MSR is not equal to 50:50 there will be two “ families” of recovered 40 MHz clock, one with a period shorter than 25 ns period and one with a longer period, which effectively creates jitter

i These longer measurements were done with two TX PCBs at the same time as the long BER measurements were done for the data links (Section 5.2).

22

in the clock. This is illustrated schematically in Figure 24 where the effect of an extremely low MSR creates a short clock period followed by a long clock period.

Figure 24 The effect of unequal mark to space ratio of the TTC signal on the recovered 40 MHz BC clock. (A) shows a BPM signal with a low mark to space ratio and (B) shows the resultant clock that would be recovered by DORIC4A.

The optimal MSR register value to obtain a 50:50 MSR for the electrical output of the BPM-12 was measured for every channel for a sample of BPM-12s as a function of BPM-12 fine delay (see Section 4.2.2). Increasing the fine delay increases the number of pairs of inverter gates the BPM signal passes through and since each inverter can slightly distort the signal, this can affect the MSR. The results for one channel are shown in Figure 25 below.

23

Figure 25 Optimal value of the BPM-12 mark to space register value versus the BPM-12 fine delay register value.

A linear fit was made to determine the intercept (ie the optimal value of the MSR register at a fine delay of 0) and the slope (ie the change in the optimal value of the MSR register with fine delay). The distributions of these intercepts and slopes for all channels for a batch of ~ 100 BPM-12s is shown in Figure 26 and Figure 27 below.

24

Optimal MSR Setting

0

50100

150200

250300

350

12 12.4

12.8

13.2

13.6 14 14

.414

.8M

ore

Fitted MSR Value

Fre

qu

ency

Figure 26 Distr ibution of intercepts of the linear fit of optimal mark to space register versus fine delay.

25

0

50

100

150

200

250

300

350

400

0.07

0.07

20.

074

0.07

60.

078

0.08

0.08

20.

084

0.08

6M

ore

Slope MS fit

Fre

qu

ency

Figure 27 Distr ibution of slopes of the linear fit of optimal mark to space register versus fine delay.

The mean and standard deviations of the distributions of fitted intercepts and slopes are given in Table 4 below.

Table 4 Summary of fits of optimal MSR register setting versus fine delay scans.

Fitted Parameter Mean Standard Deviation Intercept 13.29 ± 0.03 0.294 Slope 0.0761 ± 0.0003 0.0030 The mark to space ratio of the electrical output will in general be distorted by the VCSELs. Therefore, it is also necessary to study the MSR of the optical signal out of the TX PCBs. The positive duty cycles of the optical output of the central 6 channels for one of the TXs were measured as a function of the MSR register setting and the results are shown in Figure 28 below. All channels show similar behaviour and the optimal value of the MSR register is 17. With the MSR register set to a value of 17,

26

the positive duty cycle was measured on all channels from 7 TXs and the resulting histogram is shown in Figure 29 below.

Mark to Space Ratio

40

42

44

46

48

50

52

54

56

0 5 10 15 20 25 30

M:S register

Po

siti

ve d

uty

cyc

le %

Fibre 4

Fibre 5

Fibre 6

Fibre 7

Fibre 8

Fibre 9

Figure 28 Adjustment of duty cycle with the MSR register setting.

0

5

10

15

20

25

30

35

49 49.2 49.4 49.6 49.8 50 50.2 50.4 50.6 More

Positive Duty Cycle (%)

Fre

qu

ency

27

Figure 29 Distr ibution of positive duty cycle for the output of all channels from 7 TXs with the MSR set to 17.

The distribution of positive duty cycles is very well peaked close to 50%, showing that there is very little variation within TXs or between TXs. However, it should be noted that the optimal MSR register value for obtaining an equal MSR for the optical signal (17) is different to that for obtaining the optimal MSR for the electrical signal (13).

5.3.5 BC Clock Jitter The final check that the MSR register setting is optimal is to look at the jitter of the recovered 40 MHz BC clock. This was studied for the 6 central channels of a TX by sending the optical signals to a pre-series opto-harness (see section 5.1.2) and looking at the 40 MHz clocks recovered by the p-i-n /DORIC4A. Pseudo-random data were sent to each channel so that the phase of the BPM signal was changing. The clock jitter was estimated as the peak to peak jitter visible on the oscilloscope. The estimated jitter as a function of the MSR register setting is shown in Figure 30 below.

Clock Jitter vs MSR

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 5 10 15 20 25 30 35

MSR

Clo

ck J

itte

r (n

s) Fibre 4Fibre 5Fibre 6Fibre 7Fibre 8Fibre 9

Figure 30 Jitter (full width) in the recovered 40 MHz clock as a function of MSR setting for the central 6 channels of TD007. The fine delay registers were set to a value of 0.

The optimal value of the MSR register is 14 for 5 channels but 15 for one. This optimal value differs slightly from the value of 17 which gave the closest to 50% duty cycle for the optical signal. This could be due to the difference in the response of the DORIC4A/p-i-n diode compared to the Tektronix optical probe or to the details of the algorithm used in the oscilloscope to determine duty cycle. In any case, it is the jitter measurement of the recovered clock which defines the final system performance. The jitter was measured for the 6 central channels of another 5 TXs. The optimal value varied within a TX and from TX to TX in the range 13 to 16. If one were to choose a single value for the MSR, it would be 15. The distribution of jitter for an MSR register setting of 15 is shown in Figure 31 below. If one uses the optimal MSR

28

register value for each channel then the jitter would be significantly improved, as shown in Figure 32 below. The improvement in the jitter by using the optimised MSR register setting for each channel, compared to the value of 15 for all channels is summarised in Table 5 below.

Table 5 Summary of j itter measurements for the recovered 40 MHz BC clock. The errors quoted are purely statistical.

Full width jitter (ns) MSR=15 Optimised MSR Mean value 0.61 ± 0.04 0.43 ± 0.02 Standard deviation 0.20 0.12 Maximum value 1.08 0.68 From the results shown in Table 5, using an optimal MSR register setting does give a significant improvement in the jitter. However, even using a common value of the MSR settings for all channels gives reasonably good performance, as the RMS is still typically well below 0.5 ns.

Jitter MSR=15

0

1

2

3

4

5

6

7

8

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 More

Full width Jitter (ns)

Fre

qu

ency

Figure 31 Distr ibution of the full width of the j itter of the recovered clock for a common MSR register setting for all channels.

29

Optimised Jitter

0

2

4

6

8

10

12

14

0.3 0.4 0.5 0.6 0.7 0.8 0.9 More

Full Width Jitter (ns)

Fre

qu

ency

Figure 32 Distr ibution of the full width of the j itter of the recovered clock for an optimised MSR setting for each channel.

In order to understand if the variation between TX channels depended on which p-i-n diode/DORIC4A was used, the results for TX PCB were repeated with the MT connector reversed. The results were significantly different which suggests that even if a full calibration was done for each TX channel, a final calibration would have to be done for each channel in ATLAS (the proposed procedure for performing this calibration in-situ during ATLAS operation is discussed in Section 6.3). Finally, the value of the BPM-12 fine delay was changed from 0 to 85 (corresponding to the maximum useful fine delay of 25 ns) and the clock jitter was measured as a function of the MSR register setting and the results shown in Figure 33 below. This shows that the optimal MSR register setting for a fine delay setting of 85 is changed by 6 to 7 counts compared to that for a BPM-12 fine delay setting of 0 (see Figure 30). This is in good agreement with the measured slopes (see Figure 27) which would predict a change of 85*0.076=6.5 counts.

30

Jitter vs MSR for Fine Delay=85

0

0.2

0.4

0.6

0.8

1

1.2

1.4

18 19 20 21 22 23 24

MSR

Jitt

er (

ns)

Fibre 4Fibre 5Fibre 6Fibre 7Fibre 8Fibre 9

Figure 33 Jitter (full width) in the recovered 40 MHz clock as a function of MSR register setting for the central 6 channels of one TX PCB. The BPM-12 fine delay register was set to a value of 85.

6. System Set-up for ATLAS Configuration A simple and reliable procedure will be required for setting up the 8176 RX and 4088 TX links when the SCT is installed inside the ATLAS detector. The proposed procedure is based on that successfully used for the operation of the optical links in the SCT system test[15]. The proposed procedures for setting up the system to obtain low BER for the TTC and data links are described in Section 6.1. The proposed procedure for setting up the timing for the ABCDs is described in Section 6.2.The minimisation of the jitter of the recovered 40 MHz BC clock is described in Section 6.3.

6.1 RX and TX set-up The currents for the on-detector and off-detector VCSELs will be set to a nominal value of 10 mA. These currents will be maintained as long as possible in order to maximise the MTTF of the VCSELs and the currents will only be increased if required by radiation damage induced deterioration of the VCSELs. When the ABCD ASIC is first powered up it will be in clock/2 mode[16], which means that a 20 MHz clock should be returned down the data links. The RX DAC value can then be scanned while the ROD looks for the presence of the 20 MHz clock. The minimum and maximum value of the RX DAC for which the ROD detects the presence of a correct 20 MHz clock will be determined and the RX DAC will be set to half way between these two extreme values. The ROD can then be used to write known data into the ABCD mask register and to read this data back. A scan will then be made of the timing delay between the RX data in the ROD and a local copy of the 40 MHz BC clock. By comparing the returned mask register data with the data that was written to the register, a very simple BER measurement can be performed. The minimum and maximum values of the timing delay which produce no bit errors will be determined

31

and the timing delay will then be set to the optimal value, half way between the two extreme values.

6.2 L1 latency and BC Clock Timing In order for the pipelined system to read out the correct event corresponding to each first level trigger (L1), it will be necessary to know the delays in all parts of the system. The optical delays in the long lengths of fibre cables will be directly measured during installation and the delays in the short fibre lengths on the detector can be calculated with sufficient accuracy from the known fibre lengths. The coarse delay in the BPM-12 ASIC (see Section 4.2.2) can then be used to ensure that the L1 signal arrives at the ABCDs on a module at the correct time. The setting of the BPM-12 coarse delay can be verified by scanning this delay during LHC running using the known pattern with which machine bunches are filled[17]. To optimise the efficiency of the SCT it will be necessary to set accurately the timing of the BC clock for the ABCDs to have the correct phase with respect to the particle signals in the detector. This timing can be adjusted with the BPM-12 fine delay (see Section 4.2.2). During beam running at LHC the SCT detector hit efficiency can be measured as a function of this timing in order to determine the optimal setting of the BPM-12 fine delay. After the BC clock delays have been changed, it will be necessary to re-optimise the timing of the local copy of the 40 MHz BC clock in the ROD (see Section 6.1)

6.3 Minimisation of Jitter of Recovered 40 MHz BC Clock This in-situ calibration could be performed using the clock/2 mode in which the ABCD chips return a 20 MHz clock to the data links. The width of the “on” period of this signal should be 25ns for the optimal MSR register setting. The measurement would then be repeated after a single “1” had been sent in order to flip the phase of the biphase mark signal. The difference between the results of the width of the scans between the two phases would then be a measure of the unequal mark to space ratio of the VCSEL signal. Therefore, by adjusting the MSR register until this difference was minimised, the optimal MSR register setting could be determined.

7. Conclusions The design of the off-detector opto-electronics for the SCT and Pixel optical links has been presented. A novel array packaging was developed. Detailed analogue and digital studies of the data and TTC links have been performed. The data links work well for a p-i-n array bias voltage above 2V but require a p-i-n array bias greater than about 6V to produce the optimal performance. The TTC links work well over a large range of VCSEL drive currents. A very low jitter can be obtained on the recovered 40 MHz BC clock, provided the BPM-12 mark to space adjustment system is used. Simple procedures to set up the large number of data and TTC links in ATLAS have been described.

8. Acknowledgements This work was supported by the National Science Council of Taiwan, ROC. Financial support from the UK Particle Physics and Astronomy Research Council is gratefully

32

acknowledged. We would like to thank Neil Falconer at the Rutherford Appleton Laboratory for help with testing the DRX-12 ASICs. We thank Peter Phillips of the Rutherford Appleton Laboratory for very useful discussions on the ABCD ASICs and the SCT RODs. References 1 ATLAS Inner Detector Technical Design Report, CERN/LHCC/97-16/17. 2 ATLAS Pixel Detector Technical Design Report, CERN/LHCC/98-13. 3 D.G. Charlton et al., System Test of Radiation Hardness of Optical Links for the ATLAS SemiConductor Tracker, Nucl. Instr. and Meth. A443 (2000) 430. 4 P.K. Teng et al., Radiation hardness and lifetime studies of the VCSELs for the ATLAS SemiConductor Tracker, Nucl. Instr. and Meth. A497 (2003) 294. 5 D.G. Charlton et al., Radiation Hardness and Lifetime Studies of the Photodiodes for the Optical Readout of the ATLAS SCT. Nucl. Instr. and Meth. A 456 (2000) 292. 6 D.J. White et al., Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS SemiConductor Tracker, Nucl. Instr. and Meth. A457 (2001) 369. 7 G. Mahout et. al., Irradiation Studies of multimode optical fibres for use in ATLAS front-end links, Nucl. Instr. and Meth. A446 (2000) 426. 8 W. Dabrowski, Progress in development of the readout chip for the ATLAS SemiConductor Tracker, Proceedings of the 6th Workshop on Electronics for LHC Experiments, Cracow, Poland, 11-15 September 2000, CERN/LHCC/2000-041. 9 J.D. Dowell et al., Single event upset studies with the optical links of the ATLAS SemiConductor Tracker, Nucl. Instr. and Meth. A481 (2002) 575. 10 A. Yariv, Optical Electronics in Modern Communications, OUP, Fifth Edition 1997. 11 T.E. Sale, Vertical Cavity Surface Emitting Lasers, John Wiley and Sons 1995. 12 A.R. Weidberg, SCT Optical Links, Radiation Hard Optical Links for the ATLAS SCT and Pixel Detectors, Proceedings of the 6th Workshop on Electronics for LHC Experiments, Cracow, Poland, 11-15 September 2000, CERN 2000-010. 13 SCT opto-package, EDMS note ATL-IS-AT-009, available from https://edms.cern.ch/cedar/plsql/edmsatlas.home. 14 J. Matheson, Status Report on SCT links, Proceedings of the 8th Workshop on LHC Electronics, Colmar, France, 9-13 September 2002, CERN-LHCC-G-014. 15 P. Phillips, SCT System Performance of ATLAS SCT Modules, Proceedings of the 8th Workshop on LHC Electronics, Colmar, France, 9-13 September 2002, CERN-LHCC-G-014. 16 ABCD specifications http://chipinfo.web.cern.ch/chipinfo/docs/abcd3t_spec_v1.2.pdf. 17 See Injection/Filling schemes at http://lhc-new-homepage.web.cern.ch/lhc-new-homepage/