The MGPA ECAL readout chip for CMS

M. Raymond, Imperial College London IEEE NSS, Rome 2004 1

The MGPA ECAL readout chipfor CMS

Mark Raymond, Geoff Hall, Imperial College London, UK.Jamie Crooks, Marcus French, Rutherford Appleton Laboratory, UK.

IEEE Nuclear Science Symposium, Rome 2004

Multi–Gain Pre-Amplifier - 0.25 m CMOS chip for CMS ECAL

OUTLINEIntroduction & backgroundDesignMeasured PerformanceConclusions


CMS Electromagnetic Calorimeter

ECAL X-section PbWO4 crystals

~ 75,000 Lead Tungstate scintillating crystals 60,000 barrel, 15,000 end-cap

Hostile radiation environment

ionizing neutrons

barrel 10 kGy 2.1013 n/cm2

end-cap 25 kGy 5.1013 n/cm2

2.2 x 2.2 cm2

23 cm

ECAL

barrel end-cap

Compact Muon Solenoid

PbWO4 crystals


Crystal Readout

2 different types

Barrel - Avalanche Photodiode (APD) good for high transverse magnetic field not so radiation hard 2/crystal -> ~ 200 pF detector capacitance 60 pC full-scale signal

End-cap - Vacuum Photo-Triode (VPT) better radiation hardness OK for lower transverse magnetic field in end-cap v. low capacitance but cabling adds ~ 50 pF 16 pC full-scale signal

challenge for front end readout chip 2 different signal sizes and input capacitance prefer to have just one chip for both

APDs

VPT


BackgroundCMS ECAL dynamic range requirement ~ 16 bits to cover range from noise to full-scale signal

General approach use multiple gain ranges -> high resolution with only 12 bit ADC only transmit value for highest gain channel-in-range => have to take decision on front end every 25 ns (LHC bunch spacing)

Earlier version of CMS ECAL architecture range decision taken in preamplifier (complex chip), followed by single channel commercial ADC

New architecture proposed following major ECAL electronics review, early 2002 3 parallel gain channels (MGPA), multi-channel ADC, range decision taken by logic in ADC chip use 0.25 m CMOS to achieve:

system simplifications: single 2.5V supply for all on-detector chips, power savingswell known radiation hardnessshort production turnaround, high yield, cost savings

Short timescale for development design begun mid 2002, first submission early 2003, fortunately worked well final version (only minor design revisions) available Spring 2004

1

6

12

MGPA

12 bits

2 bits

range

LOGIC

Multi-channel ADC

12 bit ADCs

APD/VPT


MGPA Target Specifications

Parameter Barrel (APD) End-Cap (VPT)

fullscale signal 60 pC 16 pC

noise level (ENC) 10000e (1.6 fC) 3500e (0.56 fC)

input capacitance ~ 200 pF (APD) ~ 50 pF (cable)

output signals

(to match ADC)

differential 1.8 V, 0.45 V around Vcm = Vdd/2 = 1.25 V

gain ranges 1, 6, 12 10 %

pulse shaping 40 ns CR-RC

nonlinearity

(each range)

< 0.1 % fullscale

pulse shape matching

(Vpk-25)/Vpk

< 1 % within and across gain ranges

Barrel/Endcap read out using APD/VPT different capacitance and photoelectric conversion factors

3 gain ranges (1:6:12) sufficient to deliver required physics performance

40 ns pulse shaping trade-off betweenpile-up and noise (25 ns LHC bunch spacing)

linearity and pulse shape matching specsdemanding

Vpk-25 Vpk


MGPA Architecture

RF

RG1

diff. O/P stages

CF

VCM

CI

RI

gain stages

RI

DAC

I2C andoffset

generator

ext.trig.

input stage CF chosen for max. poss. gain depending on barrel/end-cap RF chosen for 40 ns decay avoids pile-up CFRF external components => 1 chip suits barrel & end-cap

differential current O/P stages external termination 2RICI = 40 nsec. => low pass filtering on all noise sources within chip

3 gain channels 1:6:12 set by resistors (on-chip), for linearity, feeding common- gate stages

I2C interface to program: output pedestal levels DAC for test pulse (ext. trig.)

CCAL

RG2

RG3I/P

VCM

CI

RI

RI

VCM

CI

RI

RI

RFCF

i

i

i

input stagecharge amp.

VCM


Noise Sources

input stage high Cf (low gain) to cope with large full-scale signals => corresponding low Rf for 40 ns time const. => Rf noise dominates over input FET

barrel ENC

(CIN=200pF)

end-cap ENC

(CIN = 50 pF)

Rf noise 4900 e 2700 e

I/P FET 1800 e 660 e

total 5220 e 2780 e

gain stage contribution can’t avoid for low gain range (RG big) but this range only used for larger signals so signal/noise still acceptable

482106.1

718.2222222

19

cgGfGfTOTFET

f

iRCRkTCCv

R

kTENC

input stage

RG

common-gategain stage

iCG

iRGCIN

vFET

sourcefollower

diff.outputstage

vRf Rf

Cf


Chip Layout

I2C

1st stage

highgainstage

diff. O/P stage

offset gen.

layout issues

gain channels segregated as much as poss. with separate power pads -> try to avoid inter-channel coupling

lots of multiple power pads

die size ~ 4mm x 4mm

packaged in 100 pin TQFP (14mm x 14mm)midgainstage

lowgainstage

diff. O/P stage

diff. O/P stage


Test Bench

pulsegen.

prog.attenuator

14-bitVMEADC

MGPAtest

board

automated, controlledby PC running LabVIEW

14-bit VME ADC need high precision to measure performance to 12-bit level

MGPA socketed on test boardallows chip to chip comparisonwithout change of externalcomponents

prog.delay


Measured Output Pulse ShapesV

olts

time [nsec]

low gainrange

mid gainrange

high gain range

differential O/P signalsfrom all 3 gain ranges

0 – 60 pC, 40 steps(logarithmic spacing)

no signs of distortion in lower gain rangeswhen higher rangessaturate

=> effective gain channel separation in layout

gain ratios 1 : 5.6 : 11.0 (c.f. 1 : 6 : 12)

lin

ear

r an

ge


Nonlinearity

-0.2

0.0

0.2

6040200

-0.2

0.0

0.2

12840

-0.2

0.0

0.2

6543210

-0.2

0.0

0.2

6040200

-0.2

0.0

0.2

1086420

-0.2

0.0

0.2

6543210

MGPA Version 1 MGPA Version 2

Nonlinearity given by:

pk.pulse height – fit (to pk.ht.) fullscale signal

10 chips measured for eachMGPA version

v. similar results V1 cf. V2

nonlinearity within (or close to)± 0.1% specification

Non

linea

rity

[% f

ulls

cale

]

Non

linea

rity

[% f

ulls

cale

]

charge injected [pC] charge injected [pC]

high gain range

mid

low

mid

low

high


1

0

norm

. pu

lse

ht.

250200150100500[nsec.]

1.5

1.0

0.5

0.0

1.5

1.0

0.5

0.0

[vol

ts]

1.5

1.0

0.5

0.0

250200150100500[nsec.]

Pulse Shape Matching

high

mid

low

normalise all 33pulse shapesto max pulse ht.and superimpose

Vpk

Vpk-25

(Average PSMF = average over all pulse shapes for all 3 gain ranges)

PSMF = Vpk-25

Vpk

Pulse Shape Matching = (PSMF – Average PSMF) Average PSMF

-1.0

0.0

1.0

PS

M [

%]

1.51.00.50.0peak pulse height [volts]

lowmidhigh± 1% spec.

Output pulses spanningfull-scale range for all 3gains (11 / range)


4000

3000

2000

1000

060402002001000

Noise

10000

8000

6000

4000

2000

02001000

EN

C [

rms

elec

tron

s]

added capacitance [pF] added capacitance [pF]

6040200

high gain chan. mid gain chan. mid gain chan.high gain chan.

weak dependence on input capacitance as expected

within spec. for high and mid-gain ranges: barrel < 10000 e, end-cap < 3500 e

low gain range:barrel: 27300 e ± 12% end-cap: 8200 e ± 11%completely dominated by gain stage noisebut signals large => electronic noise not significant (< 0.2% contribution to overall energy res’n.)

BARREL END-CAP

7240+5.8/pF 3040+4.5/pF 3270+4.5/pF7870+4.9/pF


Radiation Tests

10 keV X-rays (spectrum peak) , dosimetry accurate to ~ 10%, doserate ~ 1 Mrad/hour, no anneal

~ 3% reduction in gain after 5 Mrads (50 kGy, 2 x end-cap worst case)

no measurable effect on other performance parameters (noise, linearity, PSM ….)

low mid high

pre-rad5 Mrads


On-chip Test Pulse

ext.10pF

MGPA I/P

Vol

ts

nsec.

simple DAC allows programmable (I2C)amplitude charge injection -> range of signal sizes for each gain range

external trigger required

allows functional verificationduring chip screening and in-system

I2C

externaledgetrigger


Conclusion

MGPA development successful – architecture suits both barrel and end-cap detector regions

Analogue performance goodgainlinearitypulse shape matchingnoise

rad-hard as expectedpower consumption 600 mW

Current status

1st barrel supermodule contructed at CERN (barrel segment, 1700 channels) performance as expected (excellent noise uniformity) wafer mass production complete – large nos. packaged chips already available

within (or v. close to) spec.

5 channel VFE card


Transistor Level Schematic


2

4

68

0.1

2

4

68

1

2

4E

nerg

y re

solu

tion

[%]

102 3 4 5 6

1002 3 4 5 6

1000Energy [GeV]

constant 10,000 electrons (x 5) overall (0.5% + const.10,000 only) variable MGPA noise (x 5) overall (variable MGPA)

0.5% const. includescalibration & other errors

Barrel Energy Resolution

x 12 x 6 x1


Pulse Shape MeasurementsV

olts

time [nsec]

low gain range mid gain range high gain rangeO/P signals probedindividually

0 – 60 pC, 40 steps

saturation in mid and high gain ranges

no clamping outside linear range


I2C Pedestal AdjustV

olts

nsec.

I2C=0 I2C=50 I2C=100

VCM

ADCI/Prange

High gain range, ~ fullscale signal.I2C pedestal adjust sets offset current to diff O/P stage (one for each gain range)

I2C ~ 50 about right in this case


Linearity and Pulse Shape Matching

important for simple reconstruction of “true” pulse shape from samples coming from different gain ranges

target specifications

non-linearity < 0.1 % fullscale (each gain range)

pulse shape matching factor: Vpk-25/Vpk < 1 % within and across all 3 gain ranges

low gainrange

high gainrange

linearize

12-bitrange

25 ns samples

Vpk-25

Vpk

The MGPA ECAL readout chip for CMS

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