OCTOBER 2012 – LISBON – PORTUGAL 1

Abstract —The goal of this project is the design, construction,

and testing of a system that allows the measurement of viscosity of

liquids using a vibrating wire cell working in free decay mode.

The main contribution of this work is the original mode of

controlling the stimulus and the gathering of data in the context

of viscosity measurement using a graphical interface (GUI) where

the user can control the stimulus intensity and the acquisition

rate. A Field Programmable Gate Array (FPGA) is used to

control and synchronize the entire system connecting the GUI and

the hardware.

The maximum current used to stimulate the vibrating wire

(IRMS=0.825A) allow the use of larger diameter vibrating wires

leading to the possibility of measuring more viscous liquids.

Using the developed prototype to acquire the response of the

vibrating wire and fitting the experimental points to the equation

that describes the theoretical behaviour of vibrating wire

response, we obtain values of frequency and logarithmic

decrement with a standard deviation of 0.1Hz and 5x10-5

respectively, allowing compute the viscosity of the tested liquid.

Index Terms—FPGA, Free Decay Mode, Graphical Interface,

Signal Conditioning, Vibrating Wire, Viscosity.

I. INTRODUCTION

HE knowledge of viscosity of liquids is necessary for

quality control in various industries like pharmaceuticals,

cosmetics, food, chemical, clinical analysis, construction, oil,

etc. To define standard liquids such as water, toluene or

diisodecyl phthalate (DIDP) to calibrate other viscometers is

other scope of knowing the viscosity of liquids [1] [2] [3].

There are different types of viscometers based on different

methods to measure the viscosity of liquids. The viscometers

can be divided into two categories: primary (rotational

viscometers and vibrating viscometers) and secondary

(capillary viscometers and falling body viscometers) [4] [5]

[6]. This work is about the vibrating wire method.

The vibrating wire cell was developed and validated in [7].

The vibrating wire sensor is a metallic wire made of tungsten,

subject to an axial tension, placed within a magnetic field and

immersed in the liquid whose viscosity is to be measured as

shown in Fig. 1. It can be operated in either free decay or

forced oscillation modes. This work is about the free decay

mode.

Fig. 1. Vibrating wire cell [4].

Permanent magnets mounted externally create a magnetic

field perpendicular to the wire. The flow of an AC current

through the wire creates a force which sets it into a transverse

oscillation motion. The movement of the wire inside the

magnetic field induces a potential difference at the wire’s

terminals. The movement of the wire depends on its radius,

density and internal damping, as well as on the liquid density,

temperature and viscosity [4] [7].

For any type or method of measurement used it is

indispensable to have a theoretical model that relates the

characteristics of motion with the viscosity of liquid [4]. A

theoretical model that represents the time response of a

vibrating wire in free decay is represented by

1)cos()( VtAetV t (1)

where V(t) is the induced voltage at the wire terminals due to

its damped free decay oscillation; A is the initial amplitude of

induced voltage; ∆ is the logarithmic decrement; ω is the

frequency of the transverse oscillations; t is time; φ is the

signal phase offset and V1 is signal amplitude offset.

The induced voltage at the wire terminals V(t) and time

instant t are obtained by experimental method. The initial

amplitude A, the logarithmic decrement ∆, the oscillation

frequency ω, the signal phase offset φ and the signal amplitude

offset V1 are obtained by a nonlinear fitting of the experimental

data [1] [7].

Therefore, the main objective of this work is the design,

construction and testing of a portable system to stimulate and

acquire data from a vibrating wire sensor that allows us to

determine the parameters that define equation (1).

The Measure of Viscosity of Liquids with a

Vibrating Wire Cell

Luís Filipe Fonseca Regada

Instituto Superior Técnico, Lisboa

06426.regada@academiamilitar.pt

T

OCTOBER 2012 – LISBON – PORTUGAL 2

II. SPECIFICATIONS AND OVERVIEW

A. Specifications

System specifications are imposed by vibrating wire method

in free decay mode. The system must:

--Produce a symmetric current pulse that stimulates the

vibrating wire.

--Control the duration and amplitude of this pulse by the

user through a graphical interface (GUI).

--Acquire the vibrating wire response that is a damped

sinusoid signal with maximum amplitude in the microvolt

range.

--Amplify the vibrating wire response. The GUI must

allow the user to choose the amplification gain.

--To acquire 1000 samples with 100kHz of sampling

frequency (10µs of sampling period) that corresponds to 10ms

of signal response. The GUI must allow the user to change the

sampling frequency.

--After acquiring the vibrating wire response data it is

necessary to send it to a computer. This computer has a GUI

where the samples should be displayed in a graph illustrating

the vibrating wire response and save this information into a

file.

The expected result is a functional prototype of the system.

B. Overview

The work is divided into three blocks as shown in Fig. 2.

The first block is to produce a graphical interface (GUI) that

defines the characteristics (duration and amplitude) of the

symmetric current pulse to stimulate the vibrating wire. It also

allows the user to choose the length of the vibrating wire

response and the amplification gain. This GUI should also

receive the points, build a graph and save this graph and the

points of the graph.

The second block is an interface between the GUI, the

production of a symmetric current pulse and the acquisition of

the vibrating wire response. This interface is implemented in a

Field Program Gate Array (FPGA) and must control a Digital-

Analog Converter (DAC) to produce a pulse to stimulate the

vibrating wire according to the user options and control an

Analog-Digital Converter (ADC) to acquire the vibrating wire

response according to the user options. This interface must

also save all samples of vibrating wire response and only after

completing the acquiring of all samples the interface controls

the sending to the computer. To do this it is necessary to

define the communication between this interface and the

computer. Besides these features, this interface should allow

the control a set of relays to select the amplification gain,

depending on user options and another set of relays to

synchronize the vibrating wire stimulus and vibrating wire

response acquisition, ensuring that there is no path for any

currents which circulate through the vibrating wire before the

experiment starts.

The third block is to produce and condition the current pulse

to stimulate the vibrating wire. Besides that it is also necessary

amplify the vibrating wire response, ensuring the necessary

shield and acquire the vibrating wire response.

Fig. 2. Global system.

III. GRAPHICAL INTERFACE (GUI)

To develop the GUI was used the Microsoft Visual Studio

2010 program and the Windows Forms Application of Visual

C#. When GUI is started it has the aspect of the Fig. 3:

Fig. 3. GUI start.

The developed application starts by updating the USB ports

available and defining the default characteristics of USB

communication with FPGA as shown in Fig. 4:

Fig. 4. Default communication characteristics.

The user can change these communication characteristics.

To initiate the communication the user clicks on the button

Abrir Porta. Then the GUI changes its aspect to the aspect of

the Fig. 5:

OCTOBER 2012 – LISBON – PORTUGAL 3

Fig. 5. GUI after initiating the communication with FPGA.

Now the user may insert the following characteristics as

shown in Fig. 6:

--Duration of the symmetric current pulse between

0.01ms and 9.00ms.

--The pulse amplitude between 0.01V and 1.65V.

--The duration of vibrating wire response to be sampled.

--Choose between a resistance of 10Ω or 100Ω.

--Choose if he wants to use the 0.1Ω resistance (for future

use).

--Choose the amplification gain.

Fig. 6. GUI parameters to conditioning pulse to stimulate the vibrating wire

and amplification gain.

The resistance of 0.1Ω is for future use. The user can insert

different amplification gains to allow testing liquids with

different viscosities.

When the user clicks on the button Iniciar the GUI

computes the “frequency” of the pulse according to the

duration of the pulse introduced and compute the current of the

pulse according to the amplitude and the resistance chosen.

Then, the application makes the validation and sends the

parameters inserted.

After all parameters have been sent to the FPGA it makes its

processing (see in the next topic) and sends the samples back

to the GUI that builds a graph and allows to save the graph and

the samples.

IV. DESIGN, SIMULATION AND IMPLEMENTATION ON FPGA

It was used the development kit Spartan-3 Starter Kit Board

[8] with the FPGA XC3S1000 [9]. The hardware description

language (HDL) used was the VHDL. The tool used to

describe the desired circuit using VHDL, do the

implementation, simulation and configure the FPGA used was

Xilinx ISE Design Suite 12.4.

The FPGA receives parameters inserted by the user in Fig. 6

from a USB cable connected to a computer which runs the

GUI and store them in an implemented memory. Then the

FPGA controls a DAC to produce a pulse with the

characteristics referred by the user and corresponding to the

data stored in memory.

The FPGA must also control relays belonging to the signal

conditioning block and control is done according to the user

options, which are also stored in memory.

Next, the FPGA controls an ADC to acquire samples from

vibrating wire response and store these samples in another

memory.

Finally, the FPGA should send the samples stored in output

memory back to the GUI using the same USB cable. The

whole process must be synchronous and commanded by the

FPGA as shown in Fig. 7.

Fig. 7. FPGA in the system.

In FPGA the following circuits were implemented with the

following functions as shown in Fig. 8:

--Interface_serie: circuit responsible for communication

with the computer.

--UARTcomponent: circuit responsible for receiving

parameters from the serial port bitwise and group them into

bytes to send to Decode_hexa_chars. Circuit responsible for

receiving the samples from Encode_hexa_chars and send them

to the serial port bitwise.

--Decode_hexa_chars: circuit responsible for converting

ASCII characters from UART to the correspondent

OCTOBER 2012 – LISBON – PORTUGAL 4

hexadecimal representation. When this circuit gets the

character L generates a signal that indicates that has received

everything and FPGA can begin producing the pulse to

stimulate the vibrating wire.

--Memoria_entrada_na_FPGA: 18432bit (18kbit) dual

port RAM to store parameters from GUI.

--Circuito3: receive parameters from

Memoria_entrada_na_FPGA, processes them and sends them

to the DA2_controller and to the digital outputs of the FPGA.

Receives samples from AD1_controller, processes them and

sends them to Memoria_saida_da_FPGA.

--DA2_controller: controls PmodDA2 [10] (used DAC)

to produce the symmetric pulse.

--AD1_controller: controls PmodAD1 [11] (used ADC)

to sample the vibrating wire response.

--Memoria_saida_da_FPGA: 18432bit (18kbit) dual port

RAM to store samples.

--Encode_hexa_chars: circuit responsible for converting

samples from hexadecimal to ASCII representation.

--Interface_placa: circuit responsible for allowing

debugging.

Fig. 8. Global system implemented in the FPGA.

V. THE CONDITIONING OF THE ANALOG SIGNALS

After the user introduces in the GUI the duration and the

amplitude of the pulse and after these parameters are received

by the FPGA to control the PmodDA2 to produce the

symmetric pulse, it is necessary to condition this pulse to

excite the vibrating wire.

The current pulse to stimulate the vibrating wire must have a

square symmetric wave with the first half of the period positive

and the second half of the period negative [1]. The I/O pins of

the FPGA and the PmodDA2 only provide voltages between

0V and 3.3V, so it is only possible to produce a symmetrical

square impulse centered on 1.65V with the first half of the

period greater than 1.65V (but less than 3.3V) and the second

half of the period greater than 0V (but less than 1.65V). To

center the produced pulse on 0V (instead of 1.65V) was

necessary to make a block of hardware to shift the level of the

pulse down without introduce distortion. This block is shown

in Fig. 9 in A.

The vibrating wire is stimulated by current, so it is used a

power amplifier capable of producing a pulse with effective

amplitude with hundreds of milliamps. This power amplifier is

shown in Fig. 9 in B.

As in [1] [4] [10] it is necessary to use a resistor in series

placed between the produced pulse and the measuring cell to

limiting the current though the measuring cell. To study

different liquids with different viscosities it is necessary to use

different vibrating wires with different radius and different

resistors in series. It was decided to put resistor R9 and R10 in

parallel and two different relays S1 and S2 to select which

resistor limits the current of the pulse.

During the vibrating wire stimulation it is necessary to

synchronize two relays. The relay S3 must be conducting

during the pulse duration and the double relay S4 must be open

to avoid the influence of currents which leads to false readings

or errors measurements. After the end of the pulse duration

relay S3 must stop conducting and the double relay S4 must

lead the vibrating wire response to an amplification block C

with gain of one thousand.

When not making any experimental test, all relays are open

to protect vibrating wire of residual current.

Next, the amplified response of vibrating wire is amplified

again by an amplifier block D with the gain selected by the

user in the GUI, in order to have the amplified response of

vibrating wire with an amplitude between 0V and 3.3V to be

digitalized by PmodAD1, sent to FPGA and finally to the GUI

on the computer. To do this it is necessary to shift up the

output of D to center this signal on 1.65V (stage E).

The power amplifier B and the amplification block C are

connected to the outside of this module through optical

isolators IO, which prevent the flow noise currents and allow

the ground node to float and be connected to a Faraday shield

that encloses the part of circuit between power amplifier B and

the amplification block C and they are connected to the

external wall of the measuring cell, providing a screen against

noise.

Fig. 9. Global system.

OCTOBER 2012 – LISBON – PORTUGAL 5

The conditioning of the analog signals was implemented in

two separated boards. The “more sensitive” to noise board

with the power amplifier B, relays S1, S2, S3 and S4, the

resistors R9 and R10, the amplification block C and two

optical isolators IO. The “less sensitive” to noise board with

the DAC PmodDA2 and ADC PmodAD1, the amplification

block D and two level shifters A and E.

The ADC PmodAD1 gives 12bit per sample.

The schematic system is shown in appendix A and B.

The amplification block D controller by the user is

implemented with three amplification stages, where the first

stage could amplify 1 or 10, the second stage could amplify 1,

2, 5 or 10 and the third stage could amplify 1 or 10. With this

scheme it is possible to allow the following amplifications, as

shown in the Table I:

TABLE I

AMPLIFICATION SCHEME

1 x 1 x 1 = 1 1 x 10 x 5 = 50

1 x 1 x 2 = 2 10 x 10 x 1 = 100

1 x 1 x 5 = 5 10 x 10 x 2 = 200

1 x 10 x 1 = 10 10 x 10 x 5 = 500

1 x 10 x 10 = 20 10 x 10 x 10 = 1000

VI. RESULTS

To test and validate the acquisition and the production of

the pulse, the DAC is directly connected to the ADC. The user

inserts the parameters to produce the pulse in the GUI with the

aspect shown in Fig. 6. The output is, for example, shown in

the Fig. 10:

Fig. 10. Graph with the samples of the produced impulse.

Thus, it tests the GUI to control the production of the pulse

and the reception of data from the FPGA. It also tests the

correct functioning of the FPGA controlling the ADC and the

DAC, storing samples and communication with computer.

After producing the pulse it is necessary to synchronize the

relays S3 and S4 (of Fig. 9). To test and validate this, the

vibrating wire was replaced by a RLC circuit causing an

oscillation after the pulse was applied. At this stage

amplification has not yet been introduced, so the RLC circuit

is directly connected to the ADC. When both relays are always

conducting and there is no synchronism, the result is shown in

the Fig. 11:

Fig. 11. Both relays are always conducting. There is no synchronism.

When the relay S3 is conducting until the end of the pulse

duration and the relay S4 is always conducting, the result is

shown in the Fig. 12:

Fig. 12. Relay S3 is conducting until the end of the pulse duration and relay

S4 is always conducting.

When relay S3 is conducting until the end of pulse duration

and relay S4 is not, and after that relay S4 is conducting until

the end of pulse duration and relay S3 is not (the relays S3 and

S4 are synchronized) the result is shown in the Fig. 13:

OCTOBER 2012 – LISBON – PORTUGAL 6

Fig. 13. Relay S3 and S4 synchronized.

As we can see in Fig. 13 the relay S4 is not conducting until

the end of the pulse duration (4ms) because ADC saturates

when there is no signal connected to its input.

After the relays are synchronized, the ADC starts

conversion in the end of pulse duration when the relay S4

starts conducting.

To test the level shifter was performed a simulation using

PSpice. As we can see in the Fig. 14 the green line is centered

at 1.65V and represents the produced pulse. The red line is the

output of first level shifter that shifts the pulse down to center

the input pulse (green line) at 0V. The blue line is the output of

the second level shifter that shifts the pulse up to center the

vibrating wire response (in this example, the red line) at 1.65V

again.

Fig. 14. Simulation of the behaviour of the level shifter.

To test the entire system, the RLC circuit is replaced by the

vibrating wire and all amplification as shown in Fig. 9. After

making an acquisition, the experimental points (V(t) and t)

were fitted to the curve that defines the theoretical behaviour

of the vibrating wire response defined in (1) using the Table

Curve 2D.

Before introducing the electrostatic shield, the vibrating

wire response acquired was shown in the Fig. 15:

Fig. 15. Vibrating wire response with no electrostatic shield.

As we can see in Fig. 15, the noise distribution has

amplitude of 0.9Vpeak-to-peak. After introducing the “more

sensitive” board to noise in an electrostatic shield, the noise

has amplitude of 0.1V peak-to-peak which is approximately 8 times

less noise, as shown in Fig. 16:

Fig. 16. Vibrating wire response with electrostatic shield.

The parameters to compute the liquid viscosity are the

frequency and the logarithmic decay of vibrating wire

response. The average of measured frequency and logarithmic

decay are faverage=877.0985Hz and ∆average=0.06075 with

standard deviation of σf=0.118Hz and σ∆=5 10-5

.

The vibrating wire response has an RMS amplitude of

SRMS=0.319V and the noise RMS amplitude is RRMS=0.023V.

The signal-to-noise ratio is SNR=22.9dB. Once a sample is

encoded into 12bits and noise has about 0.13Vpeak-to-peak, which

correspond to 8 “noisy” bits and 4bits of “pure” vibrating wire

response.

Some tests and experimental results are presented in table II.

TABLE II

SOME RESULTS

Experiment f (Hz) ∆ V1 (V) A (V) R2

No shield 879.410 0.0499 -0.05 1.71 -0.44 0.910

1.º with shield 876.972 0.0608 -0.02 1.38 -2.97 0.996

2.º with shield 876.989 0.0607 -0.02 1.39 -3.05 0.994

3.º with shield 877.210 0.0607 -0.02 -1.49 -1.40 0.995

4.º with shield 877.223 0.0608 -0.22 -1.48 -0.80 0.994

OCTOBER 2012 – LISBON – PORTUGAL 7

VII. CONCLUSION

The scope of this project is a multidisciplinary work that

integrates software and hardware together in the context of

viscosity measurement. The hardware was designed,

implemented, tested and controlled by the designed,

implemented and tested software (GUI). It was necessary to

have concepts of noise and signal conditioning, too.

The maximum current to stimulate the vibrating wire

(IRMS=0.825A) is also an original contribution, allowing to use

more viscous liquids and wires with a larger diameter.

It was implemented a solution that allows to fulfill the

specifications, obtaining a vibrating wire response with

SNR=22.9dB. To compute the viscosity of liquids it is

necessary to know the frequency and logarithmic decay of

vibrating wire response. The frequency obtained was

f=877.0985Hz and ∆=0.06075. The standard deviation of this

experimental results was σf=0.118Hz and σ∆=5 10-5

. It can

be concluded that the obtained results are acceptable to

compute the liquid’s viscosity.

It can be seen that when we inserted the “more sensitive”

board inside the electrostatic shield, noise is reduced about 8

times. One way to try to decrease the noise level would be to

place the entire system into an electrostatic shield and improve

the implemented shield.

It would be interesting evaluate the possibility of introduce

new features in GUI like the possibility of performing

scheduled measurements and scheduled automatic successive

measurements.

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OCTOBER 2012 – LISBON – PORTUGAL 8

APPENDIX A

Fig. 17. Schematic (part I).

OCTOBER 2012 – LISBON – PORTUGAL 9

APPENDIX B

Fig. 18. Schematic (part II).