The MAPS -based ITS Upgrade for ALICE...Stave Readout Unit Inner-Barrel Assembly Outer-Barrel...

The MAPS-based ITS Upgrade for ALICE

G. Contin (Università di Trieste – INFN Trieste)on behalf of the ALICE Collaboration

VERTEX 2019 – The 28th International Workshop on Vertex Detectors13-18 October 2019 - Lafodia Sea Resort, Lopud Island, Croatia

The ALICE Upgrade for Run3

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“Old” ITS-1 … decommissioned and displayed in the ALICE exhibition at P2

Tracking detectors upgraded: Inner Tracking System (ITS-2)Time Projection ChamberMuon Forward Tracker

Other upgrades: Fast Interaction TriggerIntegrated Online-Offline system (O2)

record minimum bias Pb-Pb data at > 50kHzDetector readout electronics

See E. Botta’s talk: “ALICE ITS: Operational Experience, Performance and Lessons Learned”

The Inner Tracking System ITS-2

• Monolithic Active Pixel Sensor (MAPS)

• Pixel pitch: ~30 µm• 7 cylinders covering ~10 m2 area• Innermost radius: 23 mm • Inner Barrel (IB)

• 3 Inner Layers (48x 9-chip Staves)• ~0.35% X0 material budget

• Outer Barrel (OB)• 2 Middle Layers (54x 8-module Staves)• 2 Outer Layers (90x 14-module Staves)

• ~24k chips = 12.5G pixels

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147 cm

40 cm

ALICE ITS Upgrade - [email protected]

“Technical Design Report for the Upgrade of the ALICE Inner Tracking System” ALICE Collaboration, J.Phys. G41 (2014) 087002, CERN-LHCC-2013-024

Simulated detector performance

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• Pointing resolution• x3 and x6 improvement in rϕ and z for 0.5 GeV/c π• 40 µm for 0.5 GeV/c π

• Standalone tracking efficiency• > 60% for 0.1 GeV/c π• > 95% for π with pT > 0.3 GeV/c


• Reduction in material budget, pixel pitch and radius of the first layer will lead to a dramatic improvement in the detector performance, especially at low pT

1018 cm-3

NA ~1013 cm-3

NA ~1018 cm-3

Diffusion

DriftDrift

The ALPIDE sensor

14/10/2019

• 27x29x25 µm3

• 1024 x 512 pixels• Spatial resolution: ~5 µm• Priority Encoder Readout

See V. Raskina’s poster: “Radiation Hardness Studies of ALPIDE, the CMOS sensor for the ALICE ITS Upgrade”

MAPS produced using TowerJazz 0.18µm CMOS Imaging Process

Monolithic Active Pixel Sensor• Deep P-well allows in-pixel full CMOS • Low-power (40mW/cm2)• ~30 μm pitch high granularity• 50 μm thickness low material budget• >1 kΩ·cm resistivity p-type epitaxial

layer (25 μm) • Possibility of reverse biasing

• Integration time: < 20 µs• Read out up to 1.2 Gbit/s• Continuous or triggered read-out• Final testing yield: 64%

The Inner Barrel

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• 9x 50µm-thick ALPIDE chips • Aluminum Flexible Printed Circuit (FPC)• Each chip read out separately• 27 cm length• Hit density > 9.1 cm-2

• Global IB HIC yield: 75%

IB Hybrid Integrated Circuit (HIC)

Sensor-sideview

FPC-side view

• Clock, control, data, power pads wire-bonded to FPC

The Inner Barrel

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IB Hybrid Integrated Circuit (HIC)

Sensor-sideview

FPC-side view

Material thickness: ~ 0.35% X0

Readout speed: 1200 Mbps<radius> (mm): 23, 31, 39 Nr. staves: 12, 16, 20Nr. chips: 432Chips tested at CERNHICs and Staves assembled at CERNGlobal IB Stave yield: 97%

FPC-side viewIB Stave

• 9x 50µm-thick ALPIDE chips • Aluminum Flexible Printed Circuit (FPC)• Each chip read out separately• 27 cm length• Hit density > 9.1 cm-2

• Global IB HIC yield: 75%

• Clock, control, data, power pads wire-bonded to FPC

The Outer Barrel HIC production

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• 14x 100µm-thick ALPIDE chips (2 rows) • Data and control transferred through 1 master chip per row• Chip pads wire-bonded to copper-based FPC• Power delivered via 6 cross-cables soldered to FPC• Hit density < 2.8 cm-2

See M. Buckland’s poster: “Series production and test of hybrid modules for the ALICE ITS Upgrade”

1 2 3 4 5 6 714 13 12 11 10 9 8TAB

Sensor-sideview

FPC-sideview

Custom made Module Assembly Machine (MAM)

Production (cumulative) evolution

2017

2018 2019

Construction sites• CHIP test

• Yonsei, Pusan• FPC preparation/test

• Catania, Trieste• HIC production

• Bari, Liverpool, Pusan/Inha, Strasbourg, Wuhan

Production completed

OB HIC productionAssembled: 2592Detector-grade: 2180Global yield: 84%Installed on OB: 1698

See N. Valle’s poster: “Ageing tests of the Hybrid Modules for the ALICE ITS Upgrade”

Nr. modules/stave: 4 (ML), 7 (OL) <radius> (mm): 194, 247, 353, 405

Material thickness: ~ 1% X0 Readout speed: 400 Mbps

Power density ~ 40mW/cm2 Length (mm): 844 (ML), 1478 (OL)

Nr. staves: 24, 30, 42, 48 Nr. Chips: 6048 (ML), 17740(OL)

The Outer Barrel: Middle (ML) and Outer Layers (OL)

14/10/2019 9ALICE ITS Upgrade - [email protected]

End of production: November 2019

OL staves rework almost done with ~50% yield

Detector-grade staves ML Staves produced: 56OL Staves produced: 92Global OB Stave yield > 90%Spare production ongoing

Production target: 90 + 10 (OL), 54 + 6 (ML) (# spares)

2018 2019

Production (cumulative) evolution

The Outer Barrel Stave production

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Half-Stave assembly

HIC-to-HIC interconnection

soldering

HIC alignment on Cold Plate

HIC gluing onto Cold Plate


The Outer Barrel Stave production

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Half-Stave assembly Stave assemblyTwo half-staves on Space Frame

Power Bus installation

Boxed for shipping

HIC-to-HIC interconnection

soldering

HIC alignment on Cold Plate

HIC gluing onto Cold Plate


At CERN: Layer and Barrel assembly

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The staves are tested at receptionvalidated after installationor sent to rework in case of problems

• Inner barrel assembly completed: fully functional

• Top Outer half-barrel assembly completed• Bottom Outer half-barrel awaiting a few more units

• Maximum accepted dead area per OB Stave: 2%• Outer Barrel being assembled avoiding overlaps of dead chips

Inner half-layers Middle half-layer Outer half-layer


Support structures

➢➢

➢ Institutes:LBNL (US), CERN, Padova (IT), St. Petersburg (RU)

Component production completedInsertion dry test performed

Services IB

Services OB

Detector IB

Detector OB

ITS upgrade - Component production status


➢➢ CAEN powering modules available and in use in commissioning setup➢ Power board production completed

Readout electronics:➢ Institutes:

Austin (US), Bergen (NO), CERN, Nikhef (NL), Padova (IT)➢ 192 FPGA based RUs, operating in a mild radiation

environment (<10 krad, 1011 1 MeV/neq)➢ Board production completed

Power SystemInstitute: LBNL (US), Bari (IT)

Support structures

➢➢

➢ Institutes:LBNL (US), CERN, Padova (IT), St. Petersburg (RU)

Component production completedInsertion dry test performed

Services IB

Services OB

Detector IB

Detector OB

CRU O2 FLP

ALPIDE

Up to 28 Sensors per RU (either

standalone orin master mode

GBT 3.2 Gb/s

GBT3.2 Gb/s

GBT3.2 Gb/s

GBT3.2 Gb/s

GBT3.2 Gb/s

Control

Trigger

Stave

SCA CAN

ReadoutUnit (RU) Data

Power

PowerUnit (PU)

DCSbackupRU interface

DCSITS specific operations

LTU

Power



ITS upgrade - Component production statusSee P. Giubilato’s talk: “The ALICE ITS Upgrade Readout and Power System”


Detector Construction and Assembly• HIC production: completed• Stave production: 90% done

Continues until November 2019 for spare staves• Electronics production and testing: done

Commissioning at the surface with final services ongoing (operation 24/7)

Installation

6-month Global Commissioning

May ‘19

Aug ‘19

June ‘20

Feb ‘21

Construction, Installation and Commissioning Timeline

15

Jun ‘19 StaveReadout Unit

Inner-Barrel Assembly Outer-Barrel Assembly

Installation Global commissioning

Oct ‘19 Outer-Barrel Layer Assembly: >75% done

Sep ‘19

14/10/2019

Dec ‘17


Commissioning at the surface

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See T. Lazareva’s poster: “Assembly and commissioning of the ALICE ITS Upgrade”


Half-Layers 5-6 TOP

Half-Layers 3-4 TOP

TOP Inner Half-Barrel

OB TOP IB TOP IB BOTTOM OB BOTTOMCrates

Commissioning at the surface

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See T. Lazareva’s poster: “Assembly and commissioning of the ALICE ITS Upgrade”


Half-Layers 5-6 TOP

Half-Layers 3-4 TOP

TOP Inner Half-Barrel

OB TOP IB TOP IB BOTTOM OB BOTTOMCratesTOP Outer Half-Barrel

Noise and threshold performance

18

Threshold is a trade-off between: - Detection efficiency

Threshold < Charge QMIP (~225e-)- Fake-hit rate:

Threshold >> Noise

Threshold Noise

µ = 99.4 e-

RMS(µ) = 20.6 e-𝜎𝜎 = 5.53 e-

RMS(𝜎𝜎) = 0.96 e-

Threshold and noise after tuning for an OL Stave (~100M pixels) compared with a single chip test data

Extremely quiet detectorFrom tests performed on a spare IB layer, running the IB at fake-hit rates below 10-10/pixel/event seems feasible

14/10/2019 ALICE ITS Upgrade - [email protected]

Threshold Tuning

19

Before Tuning

After Tuning

untuned

tuned

After Tuning, zoomed

14/10/2019

• Adjustment of front-end parameters to equilibrate the charge thresholds• Achieving uniform response across the detector, verified on a spare IB half-layer• Very satisfying threshold stability over time


Spare Inner-Barrel half-layer test data

Evolution of the ALICE ITS

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2009-2019 2021+ALICE ITS-1 ALICE ITS-2

Readout rate: 1 kHzThickness of first layer: 1.14%X0

Integration time: <20 µsThickness IB layer: 0.35%X0


Evolution of the ALICE ITS

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2009-2019 2021+ALICE ITS-1 ALICE ITS-2

Readout rate: 1 kHzThickness of first layer: 1.14%X0

Integration time: <20 µsThickness IB layer: 0.35%X0

2025+

ALICE ITS-3

Innermost layer: at R = 18 mmThickness of each layer: 0.05%X0

Replace theITS-2 Inner Barrel

See M. Mager’s talk: “Upgrade of the ALICE ITS in LS3”


Conclusions

• The ALICE ITS Upgrade (ITS-2) is based on MAPS technology• It will dramatically improve the ALICE tracking capabilities at low momenta• Detector component production is completed, spare part production is ongoing• Commissioning progressing well, performance exceeding the expectations• The ITS will be installed in ALICE in June 2020 • 6 months of global commissioning with central systems before Run3 data taking• A further upgrade of the ITS Inner Barrel (ITS-3) for LHC Long Shutdown 3 has

been proposed and the R&D activities have already started

14/10/2019 22ALICE ITS Upgrade - [email protected]

Thank you for your attention!

Backup slides

14/10/2019 ALICE ITS Upgrade - [email protected] 24

* revised numbers w.r.t. TDR** including a safety factor of 10, revised numbers w.r.t. TDR

THR

COMPAMP

Bias, Readout, Control

Read

out (

zero

sup

pres

sion)

Read

out (

zero

sup

pres

sion)

Read

out (

zero

sup

pres

sion)

Read

out (

zero

sup

pres

sion)

1024 columns

512

row

s

25

ALPIDE and Detector Parameters (Vs. ITS1)

Chip size:30 mm x 15 mm

Pixel size:27 µm x 29 µm

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ITS Run1/Run2 ITS upgradeNumber of layers 6 (pixel, drift, μstrip) 7 (MAPS)Rapidity range |η| < 0.9 |η| < 1.3Material budget per layer 1.14% (SPD) 0.35% (IL)Distance to interaction point 39 mm 22 mmPixel size 50 x 425 μm2 29 x 27 μm2Spatial resolution (rφ x z) 12 μm x 100 μm (SPD) 5 μm x 5 μmMax. readout speed Pb-Pb 1 kHz 100 kHz

Material budget ITS-2 innermost layer

6

Assembly and Quality Assurance workflow

27

Assembly: HICs Half-staves StavesQA: Functional test at each step + HIC EnduranceMetrology: Align components and map the sensitive volume positions

Probe testedChips

Tested and sizedFlexible Printed Circuits

Chip alignment

FPC gluing

Functional test

Concurring processes

HIC wire bonding

Endurance test HIC rework

HIC: repeat wire bonding

~4 days

Rework procedures


Assembly: HICs Half-staves StavesQA: Functional test at each step + HIC EnduranceMetrology: Align components and map the sensitive volume positions 28

Probe testedChips


Tested and sizedCold Plate

Chip alignment

FPC gluing

Interconnection soldering

Half-Stave metrologyFunctional test


HIC wire bonding

Half-Stave assembly

Endurance testFunctional test Half-Stave

rework

HIC rework

HIC: repeat wire bondingHalf-Stave: replace HIC

Rework procedures

~4 days

Reception test


29

Assembly: HICs Half-staves StavesQA: Functional test at each step + HIC EnduranceMetrology: Align components and map the sensitive volume positions

Probe testedChips


Tested and sizedCold Plate

Chip alignment

Sized Carbon Fiber Space Frame

FPC gluing

Interconnection soldering

Half-Stave metrology

Tested Power Bus and Filter Board

Functional test

Final validation test

Stave assembly

Stave delivered to CERN


HIC wire bonding

Half-Stave assembly

Power Bus soldering

Stave metrology

Endurance testFunctional test Half-Stave

rework

HIC rework

HIC: repeat wire bondingHalf-Stave: replace HIC Stave: Disconnect and rework Half-Stave

Rework procedures

~4 days ~2 weeks

Reception test

The MAPS -based ITS Upgrade for ALICE...Stave Readout Unit Inner-Barrel Assembly Outer-Barrel...

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