The LAV primitive generator
description
Transcript of The LAV primitive generator
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 1
The LAV primitive generatorFrancesco Gonnella18th December 2013
TDAQ Working Group Meeting
18 December 2013
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 218 December 2013
OBTRIG
TRIGGEN TRIG
LAV trigger generator inside PP
Input data is read from the OBTRIG fifo; Data is elaborated from TRIGGEN module Output data is written to TRIG fifo
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 3
LAV front-end electronicsLAV electronics channel working principle
18 December 2013
Split the input signal into two copies: 1 copy to comparator + 1 copy to analog sums
Clamp the signal preserving its width, wide dynamical range is expected (MIP 70 MeV ~ 10 mV, high energy γ ~ 1V)
Amplify the signal and compare with 2 thresholds Each threshold is independently adjustable up to 250 mV Produce an LVDS signal and send the signal to the digital read out
board
High
thre
shol
dClamp
Amp 6x
CompareLow
thre
shol
d
LVDS
LVDSSplit
to analog sum
To TDC
To TDC
4
LAV PP firmware Physical event reconstruction and and slewing correction
Constant time offset for each channel (cable and time of flight) Event reconstruction (High and Low High Threshold matching) Slewing correction Recognize the end of the 6.4 μs frame (EoF) Deliver data (primitives and EoF) to SL on a 32-bit bus Error on FIFO L/H full
18 December 2013Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy
Offsetand
map Ch.
Selector
FIFO L
FIFO H
FIFO L
FIFO H
FIFO L
FIFO H
Event Finder
offset
RAM(ECS
)
Data formatte
r & threshold retriever
thresholdRAM(ECS)
Slewing calculator
Output stage
to TRIG fifo
OB FIFO
64 blocks(128 FIFOs)
InputStage
End-of-Frame signal
mapRAM(ECS
)
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 5
Time-offset corrector module Receives input stream Checks if data is a time
Retrieves the proper offset value from offset RAM
Adds the offset to the time
If data is a timestamp (0xA) or a counter (0xB) Transmits data
untouched
Input-output delay:4 clock cycles.
18 December 2013
Data in Time-offsetadder
Data out
address offse
t
clock
Data Ready in
Read enable
OffsetRAM
13-bit words
LSB=100ps
address
offset
Write enable
ECS
Data Ready Out
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 6
Channel mapping module Receives input stream If data is a time
Reads original channel number
Replaces it with new ch number read from RAM
One bit is used to enable and disable the channel
If data is a timestamp (0xA) or a counter (0xB) Transmits data
untouched
Input-output delay:4 clock cycles.
18 December 2013
Data in Channel mapper
Data out
Address (old ch)
Ch. n
umbe
r
clock
Read enable
MappingRAM
8-bit words(7 = disabled, 6-0 channel number)
address
Channel
Write enable
ECS
Data Ready in Data Ready Out
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 7
Channel-selecting module
Redirect fine time to the proper channel fifo time stamps are sent to all channels at once
Reduce data size form 32 bits to 22 bits
18 December 2013
FIFO High
FIFO Low
FIFO High
FIFO Low
FIFO High
FIFO Low
data bus
Channel selectorData in
clock
Data Ready in
Write enable
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 8
Channel time fifo module
Properly merge time stamp and fine time
Different High and Low FIFO depth: 8 and 16 words
Different High and Low FIFO FSM logic
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Fine
Tim
eTi
me
Stam
p
…Da
ta: 0
0112
345
TS: 0
0112
344
Data
: 001
1234
6Da
ta: 0
0112
347
Data
: 001
1234
8TS
: 001
1234
5
MegaWizard Fifo (8H/16L words)
Push Fifo
OutputFSM
Ready
40-b
it da
ta
22-b
itda
ta
Empt
y
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 9
Event-finder module architecture
18 December 2013
Block number encoderFIFO High
FIFO Low
FIFO High
FIFO Low
FIFO High
FIFO LowEvent Finder FSM
• Wait for High• Look for Low in time
• if L is preceding discard it;
• If L is successive discard L and H
• If L matches H produce output data:block number (6 bit)absolute time (40 bit)rise time (8 bit)
2x
32-b
itda
ta
data bus
This module works under the assumption that data, for a given channel, are time ordered.
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 10
Threshold retriever module Parse 2x 32-bit input words:
Retrieve proper threshold values from RAM
Produce a formatted 72-bit word:
Need to know thresholds form DCS. Not yet done
18 December 2013
32-bit Data in
Data formatter
&Thresholdretriever
72-bit Data out
address offse
t
clock
Strobe in
Read enable
ThresholdRAM
address
Thr
WE
ECS
Strobe out
31 – 30
29 Block 24
23 – 20
19 Risetime 12
11 – 8
7 Time(39:32) 0
31 Time(31:0) 0
71 Low Threshold 60
59 High Threshold 48
47 Risetime 40 39 Time 0
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 11
High Level Synthesis Calculator
18 December 2013
Module realised using High Level Synthesis (A. Bellotta)
HLS calculator performing slewing calculation:
Working frequency: 160 MHz Input-output latency: 9 clk Throughput: 1 clk Reasonable resources
utilization
72-bit Data in
HLSSlewing
correction calculator
40-bit data out
Strobe in Strobe out
clock
Megawizard divider:
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 12
LAV-PP output data format Data sent from each PP to SL is formatted as following:
Data is composed of 2 32-bit words, the first starting with “10”
The End of Frame is 1 word starting with “11”
For example:
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31 ”10” 30 29 Block 24 23 Error 22 block error 20 19 Risetime 12 11 – 8 7 Time(39:32) 0
31 Time(31:0) 0
31 ”11” 30 29 Primitive counter 0
0X81000A000X0008FFB70X800005000X0008FFFA0XC00000010X81000A000X0009FFB80X800005000X0009FFFB0X81000A000X000AFFBA0X800005000X000AFFFD0XC00000020X81000A000X000BFFBB0XC0000003
Reminder: 0xC = ‘1100’
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 13
+---------------------------------------------------------------------------+; Fitter Summary ;+-------------------------------+-------------------------------------------+; Fitter Status ; Successful - Tue Nov 19 11:56:52 2013 ;; Quartus II 64-Bit Version ; 12.0 Build 178 05/31/2012 SJ Full Version ;; Revision Name ; pp_fpga ;; Top-level Entity Name ; pp_fpga ;; Family ; Stratix III ;; Device ; EP3SL110F1152C4 ;; Timing Models ; Final ;; Logic utilization ; 74 % ;; Combinational ALUTs ; 39,996 / 86,000 ( 47 % ) ;; Memory ALUTs ; 3,268 / 43,000 ( 8 % ) ;; Dedicated logic registers ; 43,150 / 86,000 ( 50 % ) ;; Total registers ; 43806 ;; Total pins ; 581 / 744 ( 78 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 3,276,930 / 4,303,872 ( 76 % ) ;; DSP block 18-bit elements ; 4 / 288 ( 1 % ) ;; Total PLLs ; 3 / 8 ( 38 % ) ;; Total DLLs ; 1 / 4 ( 25 % ) ;+-------------------------------+-------------------------------------------+
PP FPGA: resources utilization
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14
LAV SL firmware Primitive merging and Multiple Trigger Packet (MTP) generation
Merge physical hit times from the 4 PPs Group together hits within a given cluster (5 ns window) Evaluate the average of the clusters, obtaining primitive times Sort primitive times Produce an MTP Error on primitive lost
18 December 2013Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy
Data merger
PP0 FIFO
PP1 FIFO
PP2 FIFO
PP3 FIFO
FIFO Clustering module
Sorting module
sortingRAM
Average calculator
Output stage
Data counter
Cluster hit number
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 15
Data Merger FSM handling the 4 FIFOs
Priority switches cyclically among the 4 FIFOs
FSM waits for EoF words from all the enabled PPs before producing a global EoF word
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2356
2345
2300
EoF
32
bit
2322
EoF
32
bit
2358
2331
EoF
32
bit
EoF
32
bit
Data merge
r 2356
2322
2358
2345
2331
2300
EoF
32 b
it
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 16
Clustering module Composed of 32 (can be increased) basic cells
Each cell stores the first Time received
If successive times match Time it adds them to Sum and increases Number.If not, it sends the time to the next cell
The matching window is asymmetrically programmable (up to ±12.5 ns) through 2 independent registers
At the EoF it acts as a shift register, giving as output all the cluster times and number of events per cluster
The Average Calculator performs the division between Sum and Number
Number is also fed to the sorting module to be written into the final primitive data
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Clustering cell
• Time• Number• Sum
Clustering cell
Clustering cell
Clustering cell
Clustering cell
Time out
Number out
Time in
Number in
Sum outSum in
HLS Average calculator
(A. Bellotta)Number outSum out Average out
160 MHz Latency : 3 clk Throughput: 1 clk
This is a simplified scheme: actually time values are split into Coarse and Fine so that divisions are performed on 8-bit values rather than 40-bit.
Low limit
register
High limit
register
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 17
Sorting module and RAM Composed of 32 (can be increased)
basic cells Each cell receives a time. The first time
is stored. Successive times:
If greater than the stored time simply pass through the cell
If smaller pass through the cell increasing the position of the cell
At the EoF, it acts as a shift register giving as output all the times and their respective positions
Data is fed into a RAM and addressed with their position
In the meantime the number of primitives is counted out
At the and the sorting RAM is read out starting from address 0 up to the last counted datum
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Sorting cell
• Time• Position
Sortingcel
l
Sorting cell
Sorting cell
Time out
Position out
Time in
Position in
RAMData
Address
Num
ber of hits
From clustering module
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 18
LAV-SL output data format Data sent from SL is formatted as following:
Data is composed of 3 32-bit words, to fit global firmware specs
For example:
18 December 2013
31 reserved 24 23 primitive counter 031 hit number 28 27 reserved 8 7 fine time 0
31 coarse time (timestamp) 0
0x000000530x3000003d0x00004a850x000000540x900000400x00004abd0x000000550x1000003e0x00004ac50x000000560xa00000400x00004afd
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 19
+---------------------------------------------------------------------------+; Fitter Summary ;+-------------------------------+-------------------------------------------+; Fitter Status ; Successful - Thu Nov 28 12:59:38 2013 ;; Quartus II 64-Bit Version ; 12.0 Build 178 05/31/2012 SJ Full Version ;; Revision Name ; sl_fpga ;; Top-level Entity Name ; sl_fpga ;; Family ; Stratix III ;; Device ; EP3SL110F1152C4 ;; Timing Models ; Final ;; Logic utilization ; 39 % ;; Combinational ALUTs ; 22,484 / 86,000 ( 26 % ) ;; Memory ALUTs ; 257 / 43,000 ( < 1 % ) ;; Dedicated logic registers ; 18,758 / 86,000 ( 22 % ) ;; Total registers ; 18898 ;; Total pins ; 728 / 744 ( 98 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 1,450,850 / 4,303,872 ( 34 % ) ;; DSP block 18-bit elements ; 0 / 288 ( 0 % ) ;; Total PLLs ; 2 / 8 ( 25 % ) ;; Total DLLs ; 0 / 4 ( 0 % ) ;+-------------------------------+-------------------------------------------+
SL FPGA: resources utilization
18 December 2013
Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy 20
Conclusions LAV primitive generator has been successfully integrated with the new
version 2 TEL62 firmware LAV primitive generator has been tested successfully during last dry
run, results will be/have been presented by R. Piandani Resources are reasonable for SL (~40%), at the limit for PP (74%) Possible improvements
Some internal FIFO (especially in the PP) could be made available from ECS for debug proposes
Introduce the possibility or sending/not sending the primitive on the basis of the number of hits of the cluster
The “rise time” information is available at SL level so a preliminary charge reconstruction procedure is under study
Requests: We are performing very interesting tests with cosmic rays using periodic
triggers. Could it be possible to use LAV fw to generate triggers? This would tremendously improve our efficiency.
18 December 2013