The Journey to FinFETss3.amazonaws.com/sdieee/1847-2015_04_Loke.pdfPhil Fisher Greg Kovacs Steve...

The Journey to FinFETs

Alvin [email protected]

30-Apr-2015 & 21-May-2015

IEEE San Diego – CPMT Chapter & AP/MTT/ED/SSC/CAS Joint Chapter

© Loke, The Journey to FinFETs

Something to Ponder…People get lostbecause they cannot be found.

Theodorus Loke

Slide 1


Dave Pulfrey

Bruce Wooley

Krishna Saraswat

Simon Wong

Tom Lee

Jim Plummer

Ying-Keung Leung

Tom Cynkar

Gary Ray

Jeff Wetzel

Chintamani Palsule

Martin Wedepohl

Bob Barnes Dick Dowell

Bich-Yen Nguyen

Wei-Yung Hsu

Qi-Zhong Hong

Tom Lii

Ron KennedyMark Horowitz

John Bravman

Paul Townsend

Joe McPherson

Rick Hernandez

Phil Fisher

Greg Kovacs Steve Kuehne

Charles Moore Michael Oshima Jim Pfiester

Mike Gilsdorf

Tin Tin Wee

Matt Angyal

Bruce Doyle Emerson Fang

Andy Wei

Jung-Suk Goo

Ray Stephany

My Teachers

Shawn Searles

John Faricelli Dennis Fischette

Tom TiedjeGerry TalbotChangsup Ryu

Justin Leung

Takamaro Kikkawa

Larry Bair

Ram Venkatraman Carl-Mikael ZetterlingPatrick Yue

Bob Havemann

Slide 2

Shawming Ma Michael Nix

Joanne Wu

Don Morris

Tom Bryan

Tim Hollis Reza Jalilizeinali

Behzad Razavi Jeff Rearick

Luigi Colombo

Guoqiang Xing


The 10000-Foot View… A Switch

Slide 3

small, fast, thrifty

Scaling Performance Energy-Efficient


CMOS Scaling Still Alive

Slide 4

Keating, Synopsys [1]

Intel 22nm & 14nmtri-gate finFET

• Leading foundries scrambled, now in 16nm tri-gate early production• Intel started 14nm production


Our Objective• Understand how MOSFET structure has evolved• Understand why it has evolved this way• Fundamentals, fundamentals, fundamentals

Slide 5

L=35nm

SiGe

L=35nmL=35nm

SiGe

L=35nm

SiGe

L=35nmL=35nm

SiGe


OutlinePart 1

• Motivation• MOSFET & Short-Channel Fundamentals• 130nm Fabrication• Lithography

Part 2• Strain Engineering (90nm & Beyond)• High-K / Metal-Gate (45nm & Beyond)• Fully-Depleted (22nm & Beyond)• Tri-Gate FinFETs• Conclusions

Slide 6


The Basis of All CMOS Digital ICs

Slide 7

• Voltage represents logic level• Charging and discharging a capacitor… very quickly!• Shorter delay and lower power

pull-down logic

pull-up logic

inputseff

DDload

eff

loaddelay I

VCI

Qt

fVCP DDloaddynamic2


Effective Inverter Drive Current

Slide 8

0.0

0.5

1.0

1.5

0.0 0.2 0.4 0.6 0.8 1.0

I D (m

A)

VDS

(V)

VGS

0.5V

0.7V

1.0V

0.2V

IDsat

IDoff

IDlow

IDhigh

IDeff

• IDeff estimates effective inverter current drawn during switching

• More realistic and way less optimistic than IDsat

Na et al., IBM [2]

IDlin

2,

,2

2

DDDSDDGS

DDDSDD

GS

VVVVIDIDhigh

VVVVIDIDlow

IDhighIDlowIDeff

28nm, VDD=1.0V


Flatband Condition (VGS=VFB)

Slide 9

p-typebody

poly gate

n+

sourcen+

drain

siliconsurface

source-to-bodydepletion

drain-to-bodydepletion

p+ bodycontact

VDS

VGS

VBS

EC

EV

Ei

qbqs

EF

EF

siliconsurface

M O S

qs = qb

Energy Band

Diagram


Onset of Surface Inversion (s=0)

Slide 10

p-typebody

poly gate

n+

sourcen+

drainp+ bodycontact

VDS

VGS

VBS

surfaceundoped

M O S

Energy Band

Diagram

qs

qs = 0

qb

– – –

+ ++

–

+

+ charge terminating on – charge

depletionregion


Onset of Strong Surface Inversion (VGS=VT)

Slide 11

p-typebody

poly gate

n+

sourcen+

drainp+ bodycontact

VDS

VGS

VBS M O S

Energy Band

Diagram

– – –

+

– – –

– – – – – – – – – – – –

+ + ++ + + ++ + + ++ + + ++ + + ++ + +

–

–– – –

ox

depbFBT C

QVV 2

ss

qb

qsqVT

qs = qb

inversionlayer


Lower the Surface Barrier

Slide 12

VGS > VTVDS > 0 (net source-to-drain current flow)Carriers easily overcome source barrierSurface is strongly inverted

VGS VTVDS = 0 (no net current)Source barrier loweredSurface is inverted

VGS = 0VDS = 0 (no current)Large source barrier(back-to-back diodes)

electroncurrent

Sze [3]


Quantifying Charge to Move s by 2b

Slide 13

• Assume uniformly doped p-type body

• How much body must be depleted to reach strong inversion?

––

––

––

––

––

qN

xdgate

++++++

++++ body

NqNx bSi

d122

ddep qNxQ

x

V

0 xd

2b

Si

db

qNx

2

22

dxEV

xE0

xd

Si

dqNx

Si

QdAE


Short-Channel Effects (SCEs)

VDD not scaling as aggressively as L Higher channel electric fields

– Velocity saturation– Mobility degradation

Slide 14

gate

n+

sourcen+

drain

source-to-bodydepletion

drain-to-bodydepletion

L

L

VT

VDS

VT

DIBL


Overcoming Short-Channel Effects

Improve gate electrostatic control of channel charge• Higher body doping but higher VT

• Shallower source/drain but higher Rs

• Thinner tox but higher gate leakage• High-K dielectric to reduce tunneling• Metal gate to overcome poly depletion• Fully-depleted structures (e.g., fins)

Stressors for mobility enhancement

Slide 15

gate

n+

sourcen+

drain

dopingx j

1


Not So Fundamental After All

• Body doping has increased by 2–3 orders of magnitude over the decades

• Surface way more conductive at strong inversion condition using “fundamental” VT definition

• What matters is how much OFF leakage you get for a given ON current

• IDoff vs. IDsat (or IDeff) universal plots have become more useful to summarize device performance

Slide 16

M O S

Energy Band

Diagram

fsfs

qb

qfsqVT

qs = qb

inversionlayer

ox

depbFBT C

QVV 2


IOFF–ION Universal Plots

Slide 17

Comparison of 90nm Technology Foundry Vendors

1.2V1.0V1.2V1.0V

NMOSPMOS

0.1

1.0

10.0

100.0

1000.0

0 200 400 600 800 1000 1200

OFF

Lea

kage

Cur

rent

(nA

/m

)

ON Drive Current (A/m)

• High ION high IOFF & low ION low IOFF

• OFF leakage prevents VT from scaling with gate length• Multiple VT’s enable trade-off between high speed vs. low leakage

log (IDS)

VGSVT1 VT2

IOFF1

IOFF2

VDD

ION1ION2


drawn

drawnDS L

WIIGST VV

0

• Onset of strong inversion near impossible to measure

• Sweep log IDS vs. VGS

• Find VGS when IDS crosses user-specified threshold I0normalized to W/L

VGS

log IDShigh VDS low VDS

I0×W/L

VTsat VTlin

• Foundry-specific I0 ~ 10 to 500 nA• No physical connection to

“fundamental” VT definition

DIBL

Slide 18

Constant-Current VT Measurement


Subthreshold Leakage

Slide 19

• MOSFET is not perfectly OFF below VT it’s just a BJT• VG s lower source-to-channel barrier• Gradually more carriers diffuse from source to drain• Capacitive divider between gate and undepleted body

Cox

CSibody

gate

VG

VB

source

drainVG

Siox

oxGs CC

CV

source drain

s


Subthreshold Slope

Slide 20

• Planar 28nm: S = 100–110mV/dec at 25°C

• Want tight coupling of VG to s but have to overcome CSi

• Large Cox thinner gate oxide, HKMG• Small CSi lower body doping, FD-SOI, finFET• Get diode limit when Cox & CSi 0 (η = 1)

• Reducing S enables lower VT , VDD & power for same IOFF

ox

SioxB

CCC

qTkS

10ln

VB

VG

s

ox

Siox

CCCdecmVS

/60 at 25°C

• VG needed for 10 change in current

CSi

Cox


Drain-Induced Barrier Lowering (DIBL)

Slide 21

• OFF leakage gets worse at higher VD

• E field from drain charge terminating in body, reducing gate charge required to reach VT

• Characterized as VT reduction for some VD

• Planar 28nm: 150–160mV for VD =1V• Reducing DIBL also enables lower VDD & power for same IOFF

reduction of barrier heightat edge of source

VDD

source draingate

source drain

–

+++++

–––

–

–

+

+++++++ +

––

––

–––

–

E field


Benefits of Lower DIBL & S

Slide 22

log (IDS)

VGSVTsat VTlin

IDoff

VDD

IDsatIDlin

log (IDS)

VGSVDD

log (IDS)

VGSVDDVTsat VTlin

IDoff

IDsatIDlin

Same SLower DIBL

Lower SSame DIBL

Maintain IDsat & IDoff

VTsat VTlin

IDsatIDlin

IDoff

• Combination of reduced DIBL & S is key to enabling lower VDD& power for same IDsat & IDoff

S

DIBL


3-Way Competition for Body Charge

Slide 23

What’s happening to surface potential?

p-well

gate

VB

source

drain

VD

drain

VG

VD

source

drainVG

source

drain|VB|

DIBL

bodyeffect

gate control(what we want)


The Roads to Higher Performance

Slide 24

sourcedrain

channel

Decrease L – steepen the hill

sourcedrain

channellithographyscaling

Increase µ – move carriers faster

sourcedrain

channel

strain engineering

sourcedrain

channelIncrease Cox – move more carriers

high-K dielectricmetal gate

Must contain parasitic R & C from undoing all the IFET gains


OutlinePart 1



Slide 25


130nm MOSFET Fabrication

Slide 26

Well Implantation

2 n-well p-well

Gate Oxidation &Poly Definition

3

gate oxide

Source/Drain Extension& Halo Implantation

4halos

Spacer Formation &Source/Drain Implantation

5

Salicidation

6

silicide

PMOS NMOS

Shallow Trench Isolation

1 STIoxidep-Si substrate


Shallow Trench Isolation

Slide 27

1

2

3

4

5

Advantages over LOCOS• Reduced active-to-active

spacing (no bird’s beak)• Planar surface for gate

lithography

Deposit & pattern thin Si3N4etch mask & polish stop

Etch silicon around active area –profile critical to minimize stress

Grow liner SiO2, then deposit conformal SiO2 – void-free deposition is critical

CMP excess SiO2

Recess SiO2Strip Si3N4 polish stop


p-wellSTIoxide

STIoxide

Well Implant EngineeringRetrograded well dopant profile for n-well AND p-well too(implants before poly deposition)

Shallow/steep surface channel implant • VT control• Slow diffusers critical (In, Sb)

Very deep high-dose implant• Latchup prevention• Noise immunity• Faster diffusers (B, As/P)

Sequence implant to reduce ion channeling, especially for shallow implant

Depth

SubstrateDoping

substratebackground

Deeper subsurface implant• Extra dopants to prevent subsurface

punchthrough under halos• Prevent parasitic channel inversion on

STI sidewall beneath source/drain• Faster diffusers (B, As/P)

Slide 28


Poly Gate Definition

Si substrate

• Process control is everything – resist & poly etch chamber conditioning is critical (don’t clean residues in tea cups or woks)

• Trim more for smaller CD (requires tighter control)• Less trimming if narrower lines can be printed

poly-Si

1 2 3

anti-reflection layer (ARL)

gateoxide

resist

Pattern resist Trim resist (oxygen ash)

Etch gate stack

polygate

• Gate CD way smaller than lithography capability

Slide 29


Channel & Source/Drain Engineering

Slide 30

polygate

self-aligned source/drain extension implant (n-type)

p-well

1

dielectric spacerformation

p-well

polygate3

self-aligned source/drain implant (n-type)

4

p-well

polygate

halos

self-aligned high-tilt halo/pocket implant (p-type)

p-well

polygate2


Benefits of Halo and Extension

Slide 31

Resulting structure• Less short-channel effect• Shallow junction where

needed most

polygate

halos

Not to be confused with LDD in I/O FET• Same process with spacers but Iightly doped drain (LDD) is

used for minimizing peak electric fields that cause hot carriers & breakdown

• Extensions must be heavily doped for low series resistance

extensions


Self-Aligned Silicidation (Salicidation)

Slide 32

• Need to reduce poly & diffusion Rs, or get severe IFET degradation

1

Deposit sicilide metal (Ti, Co, Ni)

RTA1 (low temperature)Selective formation of metal silicide from metal reaction with Si

welldiffusion

2

Strip unreacted metal

3

RTA2 (high temperature)Transforms silicide into low-phase by consuming more Si

4

poly

STI

• TiSix CoSix Ni/PtSix• Scaling requires smaller grain size to minimize Rs variation


OutlinePart 1



Slide 33



Slide 34

sourcedrain

channel


sourcedrain



sourcedrain

channel

strain engineering

sourcedrain




Let There Be Light

Slide 35

Resolution = k1

NA

• Tooling has traditionally driven resolution scaling• Shorter : 436nm 365nm 248nm 193nm• Higher NA lenses capping at 1.35

/ N

A (n

m)

• Both and NA have hit a wall

• No new litho tool for 16/14nm (EUV not primetime yet)

• Single patterning limited to ~80nm pitch

• Double/triple patterning very expensive

Wei, GlobalFoundries [5]

© Loke, The Journey to FinFETs Slide 36

Step-and-Scan Projection Lithography• Slide both reticle & wafer across narrow

slit of light

• Only need high-NA optics orthogonal to scan but now high-precision constant-speed stages to move mask & wafer

• Cheaper than high-NA 2-D optics

• 6” x 6” physical reticle size (4× reduction)

• 25 x 33mm or 26 x 32mm field size

• Weak intensity of deep-UV source requires sensitive chemically-amplifiedresists for better throughput

• Enables dose mapping (adjust light dose during scan to compensate for loading)

Slit SourceExcimer Laser

KrF (248nm) or ArF (193nm)


Immersion Lithography

Slide 37

NA = n sin = d / 2 f

Resolution =k1

NA

lenswater

12-inch wafer

light

• Remember oil immersion microscopy in biology class?• Extend resolution of refractive optics by squirting water

puddle on wafer surface prior to exposure• nwater ~1.45 vs. nair ~ 1• Tedious but EUV is not primetime yet

• More light bending collect higher orders of light


Resolution Enhancement Technology

Slide 38

• Reducing k1 is the remaining ticket to better resolution• Attack problem from all fronts: mask, source & wafer• Imposes significant restrictions on layout design rules

Resolution = k1

NAR

ayle

igh

k 1Fa

ctor

Wei, GlobalFoundries [5]


Mask – Optical Proximity Correction

Slide 39

Non-Optimized Optimized

Mask

ResistPattern

• Sharp features are lost because diffraction attenuates higher spatial frequencies (mask behaving as low-pass optical filter)

• Compensate for diffraction effects when feature sizes << by managing sub- constructive & destructive interference

• Exaggerate edges and corners to “equalize” cutoff spatial frequency of mask

Plummer et al., Stanford [6]


Mask – Sub-Resolution Assist Features

Slide 40

• Difficulty to concurrently print dense and isolated lines• SRAFs are features intentionally placed on mask that are

too small to print but provide enough diffraction to make isolated features print well

• Imposes forbidden pitches on layout

SRAFs

Sivakumar, Intel [7]


Mask – Phase Shift

Slide 41

• Create differential optical path length to invert electric field of adjacent features



Source – Off-Axis Illumination

Slide 42

• Offers significant boost in resolution• Imposes restrictions in orientation & pitch


-2


Source – Aperture Shape Optimization

Slide 43

• Keep pixels that contribute to image enhancement• Discard pixels that degrade image contrast



Double Patterning by Pitch Division

Slide 44

Litho-Etch-Litho-Etch (LELE) Litho-Freeze-Litho-Etch (LFLE)


• Misalignment between Patterns 1 & 2 complexity with mask decomposition (coloring), design rules & models


Multiple Patterning with Cut Masks

Slide 45

• Extra mask to cut or “slice through” patterns • Significantly reduces end-to-end spacing for area reduction• e.g.

• Gate lithography at 45nm• Metal-1 lithography at 22nm

Auth et al., Intel [4]

Intel 45nm SRAMIntel 65nm SRAM


OutlinePart 1



Slide 46



Slide 47

sourcedrain

channel


sourcedrain



sourcedrain

channel

strain engineering

sourcedrain




Mechanical Stresses & Strains

Slide 48

AreaForceStress

atomic spacing > equilibrium spacing

Tension(positive stress)

Compression(negative stress)

atomic spacing < equilibrium spacing

vs.

0

Strain

• Stretching / compressing FET channel atoms by as little as 1%can improve electron / hole mobilities by several times

• Strain perturbs crystal structure (energy bands, density of states, etc.) changes effective mass of electrons & holes

• Increase ION for the same IOFF without increasing COX


Longitudinal Uni-Axial Strain

Slide 49

tension (stretch atoms apart) faster NMOS

compression (squeeze atoms together) faster PMOS

• Most practical means of incorporating strain for mobility boost• Want 1-3GPa (high-strength steel breaks at 0.8GPa)• How? Deposit strained materials around channel

• Material in tension wants to relax by pulling in• Material in compression wants to relax by pushing out


Transferring Strain from Material A to B

Slide 50

A AB

A AB

A AB

more A

less B

limitedscalability

need short channel


Ways to Incorporate Uni-Axial Strain

Slide 51

• NMOS wants tension, PMOS wants compression

• Un-Intentional (comes for free)• Shallow Trench Isolation – NMOS / PMOS

• Intentional (requires extra processing)• Stress Memorization Technique – NMOS • Embedded-SiGe Source/Drain – PMOS • Embedded-SiC Source/Drain – NMOS • Dual-Stress Liners – NMOS & PMOS • Compressive Gate Fill – NMOS / PMOS

• Strain methods are additive


Shallow Trench Isolation (STI)NMOS & PMOS

• STI oxide under compression• High-Density Plasma CVD SiO2 process (alternating deposition/etch)

deposits intrinsically compressive oxide for good trench fill• 10 CTE mismatch between Si & SiO2 increases compression when

cooled from deposition temperature• Migrated to High Aspect Ratio Process (HARP) fill in recent nodes less compressive oxide

Plummer et al., Stanford [5]


Stress Memorization Technique (SMT)NMOS

Slide 53

Ion (µA/µm)

I off(A

/µm

)

600 800 1000 1200 140010-9

10-8

10-7

10-6

10-5

control

disposable tensile nitride

stressor

tensile

Amorphize poly & diffusion with silicon implant

Deposit tensile nitride

Anneal to make nitride more tensile and transfer nitride tension to crystallizing amorphous channel

Remove nitride stressor (tension now frozen in diffusion)

1

2

3

4

Chan et al., IBM [9]


Periodic Table Trends

Slide 54

lattice spacing bandgap

• Compound semiconductor like SixGe1-x has lattice spacing & bandgap between Si & Ge

• Same idea with SixC1-x


Embedded-SiGe Source/Drain (e-SiGe)PMOS

Slide 55

P

P

Etch source/drain recess

Grow SiGe epitaxially in recessed regions

2

SiGe SiGe

• SiGe constrained to Si lattice will be in compression

• Compressive SiGe source/drain transfers compression to Si channel

Ion (µA/µm)

I off

(A/µ

m)

200 300 400 500 700

10-9

10-8

10-7

600

1

L=35nm

SiGe

L=35nmL=35nm

SiGe

• e-SiC is similar but introduces tension instead• Epitaxial SiC much tougher to do than SiGe



Dual-Stress LinersNMOS & PMOS

• Deposit tensile/compressive PECVD SiN (PEN) liners on N/PMOS• Liner stress is dialed in by liner deposition conditions (gas flow,

pressure, temperature, etc.)

TPEN for NMOS CPEN for PMOS

tensile compressive

tensile compressive



Strain Relaxation

Slide 57

When materials of different strain come together…

Material A Tensile Material B Compressive

• Both materials will relax at the interface• Extent of relaxation is gradual, depends on distance from interface• No relaxation far away from interface

interface


Strain Depends on Channel Location

Slide 58

Xi et al., UC Berkeley [10]

• SA, L & SB specify where channel is located along active area

SA L SB

• Critical for modeling device mobility change due to STI, SMT, e-SiGe, etc.

• Strain at source & drain ends of channel may be different

• Important consideration for matching, e.g., current mirrors

• Concavity & stress polarity vary with stressors in given technology but concept still applies

STIeffectonly


OutlinePart 1



Slide 59



Slide 60

sourcedrain

channel


sourcedrain



sourcedrain

channel

strain engineering

sourcedrain




Direct Tunneling Gate Leakage

Slide 61

• tox had to scale with channel length to maintain gate control

• Less SCE• Better FET performance

• Significant direct tunneling for tox< 2nm

EOT (Å)0 5 10 15 20 25 30

Gat

e Le

akag

e (A

/cm

2 )

10-510-410-310-210-1100101102103104

High PerformanceLow PowerSiO2 TrendlineNitrided oxide

McPherson, Texas Instruments [12]

EOT = Equivalent Oxide Thickness

• High-K gate dielectric achieves same Cox with much thicker tox

EOTtC ox

gate

gateox


• Even heavily-doped poly is a limited conductor• Discrepancy between electrical & physical thicknesses since charge

is not intimately in contact with oxide interface

surface charge centroid few Å’s awayfrom oxide interface

n+ poly gate

p-well

gate oxide

poly depletion (band bending)

gate charge centroid few Å’s away from oxide interface

Wong, IBM [13]

Cox

1.5nm (15Å)

poly-Sigate

Sisubstrate

gateoxide

Poly Depletion & Charge CentroidDielectric Only Half the Story


Enter High-K Dielectric + Metal-Gate

Slide 63

• High-K Dielectric (HK)• Hf-based material with K~20–30 (Zr-based also considered)• Need to overcome hysteretic polarization• High deposition temperature for good film quality

• Metal-Gate (MG)• Thin conductive film intimately in contact with high-K dielectric

to set gate work function M VFB VT• Want band-edge M, i.e., NMOS @ EC & PMOS @ EV

(just like n+ poly & p+ poly) different MG for NMOS & PMOS• Typically complex stack of different metal layers secret sauce• Conductive fill metal on top of M-setting metal-gate

• Key challenges• INTEGRATION, INTEGRATION, INTEGRATION• M shifts when exposed to dopant activation anneals• Getting the right VT for both NMOS & PMOS


Atomic Layer Deposition

Slide 64

• Deposit monolayer at a time using sequential pulses of gases • Introduce one reactant at a time & purge before introducing next

reactant• Key to precise film thickness control of HKMG stack • e.g., SiO2 (SiCl4+H2O) HfO2 (HfCl4+H2O) TiN (TiCl4+NH3)

Introduce pulse of HfCl4 gas

Monolayer adsoprtion of HfCl4 Introduce pulse of H2O gas

Surface reaction to form HfO2repeat cycle for desired number of monolayers

ICKnowledge.com [14]


HK-First / MG-First Integration

Slide 65

• Obvious extension of poly-Si gate integration• Seems obvious & “easy” at first but plagued with unstable work

function when HKMG is exposed to activation anneals• Especially problematic with PMOS VT coming out too high

Deposit HKDeposit MG1

Pattern MG1Deposit MG2

Pattern MG2Deposit gatePattern gates / MGs / HK

Implant/anneal S/ D Form silicideDeposit/CMP ILD0Form contacts

321 4


GlobalFoundries 32nm-SOI

Slide 66

Horstmann et al., GlobalFoundries [15]

poly/SiON HKMG

+35%

IDsat (µA/µm)

IDof

f(nA

/µm

)

poly/SiON HKMG

+25%

IDsat (µA/µm)

IDof

f(nA

/µm

)

NMOS PMOS

epi-cSiGe to set channel M


HK-First / MG-Last Integration

Slide 67

• High thermal budget available for middle-of-line• Low thermal budget for metal gate more gate metal choices• Enhanced strain when sacrificial poly is removed & resulting

trench is filled with gate fill metal

Deposit HK / gatePattern gate / HK

Implant/anneal S / DForm silicideDeposit ILD0CMP ILD0 to expose top of gateRemove gate

Deposit MG1Pattern MG1Deposit MG2Pattern MG2

Deposit gate-fillCMP gate-fill / MGsDeposit more ILD0Form contacts

321 4


Intel 45nm

Slide 68

NMOS PMOS



HK-Last / MG-Last Integration

Slide 69

• Same advantages as HK-first / MG-last integration• Overcomes EOT scaling limitations in HK-first / MG-last• Need to postpone silicidation to after opening source/drain etch• DSL relax & no longer useful since contacts cut through FET width• Tough to keep traditional unsilicided poly resistor MOL resistor

Deposit oxide / gatePattern gate / oxide

Implant/anneal S / DDeposit ILD0CMP ILD0 to expose top of gateRemove gate/oxide

Deposit HKDeposit MG1Pattern MG1Deposit MG2Pattern MG2

Deposit gate-fillCMP gate-fill / MGsCut to expose activeForm silicideDeposit / CMP ILD0Pattern/form contacts

321 4


Intel 32nm

Slide 70

Packan et al., Intel [16]


Gentlemen, at this point, reality set in…

Slide 71

What’s next???


OutlinePart 1



Slide 72


Partially-Depleted Silicon-On-Insulator

Slide 73

• Pros• Dynamic threshold effect (s coupling to VG edge)• Low junction area capacitance• No VT increase for stacked FETs• 4 lower SRAM soft-error rate• Body isolation from substrate noise• Simpler isolation process, reduced well proximity effect

• Cons• Body hysteresis effect – floating body gets kicked around

• Requires conservative margining for digital timing • Major pain for analog/mixed-signal design

• Substrate heating – buried oxide is good insulator• More expensive substrate, and from a single supplier

buried oxidesubstrate

STI STISTI


The Dreaded Hysteresis Effect

Slide 74

• Floating body is coupled to source, gate, drain & body• Body voltage has memory or history of other terminals, analogous to

intersymbol interference in wireline I/O • Floating body voltage noise VT noise ID noise• Can get hysteresis in bulk if ZSUB is too high

p-well

substrate

buried oxide

n+ source

n+ drain

undepletedfloating body

poly gate

VD

VG

VSUB

ZSUB


What Does Fully-Depleted Really Mean?

Slide 75

• Consider what happens when SOI layer thins down

• Conservation of charge cannot be violated• So once body is fully depleted, extra gate charge must be balanced

by charge elsewhere, e.g., beneath buried oxide• If substrate is insulator, then charge must come from source/drain• No floating body in fully-depleted no hysteresis

p-well

substrate

buried oxide

source drain

p-well

substrate

source drain

fully-depleted when turned on

depletion region

depletion region


• VGS modulates surface charge density under gate dielectric Modulate IDS when VDS ≠0Need band bending at

surfaceNeed electric field for

band bendingNeed + & – charge

separation between gate & body beneath surface

• Do we really need dopants in the body to create field effect?

––

––

––

––

––

qN

xdgate

++++++

++++ body

x

V

0 xd

2b

xE0

xd

Si

dqNx

Requirement for Field-Effect Action

x


Ground-Plane MOSFET

Yan et al., Bell Labs [17]

• Extremely retrograded well profile with no surface dopants• Depletion region cannot extend beyond buried pulse of dopants• All you fundamentally need for field-effect action is a parallel-plate

capacitor with gate dielectric & undoped semiconductor in between plates dopants are not required in the body


––

––

– –

––

––

gate++++++

++++ body

x

V

0

inv

xE0

Just Like a Parallel-Plate Capacitor

x M O S

qb=0

qVT

qs = qinv

stronglyinverted

qs

ox

depbFBT C

QVV 2

• Classic VT equation no longer has meaning because b=0

• inv is somewhat arbitrary


p-well

substrate

source drain

depletion region

• Basic idea: effectively no charge in body Body cannot terminate field lines from source & drain Field lines from source & drain forced to move down to substrate Source to body surface barrier not impacted by shorter gate length

• Substrate must be close to source & drain to prevent field lines from drain to terminate to source

• Ideally no body dopants less scattering higher µ• Need to re-adjust gate work functions since accumulation-to-inversion

transition requires less gate voltage

Why Fully-Depleted Suppresses SCE


Benefits of Lower DIBL & S

Slide 80

log (IDS)

VGSVTsat VTlin

IDoff

VDD

IDsatIDlin

log (IDS)

VGSVDD

log (IDS)

VGSVDDVTsat VTlin

IDoff

IDsatIDlin

Same SLower DIBL

Lower SSame DIBL

Maintain IDsat & IDoff

VTsat VTlin

IDsatIDlin

IDoff

• Combination of reduced DIBL & S is key to enabling lower VDD& power for same IDsat & IDoff

S

DIBL


The Big Deal with Lower DIBL

Slide 81

Higher performance for the same IDsat & IDoffL. Wei et al., Stanford [18]


Taxonomy of Fully-Depleted Options

Slide 82

Fully-Depleted

Planar 3-D(Dual- or Tri-Gate FinFET

FD-SOI Ground-plane Bulk MOS SOI Bulk


Fully-Depleted Planar on SOI

Slide 83

K. Cheng et al., IBM [19]

• a.k.a. ET (Extremely Thin) or UTBB (Ultra-Thin Body & BOX) SOI to refer to very thin SOI and Buried Oxide (BOX) layers

• SOI Si layer is so thin that charge mirroring gate charge comes from beneath BOX

• Made sense as a stepping stone from convention planar to finFETs

buried oxide

substrate

thick to reduce series resistance & apply stress


Thin BOX to Suppress SCE

Slide 84

• If body is fully depleted, field lines from drain cannot terminate in the body since there’s no charge to terminate to no DIBL

• Charge elsewhere must be nearby or field lines from drain will terminate on source charge

• However, lateral field always present when VDS≠0

T. Skotnicki, STMicroelectronics [20]


Performance Tuning with Backgate Bias

Slide 85

Yamaoka et al., Hitachi [21]

• Like “body effect” in planar bulk with CSi spanning SOI & BOX• Backgate bias can modulate both NMOS and PMOS VT at 80mV/V• Not option in finFETs but finFET subthreshold slope is better

T. Skotnicki, STMicroelectronics [22]


Fully-Depleted Planar on Bulk

Slide 86

Fujita et al., Fujitsu & SuVolta [23]

1 Low-doped layer for RDF reduction (fully depleted)

2 VT setting layer for multiple VT devices3 Highly-doped screening layer to

terminate depletion4 Sub-surface punchthrough prevention

• Reduced RDF for tighter VT & lower SRAM VDDmin• Improved DIBL but not S


Random Dopant Fluctuation (RDF)

Slide 87

0

10

20

30

40

50

130nm 90nm 65nm 45nm

minimumlengthNMOS

VT

(mV

)

Auth, Intel [7]

• RDF more prevalent with scaling since number of dopants is decreasing with each MOS generation

• Why does RDF impact magically disappear in fully-depleted?

??


RDF in Conventional MOS

Slide 88

• Back to basics• Conservation of charge• Electric field lines start at +ve charge & end at –ve charge

• Number of dopant atoms vary from FET to FET• BUT dopant atoms also vary in location

• Lengths of field lines exhibit variation• Integrated field (voltage or band bending) has VT variation

poly gate

n+

sourcen+

drain– – –

+

– – –

–

+ + ++ + + ++ + + +

–

–– – –

dxEV

partially depleted


Why Fully-Depleted Eliminates RDF

Slide 89

poly gate

n+

sourcen+

drain– – –

+

– – –

–

+ + ++ + + ++ + + +

–

–– – –

poly gate

n+

sourcen+

drain

+ + + ++ + + ++ + + +

– – – – – – – – – – – –

undoped

partially depleted fully depleted

• In fully-depleted SOI, field lines from gate cannot terminate in the undoped body (no charge there)

• Mirror charges are localized beneath BOX• Lengths of field lines have tight distribution small VT variation• However, VT now very sensitive to dimensional & geometry

variation, e.g., SOI and BOX thickness• Unfortunately, new sources of variation becoming important,

e.g., MG grain orientation


OutlinePart 1



Slide 90


What is Fully-Depleted Tri-Gate?

Slide 91

M. Bohr, Intel [25]

32nm planar 22nm tri-gate

• Channel on 3 sides• Fin width is quantized (SRAM & logic

implications)• Fin so narrow that gate mirror charge

must come from fin baseHu, UC Berkeley [24]


Tri-Gate FinFETs in Production

Slide 92

Truly impressive!!!fingate

32nm planar 22nm tri-gate

M. Bohr, Intel [25]


Conventional Wafer Surface Orientation & Channel Direction

Slide 93

0° notch

x (100)

y (010)

z (001)

(100)

• Wafer normal is (100), current flows in <110> direction• Tri-Gate FinFET: top surface (100), sidewall surfaces (110)


Mobility Dependence on Surface Orientation & Direction of Current

Slide 94

NMOS PMOS

Yang et al., IBM [26]

• Strain-induced mobility boost also depends on surface orientation & channel direction – not as strong for current along sidewalls vs. top of fin

top of fin

sidewalls of fintop of fin

sidewalls of fin


Fin Patterning – Sidewall Image Transfer

Slide 95

• Standard approach for patterning fins down to 40nm pitch

• Sometimes called SADP (Self-Aligned Double Patterning)

• Recursive process for even finer fin pitch (SAQP)

• Cut-first vs. cut-last integration to remove unwanted fins

1 Deposit & pattern sacrificial mandrel

2 Deposit & etch spacer

4 Etch target material using spacer as hard mask

5 Remove spacer mask

substrate to etch

mandrel

spacer

3 Remove mandrelhard mask

for patterning


Process Flow Summary I

Slide 96

• Pattern fins• Deposit/CMP STI oxide• Recess STI oxide sets fin height• Deposit, CMP & pattern poly

fin

gate oxide on top & both sidewalls of fin

• Deposit spacer dielectric & etch, leaving spacer on gate sidewalls

• Spacer must be removed on fin sidewall

Paul, AMD [27]

STI oxide


Process Flow Summary II

Slide 97

• Recess fins• Grow Si epitaxially to merge fins

together for reduced source/drain resistance (spacer prevents short to gate)

• Induce uni-axial channel strain by growing e-SiGe or e-SiC

• Dope source/drain dopants with in situ doping during epi

• Deposit ILD0 & CMP to top of poly• Do replacement-gate HKMG

module• Deposit & pattern contact dielectric• Form trench contacts (note

overlap capacitance to gate)

epigrowth

trench contact

metal gate

Paul, AMD [27]


Some Tri-Gate Considerations

Slide 98

• Field lines of from gate terminates at base of fins

• Fin base must be heavily doped for fin-to-fin isolation

• Dimensional variation of fins device variation

• Current density is not uniform along width of device – VT & S varies along sidewall

• Series resistance vs. overlap capacitance

• “Dead” space between fins

trench contact

metal gate


Pacifying The Multi-VT Addiction

Slide 99

• 8 VT’s typical in 28nm (NMOS vs. PMOS, thick vs. thin oxide)• Methods of achieving multiple VT

1. Bias channel length• Exploit SCE (VT rolloff with shorter L)• Increase L for lower ION & IOFF

2. Implant fin body with different dose• Field lines from gate must “work through” available

body dopants before terminating at base of fin• Prone to RDF

3. Integrate more metal gate M • Already 2 M s in standard HKMG flow• More complex integration• Metal boundary effect


Intel 22nm TEM Cross-Sections

Slide 100


Single fin (along W)

Epi merge (along W)

NMOS (along L)

PMOS (along L)


Intel 22nm Performance at 0.8V

Slide 101

0.1

1

10

100

1000

0.6 0.8 1 1.2 1.4 1.6

IOFF

(nA

/m

)

IDSAT (mA/m)

VDD = 0.8V

HP: 1.26 mA/m

MP: 1.07 mA/m

SP: 0.88 mA/m

32nm

0

1

10

100

1000

0.6 0.8 1 1.2 1.4IO

FF (n

A/

m)

IDSAT (mA/m)

VDD = 0.8V

HP: 1.10 mA/m

MP: 0.95 mA/m

SP: 0.78 mA/m

32nm

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.6 -0.2 0.2 0.6 1.0

IDSA

T (A

/m

)

VGS (V)

0.80V

SS ~69mV/decDIBL ~46 mV/V

SS ~72mV/decDIBL ~50 mV/V

NMOSPMOS

0.05V

0.80V

0.05V


NMOS

PMOS


Intel 22nm Self-Aligned Contacts

Slide 102


• Nitride cap on gate to prevent contact-to-gate shorts due to contact-to-gate misalignment

• Contacting transistors is a huge challenge in 22nm onwards typically a dominant issue during yield ramp

• Expect growing & significant complexity in MOL (Middle-Of-Line)


Intel 14nm Announcement

Slide 103

Intel [29]• More details from Intel at IEDM 2014


Conclusions

Slide 104

• Digital needs will continue to drive CMOS scaling but rising wafer cost pressure will restrict what moves to the latest node

• Expect new learning & surprises in 16/14nm & 10nm as we cope with fin design & layout

• Designers with good technology knowledge are best positioned for silicon success

• Exciting time to be designing


References[1] M. Keating, “Science fiction or technology roadmap: a look at the future of SoC design,” in SNUG San Jose Conf., Mar. 2010.[2] M. Na et al., “The effective drive current in CMOS inverters,” in IEEE Int. Electron Devices Meeting Tech. Dig., pp. 121–124, Dec. 2002. [3] S.M. Sze, Physics of Semiconductor Devices (2nd ed.), John Wiley & Sons, 1981.[4] C. Auth, “45nm high-k + metal-gate strain-enhanced CMOS transistors,” in IEEE Symp. VLSI Technology Tech. Dig., pp. 128–129, Jun. 2008.[5] A. Wei, “Foundry trends: technology challenges and opportunities beyond 32nm,” in IEEE Vail Computer Elements Workshop, Jun. 2010. [6] S. Sivakumar, “Lithography for the 15nm node,” in IEEE Int. Electron Devices Meeting Short Course, Dec. 2010. [7] J. Plummer et al., Silicon VLSI Technology– Fundamentals, Practice and Modeling, Prentice-Hall, 2000.[8] www.soitec.com[9] V. Chan et al., “Strain for CMOS performance improvement,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 667–674, Sep.2005. [10] X. Xi et al., BSIM4.3.0 MOSFET Model – User’s Manual, The Regents of the University of California at Berkeley, 2003 [11] J. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 1–8, Sep.2010.[12] J. McPherson, “Reliability trends with advanced CMOS scaling and the implications on design,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 405–412, Sep. 2007.[13] P. Wong, “Beyond the conventional transistor,” IBM J. Research & Development, pp. 133–168, vol. 2-3, no. 46, Mar. 2002.[14] www.ICKnowledge.com[15] M. Horstmann et al., “Advanced SOI CMOS transistor technologies for high-performance microprocessor applications,” in Proc. IEEE Custom Integrated Circuits Conf.,

pp. 149–152, Sep. 2009.[16] P. Packan et al., “High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors,” in IEEE Int. Electron Devices Meeting Tech. Dig.,

pp. 1–4, Dec. 2009.[17] R.-H. Yan et al., “Scaling the Si MOSFET: From bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704–1710, Jul. 1992.[18] L. Wei et al., “Exploration of device design space to meet circuit speed targeting 22nm and beyond,” in Proc. Int. Conf. Solid State Devices and Materials, pp. 808–809,

Sep. 2009.[19] K. Cheng et al., “Fully depleted extremely thin SOI technology fabricate by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised

source/drain,” in IEEE Symp. VLSI Technology Tech. Dig., pp. 212–213, Jun.2009.[20] T. Skotnicki, “CMOS technologies – trends, scaling and issues ,” in IEEE Int. Electron Devices Meeting Short Course, Dec. 2010.[21] M. Yamaoka et al., “SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin BOX FD-SOI transistors,“ IEEE J. Solid-State

Circuits, vol. 41, no.11, Nov. 2006.[22] T. Skotnicki, “Competitive SOC with UTBB SOI,” in Proc. IEEE SOI Conf., Oct. 2011.[23] K. Fujita et al., “Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low power applications,” in IEEE Int. Electron Devices Meeting

Tech. Dig., pp. 32.3.1–32.3.4, Dec. 2011.[24] C. Hu, “FinFET 3D transistor and the concept behind it,” in IEEE Electron Device Soc. Webinar, Jul. 2011.[25] M. Bohr, “22 nm tri-gate transistors for industry-leading low power capabilities,” in Intel Developer Forum, Sep. 2011.[26] M. Yang et al., “Hybrid-orientation technology (HOT): opportunities and challenges,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 965–978, May 2006.[27] S. Paul, “FinFET vs. trigate: parasitic capacitance and resistance”, AMD Internal Presentation, Aug. 2011.[28] C. Auth et al., “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM

capacitors,” in IEEE Symp. VLSI Technology Tech. Dig., pp. 131–132, Jun. 2012.[29] www.intel.com/content/www/us/en/silicon-innovations/intel-14nm-technology.html

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