The Jasmine OpenSSD PlatformThe Jasmine OpenSSD

The Jasmine OpenSSD PlatformTheJasmine OpenSSDVersion 1.2

Developers FTLGuide

FTLGuidePlatform:Developer's

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Copyright 2011 VLDB Lab. All rights Rev.

Version 1.2

Revision historyreserved.Date Author Description20110427 imsangpil (Sungkyunkwan University) Initial release 1.0

20110520 imsangpil (Sungkyunkwan University) Section 2.2 update 1.1

20120112 imsangpil (Sungkyunkwan University) Section 2.2. 3 update 1.2

Developer's The Jasmine OpenSSD Platform: FTLGuide

The Jasmine OpenSSD Platform:FTLGuideContentsDevelopersPREFACE 4ABOUT THIS DOCUMENT 4

4 FURTHER READING 4

4

CHAPTER 1. GETTING STARTED TO DEVELOP AN FTL ....................................................... 51.1. DEVELOPMENT ENVIRONMENT 5

CHAPTER 2. FTL PORTING ................................................ ................................................ 72.1. PORTING GUIDE 7 2.2. P

ORTING

E

XAMPLE

G

REEDY

FTL 9 2.3. HOW TO VERIFY FTL OPERATIONS? .................................................. ................................................. 12 2.4. S

ETTING UP TO

13

CHAPTER 3. COMPILE, BUILD & INSTALL FIRMWARE ..................................................... 143.1. COMPILE & BUILD FIRMWARE 14 3.2.

15

CHAPTER 4. DEBUGGING TIPS ................................................ ........................................ 194.1. DEBUGGING WITH UART 19 4.2. D

EBUGGING WITH

RVD 21

The Jasmine OpenSSD Platform: FTL Developer's Guide

reserved.Copyright 2011 VLDB All rights reserved.

Version 1.2

PrefaceAbout this documentThis manual Co. of Indiana SpringsBarefoot

TM

Jasmine OpenSSDcontrollerbasedplatform in

developmentthe FTL is a guide article. The main information contained in this document is as follows.

• Jasmine OpenSSD development environment for platformguide

firmware build and installation• A description

• FTL (Flash Translation Layer), including porting and debugging guidegeneralthe developmentFTL

description ofprocess

Contentsof thisTechnical documents are to be written in the following 1.

order.Chapter Getting Started to Develop an FTL

FTL This chapter describes the porting Jasmine OpenSSD platform beforeproceduredevelopment

the forenvironment.2.

Chapter FTL Porting

This chapter describes the Jasmine OpenSSDnew platform for FTL scheme in the process of

introducedporting.3.

Chapter Compile, Build & Install Firmware

Firmware This chapter describes the process to compile and build the firmware is installed on the board andJasmine

explains the 4.

process.Chapter Debugging Tips

This chapter describes the Jasmine firmware code installed on the board to verify the behavior ofsome

an introduction todebugging tips.

Further reading• RealView Debugger User Guide for the http://infocenter.arm.com/help/index. jsp? topic = /com.arm.doc.subset.swdev.rvds / i ndex.html to refer to the documentation provided.

Feedback• OpenSSD project wiki page http://www.openssdproject.org/ wiki /

Chapter 1. Getting Started to Develop an FTLJasmine OpenSSD platform for this chapter before beginning the development of FTL developmentenvironment necessaryunderstanding

for and introduces the Environment. The key points in this chapter are as follows.

FTL development describes the hardware and software requirements for the

development environment guide provides

1.1. Development Environment

1.1.1. Requirement specificationJasmine OpenSSD platform in order to develop FTL is required infollowing

thecircumstances.

H / W requirement

• Test PC 1 대

perform communication with o Jasmine Board

• Client PC 1 대

o RVD (RealView Debugger), or using the debug UARTperforms

• Jasmine Board o NAND flash moduleequipped with a body, SATA cable, RS232 cable included

• RealView InCircuit Emulator (ICE) equipment (optional)

o ICE body, Ethernet / USB cable, JTAG connector cable, S / W requirement

• Operating System : Windows XP SP2

• Firmware compiled software

o RVDS (RealView Development Suite) 3.0 or higher

o or GNU Compilation toolchain (The Sourcery G+ + Lite Edition)

• Microsoft Visual Studio 8 o PATH environment variable, add: C: \ Program Files \ Microsoft Visual Studio 8 \ VC \

• Jasmine OpenSSDthe platform

• UART when usingfirmware,Hyper terminal program

1.1.2needs.Development environment setupbased on the requirements of clause 1.1.1 above, as shown in Figure 1 under the development Lab.

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environment.Copyright 2011 VLDB All rights Lab.

Version 1.2


Compile / Build & Debugging

Running host application

Figure 1) FTL Development Environment

• Test PC and Jasmine board connects to the power and SATA cables.

• RV ICE for debugging devices connected to the Ethernet or USB port,RS232

Test PCserial cable to the serial port andtheUART interface of the Jasmine

connect board.

• Client PC in RVDS, RV ICE software, firmware, software, and install the SSD.

o RV RV ICE debugger settings allow the board to recognize and Jasmine the.

NOTE: RV debugger debugging in fact if you do not that isthe host application

the benchmark usingor only when you are debugging using UART port Client PCa

without usingseparate Test PC is all you do.

Client PC

RealView ICE

Ethernet or USB port

SATA

BoardJasmine

PCTest

ARM7TDMIS core

Version 1.2

JasmineTheOpenSSD Platform: FTL Developer's Guide

Chapter 2.FTL PortingThis chapter describes the Jasmine OpenSSDplatform porting new FTL scheme you need to know to takeaatcontents.

lookthe

2.1. Porting GuideFTL is a course of action that exist in the DRAM and flash memory to read or write data towork

perform theeopdeung. In this section, the FTL in terms of hardware components, suchaccessiblethe main

should bebypart will be described in

2.1.1.ImplementationPortingFTL, FTL protocol API for developers, including the need to implement the following Description.

function.Source file Function / Installer / installer.c ftl_install_mapping_table

FTL NAND initial metadatato

flashis writtenperform the operation.installthe

Called together to firmware./ Ftl_ [scheme] / ftl.cftl_open

FTL performs the initialization process

NAND flashfrom the metadata

loaded and initialized

VBLK # 0 is written in the formatit ismarked,

ifnot format function call format

VBLK # 0, for areas withFTLmetaformat

exceptblocks ofdelete

recording ftl_read mark

ftl_writeread processing user data

user datawrite processing ftl_flush

SATA idle / standby time

periodicallyflush the metadata tooperations

perform

2.1.2. DRAM host buffer managementSATA interface, the actual user data is transmitted through the DRAM host buffer (ie SATA

read / write buffer) is buffered. In the case of a read request, event queuefromkeomaen read

receives a passDeATA,FTL FCP command is passed to the flash memory controllerthe NAND Flash

to read data fromSATA read preallocated buffer frame sewn up. In of a write

thecaserequest,the host write command to bring the requested data arrives SATA write bufferthe

fordata to be written to flash Lab.

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On the other hand, DRAM buffer management of the host SATA, FTL, andpointerbetween the hardwarethe buffermanager

adjust the viawhereabouts, flash memory and IO bandwidth of SATA performance differences

may occur due to collisions buffer pointer be. Therefore, when porting FTL, ftl_read / write

operation of the buffer pointer in the process of FTL and SATA conflict should be implemented carefully to avoid

alsoDRAM works by the host buffer is a circular queue, sothe buffer pointer mustonly

to increasebe adjustedarticle the.

NOTE: FTL port to be implemented using the library if the LLD LLDin the DRAMhost

Pointer to a bufferadjustments to the because you do not have to worry as separately. However,firmware

FCP developers to manually set the flash to pass commands to the controller if the

abovementionedmatters that should be noted.

2.1.3.DRAM access limitationDRAM ControllerBarefoot is to increase the reliability of data, the hardware ECC

engine.For this reason, CPU onto the DRAM changes or attempts to read the data directly from the

side, ECC parity information due to data loss or incorrect data surrounding the memory canread.

be Therefore, hardwareMemory utility (. / Include / mem_util.h)

usingDRAM data must be accessible. For example, DRAM present in the metadata,to

in orderchange it,and write_dram_xx read_dram_xx using such libraries,

DRAM reads the data from the SRAM, SRAM to DRAM data changed by the in

rereflecteda series of processes that should be performed (or use mem_copy)

In addition, mem_copy often referred to using the utility data to the SRAM and DRAM

caching allows, in some cases, better performance can be expected.

then it should be familiar with the operation of DRAM memory You will be summarized in a few restrictions:

1.Per default, 128 Byte 4 Byte ECC parity information is added to the

0.2.Therefore, the available area for DRAM 64MB * 128/132 = 65075200 Bytes becomes

0.3.DRAMtoDRAM, SRAMtoDRAM memory, be sure you work with

the hardware to use the Memory utility

4.DRAMtoDRAM memory copy is performed if the size must be copied

DRAM_ECC_UNIT (128 Byte) should be aligned with the size of

0.5.Accordingly, DRAM is the start address of the metadata declaration orDRAM_ECC_UNIT

BYTES_PER_SECTORit is preferable that the sizealigned.

2.1.4. NAND configurationBarefoot VBLK # 0 in the flash memory controller and firmware binary image and the meta information

(eg scan list), such as for storing purposes. Thus, FTL VBLK # 0 with exceptionthis

theofuser data and metadata blocks should be used for data

storage, whilemany FTL technique is proposed in the academic POR / SPOR FTL side consideringflashmetadata

thememory of the secondaryarea (spare area) to record the scheme. But Barefoot Kern

is a flash memory controller can not use the secondary zone limitations. Thus, the FTL

metadatablocks are allocated to a separate recorded.

2.1.5. Flash commandFTL IO request is passed to the flash memory, briefly describe the process of operation, the FTL is

FCP (Flash Command Port) by setting a Flash command WR (Waiting Room) to

deliver, andwhile the request is waiting on WR was that, NAND flash controller,the of the

thenstatusbank,the flash command to idle BSP (Bank Status Port) to be delivered.

NOTE: FCP, WR, and a description of BSP, refer to the Technical Reference Manual

that

while,WR queue depth of '1 'because it is a new flash before passing the command, WR

queued in the command must always ensure. If, WR command is already existingstandby

in the state in flash command to issue a new FTL, the existing command is executed,not be

that maysuch as to avoid the possibility of failure should be implemented with

caution. NOTE:./ Target_spw / flash.c you will see the flash_issue_cmd function.

(ADVANCED) Autoselect mode

Autoselect modeduring a write operation, the hardware automaticallyidle statethe

selects thebybank,IO can maximize parallelism. In order operate in this mode

toof FCP and then set FCP_BANK register 0x3F to pass the

2.2.Porting Example Greedy FTLJasmine Tutorial FTL firmware includes a simple garbage collection operations in addition to the page

mappingFTL of 'Greedy FTL' (. / Ftl_greedy / ftl.c) is implemented. Greedy FTLthe

as well asgarbagecollection function, normal poweon/off enable PowerOff Recovery

(POR) function is implemented. This chapter describes the implementation details of the Greedy FTL FTLmainly

portingfor when you need to implement features described below.

2.2.1.FTL initializationPendantJasmine board hardware components ftl_open initialization is done, the function is called totoFTL.

perform the operationinitialize the Greedy FTL below is a description of the initialization process:

1.build_bad_blk_list VBK # 0 by calling the function recorded in the scan list to

read and to write bad block bitmap table

0.2.VBLK # 0 is recorded in the format that does not mark, format operations are performed.

O format function SRAM / DRAM metadata Initializes and, VBLK # 0 except

the deletion area and the ability to perform the charge operation.

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o initialize the metadata recorded in the meta area of the NAND flash, VBLK # 0on the

markrecord format.

O If, format if you do not need to do, that is not the first case ofboot

NANDloading data from flash meth FTL

3.FTL initializes the buffer pointer.

2.2.2.SRAMmetadata SRAMFTL to manage the metadata, see very oftenrelatively small size of the Information

theThis.Greedy FTL FTL metadata area is for the user data area and a page index pointer

and the free block count, and statistical information, and to manage the SRAM.

2.2.3. Address mappingGreedy FTL is unlike Tutorial FTL, LPN bank for fixed address mapping methodimplemented.

to be In other words, a particular LPN is always only a particular bank read / write operationoccurring.

is to be LPN target bank in accordance with the modular NUM_BANKSoperation on the

seekmapping information is information only manages the VPN.

Random access IO This characteristic occurs, the parallelism is disadvantages

poor, butexist,sequential access IO, especially sequential read If the Tutorial FTL operations than one

can expect a good performance.

2.2.4. DRAM metadataFTL needs to manage the metadata size is larger than the available space, SRAM, DRAMinseparate

metadataa memory area should try to obtain. To this end, the ftl.h 'DRAM segmentation' part must be modified.

Meanwhile, Greedy FTL metadata managed by the DRAM is shown below.

Table 1) DRAM metadata for Greedy FTL

Metadata Description BAD_BLK_BMP

scan list obtained through the bad block list table for the bitmap. PAGE_MAP

logical page number to physical page number of the page mapping table for mapping. PAGE_MAP the size (totalnumber of logical blocks per block, the number of pages X X 4B)

isVCOUNT

validblock metadata for managing the number of pages as garbage

collection,when the sacrifice in order to manage the selected blocks metadata. The of VCOUNT

size(bank number X bank pervirtual block number X 4B) is

2.2.5. NAND Configuration

VBLK 0 1

2 ~ 31

n

Scan list

Size info. of

Misc. firmware image

metadata

imageFirmware binary

+

PAGE_MAP

VCOUNT

...

Figure 2) NAND configuration in Greedy FTL

Greedy FTLNAND flash is managed as in the Figure 2. POR loggingfor metadataFTL,

areausing which the exception of the area for recording user data is usedpurpose.

for the FTL metadata is metadata block is sequentially

recorded, whilethe blocks in the user area, such as under Figure 3 structure. The blockgroups withinpage,

number m ofthe home the page 0 to m2, the user data is recorded, and the last m1

th page 0 to m2, the page information is recorded in the LPN. This metainformationin a separate

is recordednature of the reason for Barefoot controller firmware isa separate page within the secondary zone

available ondo not have. LPN wrote about the future of garbage collection in the city, block

the user data is used to determine the Lab.

User data

LPN list

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validity.Copyright 2011 VLDB All rights 2.2.6.

User area

vpage 0

m1

areaFigure 3) Block structure of userin Greedy FTL

reserved.Garbage collectionGarbage collectionGreedy FTL longer write new data out in the absence of free

carriedspace.Sacrificial block selection policy is valid for the entire block with the smallest number of pagesblock

you select the(. / Ftl_greedy / ftl.c the get_vt_vblock ()), which is basically a separateis

page when copying garbage collectionto minimize the operation cost policy is.

NOTE: Greedy For more information on garbage collection policy papers under the sheets. Atsuo Kawaguchi andShingo Nishioka and Hiroshi Motoda, A FlashMemory Based File System, USENIX Winter, pp. 155164, 1995

under the Greedy FTL Figure 4 shows a garbage collection Lab.

Version 1.2

operation.Copyright 2011 VLDB All rights reserved.

Version 1.2

PAGE_MAP Victim VBLK # n

(VBLK # n) of LPN VPNVPNA VPNLPN list

00

LPN

VPNFC_CPBACK

B

11

A

C

22

E

list

D Invalid

... ...

Figure 4) Garbage Collection in Greedy FTL

First, DRAM meta table to navigate my VCOUNT VCOUNT the lowest value at a block

theexpense ofblock (VBLK # n) to choose. LPN in the block list, and read the last page

crowded. Determine the validity of the data block is sacrificed LPN LPN for the latest information and the list

that contains the data that matches the VPN information through PAGE_MAP to find out information oncomparison.

the VPN sacrificial block numbers in the figure of the first user data is recorded in the A LPN 0 time

againstcan be recognized that this data is the most recent data in order to determine whether thePAGE_MAP

LPN 0VPN number is mapped to confirm that the A Valid determine that it is. Only

about VPN B and C, as in the case of the address mapping information does not match the corresponding VPN

thedata ininvalid by the fact that it is obvious.

Thus determine the validity of the library page, the LLD using the copyback function to pre

Copy haejun suffered after empty block, delete the existing block. And metainformation changes FTL

to reflectVCOUNT PAGE_MAP and garbage collection by updating the meta tableoperation.

to finish the After that, go out and write new data from that block is.

2.2.7. POR (PowerOff Recovery)Greedy FTL is normally terminated when the Jasmine board supports the POR.the

IO request is received fromhostno longer the case, ie, SATA idle / standby stateFigurein

described in2the entire area of FTL FTL metadata metadata logging to the NAND flash

(ftl_flush function

reference),after being shut down properly booted without performing the format, FTLmetadata arealogging in

FTLload metadatathe user to be ready to handle the IO request (load_metadataas

numberreference).

2.3. How to verify FTL operations?

2.3.1. logic test FTLFTLlogically verify operation in order to perform a write operation, then basically, the same

areafor a read operation is performed by comparing the two data buffers, FTL operationthere is no

can check whetherbug.To implement this method for the following two can have:

1.Or by using a separate verification program, the host application (eg IOmeter) in

readafterwriteoperation is performed by inserting the code verification

2.FTL firmware using the test o.

Valid

Invalid

code. / Include / jasmine.h OPTION_FTL_TEST to 1 to the internalFTL.

code to test the After initialization, this option is set, Jasmine,

ftl_test SATA to bypass the function call can be verified by FTL code

thisfunction is performed by a continuous function, by default, after ftl_write,

ftl_read cognitive function calls compared to the same data perform the operation.

o If more varied in order to test for a variety of firmware codetest

to verify that thecase to implement. 2.3.2POR test

The PORFTL normal operation of the code in order to test whether OPTION_FTL_TEST simplyto

set1, and, to perform the firmware to boot the ftl_test.Power button off and onafter

By Kimagainexplicit code to perform the POR, ftl_test haenghage andthe luck

the wayyou can test ..

2.4. Setting up to buildJasmine ported firmware in order to build a FTL scheme. / Ftl_xxx in the form of a

generatedfolder,the corresponding FTL header files and source code files related should be addeddefault,

by the build folder (. / Build_rvds or . / build_gnu) file_list.via of

thecompilationa list of source files written in the firmware to be. If, ftl.cexistsother than the source

file_list.via file,add the corresponding source file to be compiled with the

party

alsoJasmine relevant header files (. / Include / jasmine.h) to modify the compilation options by

the. These settings allow the NAND flash chip Jasmine board mounted type, bank configuration, 2

plane mode, DRAM size, clock speed, and can determine the operation, a test mode is also FTL,

assert verification, UART debugging, SATA 2.0/1.0, such as SATA NCQ enabled / disabled can

dothis when you have finished setting the next build, see Chapter 3 to build the firmware andcreated

the firmware binary imageto be installed on board the Lab.

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Jasmine.Copyright 2011 VLDB All rights Lab.

Version 1.2

reserved.Copyright 2011 VLDB All rights 3.

Version 1.2

reserved.Chapter Compile, Build & InstallFirmwareFirmware This chapter describes the process of compilation and build and Jasmine in the process of installingthe firmware on the boardthe

looks at3.1.

Compile & Build FirmwareFirst, under the platform of the latest firmware from the path Jasmine OpenSSD Client PC tosource

download thefiles.

• http://www.openssdproject.org/wiki/Downloads

Jasmine OpenSSD platform supports two compilation environment the. RV ICE first isequipment and

how to use theRVDS GNU toolchain and the other one is to use the method.

3.1.1. Build firmware using toolchainRVDSRVDSARMorder to build the firmware using the Client PC in RVDS 3.0 or laterinstalled.

must be

NOTE: Note that if you have not bought the full version of RVDS ARM Ltd., Website

(www . arm.com) after registering, ARM RVDS 4.1 Professional with the evaluation versiondown.

can be Note that the Evaluation version can be used for 30 days,the expiration of the two

aftermust be licensed.

Firmware build in a command window to perform the following

command.> Cd./ Build_rvds> build.bat [tutorial | greedy build firmware as above procedure is completed, the binary image of the firmware in that folder

firmware.bin file is created.

NOTE: If the following error occurs during build, after discontinuation of the vaccine program will perform.

mt.exe: general error c101008d : Failed to write the updated manifest to the resource of file ...

3.1.2. Build firmware using GNU toolchain

also Jasmine OpenSSD platform is GNU compilation tools used to firmware build can be

the first under the CodeSourcery website the latest version of Sourcery G

+ +

Lite Edition download get

and, Client PC to install.

• http://www.codesourcery.com/sgpp/lite_edition.html Tutorial FTL default Makefile is to build the set. Soportingthe new FTL

the firmware toscheme Makefile to build the first line of the following modifications.

FTL = new_scheme ...

and the command window, perform the following

command.> Cd./ Build_gnu> build.bat

above procedure is completed, the firmware build of the firmware binary image in the folder,

the file is created firmware.bin.

3.1.3. Compile firmware installerinstalling the firmware program is performed by install.exe.to the install.exe

First, in ordergeneratefile,the following path in Visual C + + 2010 Express Free Edition Download

andinstall.

• http://www.microsoft.com/express/Downloads/ # 2010VisualCPP

since the Visual C + + 2005 solution file (. / installer / installer.sln) to build the

install.exe file is created in the path. On the other hand, so the installer the created

tousefirmware,build the path you want to FTL (eg Tutorial FTL you want to

ifinstall,./ Ftl_tutorial /) to move to.

NOTE: Jasmine board channel / way configuration, if you change

include,./ include / jasmine.h after changing the BANK_BMP, installer, be sure torebuild the

use the..

3.2. Install Firmwarebuild in Section 3.1 of the firmware binary image using the install.exeJasmine

to install theboard. The process of installing the firmware are:

1.Jasmine board 'Factory mode'to boot

boot ordero Factory mode as follows: Jasmine J2 jumperof the

settingboard,and connect the power and SATA cables and turn on the power Lab.

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switch.Copyright 2011 VLDB All rights reserved.

Version 1.2

o Factory mode when booting, Jasmine board to the host PC's Device Manager

Disk drive 'YATAPDONG BAREFOOTROM' is recognized as a

0.2.The installer (install.exe) running the firmware installed on board Jasmine

Figure 5) Jasmine Firmware Installer

o Each is described as follows:

1.initialize

Jasmine performs initializing the board

2.read scan list from flash block 0

Jasmine 번째 board mounted on the bank 0 block 0 of NAND flash chips installed in

thebad block list to load the

0.3.install FW

Jasminefirmware installed on the board

4.scan init bad blks

to scan the entire NAND flash memory to write the bad block list

5.erase flash all

Full NAND flash chipdeletes all blocks. In this case, block 0installed

iswith the firmware and delete the bad block list, so it should be noted benefits

0.6.save scan list to file

menu created with 2 or 4 working bad block scan listtheof files on your

stored informPC.Enter the name of the folder where you will receive a

7.read scan list from file

6menu file saved on your PC through a scan list to readbad block list to

thecreate0.8.

exit

to exit the Lab.

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installer.Copyright 2011 VLDB All rights reserved.

Version 1.2

o Meanwhile, Jasmine board NAND flash memory in the factory at the time of scan list is already

installed. Therefore, before installing the firmware back to the PC scan lista receive

must be preceded byoperation. When performed in the order 1263 as this menu.

O ten thousand and one block 0 is installed on scan list is damaged,thethe menu 2

the error in course ofis generated. Therefore, PC stored in the scan list loading the file

afterto install the firmware. This is in order to perform the menu 173.

O If the new NAND flash modules installed on the board when Jasmine, NAND

flash memory to scan the bad block scan list after you save the firmware

to be installed. According to the order in which the menu 1463

firmwareinstallation is successfully completed, as follows Jasmine Normal jumperJ2the board

mode,set toand

the SATA cable to the power switch to turn on the minus. This process is carried out inFTL

saidformat,the format is complete, the D4 position of the LED is turned on.after connecting the SATA cable to the

Jasmine boardSATA command from the host, you are ready to perform.

NOTE: Jasmine board when power is internally ftl_open function is called,

depending on the implementation, the operation may take a long time to carry out be. This causes the hostresponse timeout error occurs because it is possible, ftl_open is completethe

attime, that is after the D4 position of the LED is on the SATA cable to connect to.

Jasmine installation is successfully completed, the firmware on the board as shown in the figure below DeviceManager

Diskdrive 'OpenSSD Jasmine you can see that recognized, and nowcomplete

it is available as aFlash Lab.

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SSD.Copyright 2011 VLDB All rights Lab.

Version 1.2

reserved.Chapter Debugging TipsJasmine OpenSSD message output via UART interface platform and ICE equipment and RV Debugger

can be debugged using the realtime firmware. In this section, these two methodsJasmine

of operation FTLboardinstalled to verify the method is described.

4.1.Debugging with UARTIn this section, JasmineUART interface board through a terminal windowoutput to informationBow

using the debuggingabout the process ofexplained.

4.1.1. Debugging settingfirst, Jasmine board UART port (P1) and Client PC's serial port to RS232

connectthecable.Jasmine and UART interface board for use onboard switch

(SW2, 3,4) is set as No.

follows.• SW2: 1,2,3,4 (ON)

• SW3: No. 1,2,3,4 (OFF)

• SW4: No. 1,2,3,4 (OFF)

Jasmine board when you have finished setting the serial port of the terminal program is configured as follows.

• bits / second (Baud rate): 115200

• Data bits: 8

• Nonebits:

Parity:• Stop 1

• Flow control: Hardware (or Yes)

UART interface to get the message outputthe firmwareOPTION_UART_DEBUG.

to activateshould be . / Include / jasmine.hset to 1, the

determinedOPTION_UART_DEBUG.

4.1.2. Debugging by printing messageUART UART port message if the print function is enabled (. / Target_spw / uart.c the

uart_print) using a dump when the error occurred or that a particular memory area,debug

outputmessagesto the operation of the firmware in such a way Can you debug. Jasminethe

UART port has been initialized andboard,Normal mode is Jasmine board is booted

belowtheon the same message is output to the terminal Lab.

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window.Copyright 2011 VLDB All rights 4.1.3.

Version 1.2

reserved. Measure Response TimeJasmine FTL firmware using the Timer function also provides the relevant performance measurement.usingthisfunction

FTL read / write and to measure the overhead of garbage collection and the delay measuring

timethe response time or the FTL output UART port for debugging logical errors can be

related to the following code as a function Timer ( . / target_spw / misc.c the

ptimer_start, ptimer_stop,_uart_print) using ftl_write performed, the response time measured.

canbe

ptimer_start (); ftl_write (lba, num_sectors); ptimer_stop_and_uart_print ();The figure below shows the test function FTL (ftl.c the ftl_test) the above code intovia the UART

the outputresponse time (unit: us) Lab.

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show.Copyright 2011 VLDB All rights reserved.

Version 1.2

4.2. Debugging with RVDRealView ICE and RealView Debugger This section describes the equipment usedthe process of debugging the

to describefirmware.

NOTE: Jasmine host application is passed to the IO board while processing the command

explicitlystops operation of the firmware walk breakpoint , busy waiting occurs, the system is

operatinglikely to be stopped. Thus, by using a separate Client PC Client PCin

to perform debugging4.2.1.

Debuggingsetting,first, the exact linebyline debugging, compile the firmware be made to modify the configurationfile.

should RVDS compilation in the configuration file. / Build_rvds / armcc_opt.via open the below,

file,modify the two options, as shown and then to perform the firmware

build.O3/ /O1

modifiedOtime/ / delete

Subsequently, the Figure 1 After making the settings, like RVD, as shown belowthe setting of RVdebugger

withICEJasmine equipment and make sure that the board is properly connected,

allconnections to complete, the menu Target> Load Image to build the firmware image

loadthe. Once the image has loaded successfully, the firmware startup code as shown in the figure below

(. / Target_spw / init_rvds.s) has be Lab.

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shown.Copyright 2011 VLDB All rights reserved.

Version 1.2

Finally, as shown in the figure below. / Release_lock.inc add script, then run the

Jasmine board's JTAG port for debugging If you open the settings are ended.

4.2.2 Debugging tip # 1 "Use a breakpoint statement"Jasmine board is powered by the startup code. / Target_spw / initialize.c

init_jasmine of the function is invoked before. The function of various hardware components

and SRAM / DRAM ftl_open area and call the function to initialize the IO request, and thenuser

waits for theif

the user IO request after power before the call waiting function is a bug in the

duetofirmware,if an error occurs suppose. As shown in the figure below, for example,within ftl_open function

can not be referencedto write data to the memory area, let's say the bug is.

Void ftl_open

(void) * (UINT32 *)0xFFFFFFFE = 10; / / data abort occurs. .

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Copyright 2011 VLDB Lab. All rights reserved.

Version 1.2

above are the Jasmine board is powered on as soon as the code is performed as data

abort interrupt occurs and because they, since the RV to run the debugger and debugging,you try

even ifproblem, come to find the code can not be

located, soin order to solve these problems, an error occurs before the explicit positionfirmware

after debugging behavior must stop, which is dummy while as shown below

statement,there is a way to insert.

volatile UINT32 g_barrier0;(g_barrier0);();

void init_jasmine

......

g_barrier;(void)= while==

ftl_openftl_open

function dummy while the door before performingstopping the flow of the

Afterfirmware,RV g_barrier by running a debugger to change the values of one linebyline debuggingproceed.

can

4.2.3. Debugging tip # 2 "Use a H / W breakpoint"FTL code if there are logical errors in the metadata of the buffer memory orvalue of the wrong

change theproblem can occur. In this case, the debugger RV `hardware breakpoint 'to

be able to perform debugging using

certainmetadata value is '0', the change you want to stop the flow at the time the firmware,as shown below

the memory addressin the order of 'hardware write 'breakpoint Lab.

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registers.Copyright 2011 VLDB All rights reserved.

Version 1.2

Breakpoint debug resume after registering the address of the memory that the observed value is '0 'write

the line to stop the flow of a bug in the firmware can be found.

4.2.4 Debugging tip # 3 "Watch status registers"BSP has performed immediately prior to being written to the flash command is interrupted due to a malfunction

occurif, BSP_INTR register interrupt debugging information possible, by observingFTL

theFirst

RV debugger menu View> Memory to open the Memory window, BSP_INTR register,

memoryaddress the interrupt information can be observed in BSP. As shown below, the bank 0

FIRQ_DATA_CORRUPT (0x82) interrupt has occurred can be confirmed

also,BSP, check the command remains in the flash immediately prior to performing a flash the type of

command,andtarget bank, block, page numbers, and a buffer address can be found. Looking at the picture below

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Pages of read operations FC_NORMAL_READ_OUT (0x0A) that occurred during the interrupt

can be seen.

NOTE: When you observe the memory value must be careful that the little endian, BSP registers andflash

command macro and DRAM memory map Refer to the Technical Reference Manual.

Version 1.2

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