THE INVERTERS
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Transcript of THE INVERTERS
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
THE INVERTERS
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
DIGITAL GATES Fundamental Parameters
Functionality Reliability, Robustness Area Performance
» Speed (delay)» Power Consumption» Energy
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Noise in Digital Integrated Circuits
VDDv(t)
i(t)
(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
DC Operation: Voltage Transfer Characteristic
V(x)
V(y)
VOH
VOL
VM
VOHVOL
fV(y)=V(x)
Switching Threshold
Nominal Voltage Levels
V(y)V(x)
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Mapping between analog and digital signals
"1"
"0"
VOH
VIH
VIL
VOL
UndefinedRegion
V(x)
V(y)
VOH
VOL
VIH
VIL
Slope = -1
Slope = -1
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Definition of Noise Margins
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
Noise Margin High
Noise Margin Low
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
The Regenerative Property
(a) A chain of inverters.
v0, v2, ...
v1, v3, ... v1, v3, ...
v0, v2, ...
(b) Regenerative gate
f(v)
finv(v)
finv(v)
f(v)
(c) Non-regenerative gate
v0 v1 v2 v3 v4 v5 v6
...
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Fan-in and Fan-out
N
M
(a) Fan-out N
(b) Fan-in M
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The Ideal Gate
Vin
Vout
g=
Ri =
Ro = 0
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
VTC of Real Inverter
0.0 1.0 2.0 3.0 4.0 5.0Vin (V)
1.0
2.0
3.0
4.0
5.0
Vo
ut (V
)
VMNMH
NML
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Delay Definitions
tpHL
tpLH
t
t
Vin
Vout
50%
50%
tr
10%
90%
tf
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Ring Oscillator
v0 v1 v2 v3 v4 v5
v0 v1 v5
T = 2 tp N
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Power Dissipation
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS INVERTER
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
The CMOS Inverter: A First Glance
VDD
Vin Vout
CL
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverters
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
1.2 m=2
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Switch Model of CMOS Transistor
Ron
|VGS| < |VT||VGS| > |VT|
|VGS|
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverter: Steady State Response
VDD VDD
VoutVout
Vin = VDD Vin = 0
Ron
Ron
VOH = VDD
VOL= 0
VM = Ronp) f(Ronn,
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverter: Transient Response
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
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CMOS Properties
Full rail-to-rail swing Symmetrical VTC Propagation delay function of load
capacitance and resistance of transistors No static power dissipation Direct path current during switching
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Voltage TransferCharacteristic
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
PMOS Load Lines
VDSp
IDp
VGSp=-5
VGSp=-2VDSp
IDnVin=0
Vin=3
Vout
IDnVin=0
Vin=3
Vin = VDD-VGSpIDn = - IDp
Vout = VDD-VDSp
Vout
IDnVin = VDD-VGSpIDn = - IDp
Vout = VDD-VDSp
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverter Load Characteristics
In,pVin = 5
Vin = 4
Vin = 3
Vin = 0
Vin = 1
Vin = 2
NMOSPMOS
Vin = 0
Vin = 1
Vin = 2Vin = 3
Vin = 4
Vin = 4
Vin = 5
Vin = 2Vin = 3
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverter VTC
Vout
Vin1 2 3 4 5
12
34
5
NMOS linPMOS off
NMOS satPMOS sat
NMOS offPMOS lin
NMOS satPMOS lin
NMOS linPMOS sat
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Simulated VTC
0.0 1.0 2.0 3.0 4.0 5.0Vin (V)
0.0
2.0
4.0
Vo
ut (V
)
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Gate Switching Threshold
0.1 0.3 1.0 3.2 10.01.0
2.0
3.0
4.0
kp/kn
VM
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
MOS Transistor Small Signal Model
rogmvgsvgs
+
-
S
DG
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Determining VIH and VIL
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Propagation Delay
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverter: Transient Response
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverter Propagation Delay
VDD
Vout
Vin = VDD
CLIav
tpHL = CL Vswing/2
Iav
CL
kn VDD
~
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Computing the Capacitances
VDD VDD
VinVout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CL
SimplifiedModel
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
CMOS Inverters
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
1.2 m=2
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
The Miller Effect
Vin
M1
Cgd1Vout
V
V
Vin
M1
Vout V
V
2Cgd1
“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”
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Computing the Capacitances
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Impact of Rise Time on Delayt p
HL(n
sec
)
0.35
0.3
0.25
0.2
0.15
trise (nsec)10.80.60.40.20
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Delay as a function of VDD
0
4
8
12
16
20
24
28
2.00 4.001.00 5.003.00
Nor
mal
ized
Del
ay
VDD (V)
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Dynamic Power Dissipation
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Need to reduce CL, Vdd , and f to reduce power.
Vin Vout
CL
Vdd
Not a function of transistor sizes!
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Impact ofTechnology
Scaling
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Technology Evolution
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Technology Scaling (1)
Minimum Feature Size
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Technology Scaling (2)
Number of components per chip
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Propagation Delay Scaling
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Technology Scaling Models
• Full Scaling (Constant Electrical Field)
• Fixed Voltage Scaling
• General Scaling
ideal model — dimensions and voltage scaletogether by the same factor S
most common model until recently —only dimensions scale, voltages remain constant
most realistic for todays situation —voltages and dimensions scale with different factors
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Scaling Relationships for Long Channel
Devices
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Scaling of Short Channel
Devices
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BIPOLAR INVERTERS
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Resistor-Transistor Logic
Vin
Vout
Vcc
RB
RC
Q1
Vin
Vout
SaturationCutof f
Forward-active
VCE(sat)
VCC
VB E(on) V in(eos)
VTC of nonsaturating gate
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
VTC of RTL Inverter
0.0 1.0 2.0 3.0 4.0 5.0Vin
0.0
1.0
2.0
3.0
4.0
5.0V
ou
t
FO=5
FO=2
FO=1
FO=0
VOH is function of fan-out
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Transient Response of RTL Inverter
0.00e+00 5.00e-10 1.00e-09 1.50e-09 2.00e-09t
0.0
1.0
2.0
3.0
4.0
5.0V
ou
t
tp = 290 psec !!!!
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The ECL Gate at a GlanceVcc
RC
Q1
Vc c
RC
Q2 VrefVin
Vout2Vout1
IEE
VEE
Vx
Core of gate:The differential pairor “current switch”
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Single-ended versus Differential Logic
VinVin
Vout1 Vout2
Vout1
Vout2
Vout1Vout2 Vout2Vout1
DifferentialSingle-ended
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Complete ECL Gate
Vcc
RC
Q1
Vc c
RC
Q2 Vre fVin
IEE
VEE
Vx
Vc cVcc
VEE
RB
Vout2Vout1
Q4Q3
VC1 VC2
Emitter-followeroutput driver
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The Bias Network
Q5
R1
R2R3
D1
D2
Vref
VCC
VEE
Issues:•Temperature variations•Device variations
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Photomicrograph of early ECL Gate (1967)
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
ECL VTC
VCC – VBE (on)
VCC – VBE(on) – IEERC
Vin
Vout
Vout2
Vout1
V r ef
+/– n T
Q1 saturates
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
ECL VTC
Vswing = IEE RC
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Simulated VTC of ECL Gate
–1.5 –1.3 –1.1 –0.9 –0.7 –0.5Vin (V)
–1.30
–1.20
–1.10
–1.00
–0.90
–0.80
–0.70V
out (
V)
Vout1 Vout2
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ECL Gate with Single Fan-out
Vcc
RC
Q1Vin
IE E
VE E
Vx
Vc c
Q3
Vcc
RC
Q1
IEE
VEE
RB
VE E
Cd Cbe
Cc s
Cbc Cbc
CbeCd
CbeVout1
FAN-OUT
VC1
Cbc
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Simulated Collector Currents of Differential
Pair
0 0.1 0.2Time (nsec)
–1
0
1
Col
lect
or
curr
ent
(nor
mal
ized
)
10 mA 5 mA
1 mA
0.5 mA
IC1
IC2
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Propagation Delay of ECL Gate
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Simulated Transient Response of ECL Inverter
0 0.2 0.4 0.6 0.8 1.0
t (nsec)
–1.30
–1.10
–0.90
–0.70V
(V
olt)
Vout1V in
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Propagation Delay as a Function of Bias Current
0 5 10 15 200
50
100
150
200
IE E (mA)
t pLH
(pse
c)
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
ECL Power Dissipation
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Scaling Model for Bipolar Inverter
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Digital Integrated Circuits © Prentice Hall 1995InverterInverter
Bipolar Scaling