The Impact of Variability on the Reliability of Long on-chip Interconnect in the Presence of...

The Impact of Variability on the Reliability of Long on-chip Interconnect in the

Presence of Crosstalk

Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alex Yakovlev, Gordon Russell

Newcastle UniversityUK

Outline

Structure and fabrications of Modern Interconnect

Why are two nominally identical wires different ?

Impact of variability on Wire Delay and Crosstalk Glitches

What are the Failure Mechanism in Capacitance-Dominated links ?

Does Variability make things worse ? Conclusions

Interconnect Stack in Modern Technologies

Source : ITRS 2007

1. Start with the previous interlayer dielectric

How to Build Multilayer's Interconnect Structure

2. Add an ‘etch stop' layer


3. Add a new layer of intra-layer dielectric


4. Etch spots in the dielectric for wires


5. Deposit the barrier metal


6. Deposit the metal


7. Grind it flat


8. Add a dielectric cap/via etch stop


9. Add more inter-layer insulator


10. Add another etch stop


11. Cut holes in dielectric for the vias


12. Cut holes in each stop layer for the vias


13. Deposit via metal


Interconnect Stack in Modern Technologies

14. Repeat the process for more layers

Variability Sources Fabrication Process

• Lithography – exact size and shape depend on environment

• Etching – also depends on environment• Thickness of metal depends on CMP environment• Deposition and polishing steps depend on chip

location on the wafer• Alignment between layers can affect vias

Source (An Overview of On-chip Interconnect Variation Lou Scheffer , SLIP 2006 )

Environmental Factors power supply and temperature Other Factors an example of a statistical variation that results in deterministic

uncertainty : CMP etching as function of location on a wafer

Variability Impact on wire electric parameters Normalized wire capacitance

distribution (C)Normalized metal resistance across manufacturing lines (R)

Source: Statistical Analysis and Optimization in the Presence of Gate and Interconnect Delay Variations Chandu Visweswariah ,IBM,SLIP 2006

Motivations

In DSM regime, due to process scaling, the contribution of interconnect delay has become significant

Wire delay and coupling effects play a significant role in determining ultimate performance

not easy to predict which is the worst corner

This work …Identify Interconnect Parametric

Variations

Develop a model for (Dwire ,, GAmplitude)

Statistical Analysis to Compute BER

Identify the Impact of Variability

Compare Different Design Approaches

Wire Model

w s

Gnd

Ground

Gnd

CpCf

Cc Cc

C’f Cf CpCp C’fC’fCf

t

h

Metal 9

Metal 8

Variations

Parameter Nominal Value Variations

Dielectric height (h) 9.40E-07 m 20%

Wire resistivity (ρ) 2.18E-08 Ωm 20%

Wire thickness (t) 8.10E-07 m 20%

Wire Width (w) 5.60E-07 m 20%

Transistor length (Leff) 90 nm 10%

Power Supply (Vdd) 1.2 V 10%

Temperature (temp) 27 oC 12 – 43 oC

Delay Sensitivity to Variability Sources

Un-Buffered Line (L=10mm, K=1)

Uniformly Buffered Line (L=10mm,K=4)

Crosstalk Glitches Sensitivity to Variability Sources


The Impact of Switching Activity

Crosstalk Case Transitions Total Capacitance

1 ↑↑↑, ↓↓↓ Cg

2 ↑↑- ,↓↓-, -↑↑, -↓↓ Cg +Cc

3 -↑- , -↓-, ↓↑↑ , ↑↓↓ , ↑↑↓, ↓↓↑,

Cg +2Cc

4 ↓↑-, -↓↑, -↑↓, ↑↓- Cg +3Cc

5 ↓↑↓, ↑↓↑ Cg +4Cc

Delay Sensitivity to Variability Sources



Variations





Failure Mechanism in Capacitive Coupled Links

Timing Failure This undesired effects occurs when the timing of a stage becomes uncertain due to coupling from the switching activity of neighboring stages, which results in a change in the total capacitance of the wire, hence dynamic delay.

Functional Failure which is caused by static noise, induced on a quiet victim net due to switching of neighboring aggressors.

Vin

1 2 k

Rint/k

Cint/k

Rint/k

Cint/kVoutD Q

CCLK

Interconnect States State Transitions Failure Mechanism

D0 ↑↑↑ , ↓↓↓ Timing Failure

D1 0↑↑ , ↑↑0, 0↓↓ , ↓↓0,1↑↑ , ↑↑1, 1↓↓ , ↓↓1

Timing Failure

D2 ↓↑↑,↑↑↓,↓↓↑,↑↓↓,0↑0,0↓0,1↓1,1↑1,1↑0,1↓0,0↑1,0↑1

Timing Failure

D3 1↑↓,0↑↓,↓↑1,↓↑0,1↓↑,0↓↑,↑↓1,↑↓0 Timing Failure

D4 ↓↑↓,↑↓↑ Timing Failure

G0 000,001,010,011,100,101,110,111,↓00,00↓,↓01,10↓,

11↑,↑11,01↑,↑10,↓0↓,↑1↑

None

G1 ↑0↓, ↑1↓,↓0↑,↓1↑ Functional Failure

G2 ↑00,↑01,00↑,10↑,↓11,↓10,01↓,11↓ Functional Failure

G3 ↑0↑,↓1↓ Functional Failure

BER Analysis

PE =-0.5- Q

PE = (Dwire >Tclk - Tsetup)

Timing Failure:

μθ = μD + μTsetup – μTclk

σ2θ = σ2

D + σ2Tsetup +σ2

Tclk

BER Analysis

X

X

PE =-0.5- Q

PE = Pr (Amp > Vth)

μ χ = μAmp – μVth

σ 2χ = σ 2

Amp +σ2 Vth

Functional Failure:

BER Analysis

ii OP 9

1BER =

P: is the Error Rate in each state

O: is the probability of Occurrence of each state


Variations





Variability: Good or Bad ?

How to combat variability ?

Conclusions Novel bit error rate estimation method Mathematical expressions - quick tool

to compare different design approaches.

BER model developed for self-timed interconnect links

Future directions - quantifying the variability impact on other system metrics

The Impact of Variability on the Reliability of Long on-chip Interconnect in the Presence of...

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