The growth of InAs and GaSb layers and nanowires on Si (111)

Licentiate Thesis

Sepideh Gorji Ghalamestani

Division of Solid State Physics Department of Physics

Sweden 2012

Division of Solid State Physics Department of Physics Lund University Box 118 S-221 00 Lund Sweden Copyright © Sepideh Gorji Ghalamestani 2012 Printed in Sweden by Media-Tryck, Lund University Lund 2012

There is plenty of room at the bottom.

Richard Feynman (1959)

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Abstract III/V semiconducting materials demonstrate outstanding properties such as high mobility and direct band gap, compared to Si. On the other hand, the mature Si-based technologies offer several advantages such as large available wafer size and economical prices. In recent years, the integration of III/V materials with Si substrates in both layer and nanowire geometries has received considerable attention for various applications. In particular, the nanowire geometry enables combination of dissimilar materials with high quality and scalable dimensions.

This thesis investigates the integration of InAs and GaSb thin layers and nanowires with Si substrates by metalorganic vapor phase epitaxy. The epitaxial growth of InAs layers on the Si (111) substrates was studied through multiple nucleation approach and resulted in thin, yet high quality layers. In addition, Au-seeded InAs nanowires were grown on the InAs epitaxial layer on 2” Si substrates, demonstrating similar properties to those grown on commercial InAs substrates. Furthermore, GaSb thin layer growth was studied on the InAs epitaxial layer and the nucleation of GaSb nanowires on the aforementioned layer was further investigated.

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Nanoelectronics revolution*

Nowadays, the size of our electronic devices is shrinking considerably. Nanoelec-tronics has revolutionized the electronic world over the past decades. In fact, what we have seen so far is only the beginning. Next to come is the Nanowire transistor.

Thirty years ago, life style was significantly less dependent on the electronic devices such as cell phones and laptops. However, nowadays it is almost impossible for many of us to live without our cell phones and laptops. It is even hard to imagine not using them for one week. Basically, we like to have portable devices that we can carry with us all the time. Currently, researchers at Lund University are investigating the possibility of using nanowire transis-tors to scale devices further down.

The size and weight of the laptops and cell phones are two important features in the market. In fact, the smaller and lighter they are the more portable they will be. Have you ever wondered how the technology is pursuing our desire? To answer this question, first we should know what Nanotechnology and Nanoelectronics are.

Nanotechnology Nanotechnology is the science of understanding and controlling matters at nanometer (nm) dimensions between 1 to 100 nm where one nanometer (1 nm) is equal to a billionth of a meter. Consider that most viruses have a diameter in the range of 20-300 nm. Human eyes are unable to see objects in the nanometer scale size. However, you might be able to imagine that the diameter of a single gold atom is one third of 1 nm.

Matters behave differently at nano-meter size and they do not obey classical physics rule anymore. Therefore, one needs to introduce new physical concepts to explain their strange behavior. Quantum mechanics is a branch of physics that could provide a mathematical description to explain their strange behaviors at nanometer size.

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Nanotechnology is a broad subject and can be divided into many subsec-tions such as Nanobiology, Nanome-chanics, Nanophotonics and Nanoe-lectronics.

Nanoelectronics Nanoelectronics studies the physics of matter at nanometer size and attempts to design smaller electronic devices. Again, let’s go back to 30 years ago, the days when people did not have any portable computer in their lives. Adam Osborne, an ex-book publisher, is considered by most historians the first person who decided to produce a portable computer that could fit under an airplane seat. In 1981, he introduced the first portable computer called “Osborne portable computer”. Except its large size and poor memory, the Osborne weighted 10.9 kg while, nowadays you can buy an iPhone which weights 0.137 kg (~1% of Osborne). Now, the question arises: “would we see the same trend in the future?” In order to answer this question, it is worth to review the technology development over the last few decades.

Transistors One of the essential building blocks of our electronic devices is called tran-sistor. A transistor is basically made of a semiconductor material and it is

used to amplify and switch electronic signals. The active part of the transis-tor is called channel. In 1965 Gordon Moore, the co-founder of Intel corpo-ration, predicted that the number of transistors on a device roughly doubles every 18 months. This predication later changed to an empirical rule and a driving force for companies. Based on the so called Moore’s law, the number of the transistors on a device has increased from 1 transistor on a chip in 1959 to more than 17 billion transistors on a chip in 2010. The progress over the last years is achieved through reducing all the dimensions of a transistor and therefore packing more transistors on the same area. However, scaling is a challenging issue and various key parameters should be considered. Nanoelectronics research-ers continuously investigate down-scaling to follow Moore’s law. One promising candidate for the future transistor generation is the nanowire. Nanowires are made of semiconductor materials in a cylindrical geometry. Their diameter varies between 10 to 100 nm and they can be some micro-meters long. Nanowires are con-structed by mimicking nature’s way of self assembly. Basically, they are grown from vapor or liquid sources where atoms arrange themselves in an ordered fashion and construct the nanowire layer by layer. Moreover, one can control their growth direction and grow them vertically on the substrate. These nanowires are of

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particular interest for the device application and they can be utilized as internal connects. In the transistor geometry, a nanowire can behave as the channel. To complete the final transistor structure, many fabrication steps should be performed after the nanowire growth. Therefore, vertical nanowire transistor structure enables packing even more transistors on the same area and allows transistor scaling below 20 nm gate length. Currently, many groups at different places around the world including research-ers at Lund University are studying the possibilities of replacing current transistor technology with nanowire transistors. Their publications over the last years confirm their progress and success. Also, there are some other

approaches toward scaling which are not mentioned here.

Therefore, it is evident that scaling will continue in the future and we will observe even smaller electronic devices on the market. So, in thirty years from now, you might compare the size of your cell phone with the current cell phones and notice a huge change. In fact, there might be a nano-sized cell phone attached to your glasses or arm watch. You might also have an ex-tremely light and thin sheet which serves as your laptop. The future technology can completely alter our life style. So, live healthy to see those happy days.

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List of Papers This thesis is based on the following papers.

I.

High quality InAs and GaSb thin layers grown on Si (111)

S. Gorji Ghalamestani, M. Berg, K.A. Dick, L.E. Wernersson

J. Cryst. Growth 332 (2011) pp 12-16.

II. Uniform and position-controlled InAs nanowires on 2” Si substrates for transistor applications S. Gorji Ghalamestani, S. Johansson, B.M. Borg, E. Lind, K.A. Dick, L.E. Wernersson Nanotechnology 23 (2012) 015302

III. Highly controlled InAs nanowires on Si (111) wafers by MOVPE S. Gorji Ghalamestani, S. Johansson, B.M. Borg, K.A. Dick, L.E. Wernersson Phys. Status Solidi C 9, No. 2 (2012) 206–209

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Papers not included in this thesis

I.

Temperature and annealing effects on InAs nanowire MOSFETs

S. Johansson, S. Gorji Ghalamestani, M. Borg, E. Lind, L.E. Wernersson

Microelectro Eng 88 (2011) pp 1105–1108

II.

RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates S. Johansson, M. Egard, S. Gorji Ghalamestani, B.M. Borg, M. Berg, L.E. Wernersson, E. Lind IEEE Trans. Microw. Theory Tech. 59 (2011) pp 2733–2738 III.

High frequency vertical InAs nanowire MOSFETs integrated on Si substrates S. Johansson, S. Gorji Ghalamestani, M. Egard, B.M. Borg, M. Berg, L.E. Wernersson, E. Lind

Phys. Status Solidi C 9, No. 2 (2012) 350–353

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Acknowledgement

There are many people without whom I could not do my Phd. First of all, I would like to thank Lars-Erik Wernersson for giving me the opportunity to come to Lund and work on this exciting topic. During almost two years of my Phd, you always motivated me by your encouragement and found time for me even when you were away. I would like to thank Kimberly A. Dick for being a concerned and supportive supervisor. You are a talented scientist and it is such an honor to work with you. I have always enjoyed our discussions and I hope we continue the same trend in the future. I am deeply grateful to Knut Deppert and Jonas Johansson for being great supervisors. I appreciate all your advice, support and your kind efforts. Also, I would like to thank Erik Lind for teaching me many interesting things about the physics of devices.

I thank Lars Samuelsson, Anneli Löfgren, Heiner Linke and Anders Gustafsson who made FTF a very nice place to work. Also, I would like to thank the lovely ladies at FTF: Mona Hammar, Lena Timby, and Monica Pålsson for all their assistance.

There are many people who helped me a lot to start my experiments in the lab. I thank Mattias Borg for helping me with Aixtron and Peter Ramvall for his continuous support on the Aixtron. Also, I thank David Adolph, Ivan Maximov, Mariusz Graczyk, Bengt Bengtsson, Anders Kvennefors, Håkan Lapovski, and George Rydemalm for all the technical support.

I had the opportunity to collaborate with several incredible people: Jessica Bolinsson, Philippe Caroff, Sebastian Lehmann and Magnus Heurlin. I have enjoyed all our meetings and discussions and I look forward to starting new projects with you.

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I would like to thank my office mates: Sofia Johansson, Bahram Ganjipur, Henrik Nilsson, Marcus Larsson and Gvidas Astromskas and all my colleagues and friends at FTF and EIT: Maria Messing, Daniel Jacobsson, Karla Hillerich, Bengt Meuller, Jesper Wallentin, Sofia Fahlvik Svensson, Martin Berg, Kristian Storm, Karl-Magnus Persson, Anil Dey, Kristofer Jansson, Mikael Egard, Mats Ärlelid, Mercy Lard, Cassandra Niman, David Lindgren and Kilian Mergenthaler, I would like to thank my family, my “second family” and all my friends. Thank you all for your endless love and encouragement regardless of long distances. Finally, and most importantly, I would like to thank my supportive and patient fiancé Omid Madani who encouraged me to come to Lund and has always supported me during this time. I would not be able to carry out my study without you.

Sepideh Gorji Ghalamestani

Lund University

Jan 2012

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List of abbreviations

CBE Chemical Beam Epitaxy

MBE Molecular Beam Epitaxy

MOVPE Metalorganic Vapor Phase Epitaxy

MFC Mass Flow Controller

SEM Scanning Electron Microscopy

SPM Scanning Probe Microscopy

AFM Atomic Force Microscopy

XRD X-Ray Diffraction

HRTEM High Resolution Transmission Electron Microscopy

VLS Vapor Liquid Solid

VSS Vapor Solid Solid

FET Field Effect Transistor

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Contents

Popular science writing ........................................................................................ vii

List of papers ......................................................................................................... xi

Acknowledgement ............................................................................................... xiii

List of abbreviations

............................................................................................... x

v

1 Introduction ..................................................................................................... 3

1.1 Nanotechnology and Nanoscience ............................................................. 3

1.2 III/V semiconductor materials ................................................................... 4

1.3 Epitaxy ....................................................................................................... 5

1.3.1 Thermodynamics ................................................................................. 5

1.3.2 Kinetics ................................................................................................ 7

2 Experimental details ......................................................................................... 9

2.1 Metalorganic Vapor Phase Epitaxy ............................................................. 9

2.2 Atomic Force Microscopy ........................................................................ 10

2.3 X-Ray Diffraction .................................................................................... 12

2.4 Scanning Electron Microscopy ................................................................. 13

3 Growth results ................................................................................................ 15

3.1 Layer growth ............................................................................................ 15

3.1.1 GaSb layer growth on Si (111) .......................................................... 17

3.1.2 InAs layer growth on Si (111) ............................................................ 21

3.1.3 GaSb layer growth on InAs/Si (111) .................................................. 24

3.2 Nanowire growth ..................................................................................... 25

2

3.2.1 GaSb nanowires ................................................................................. 26

3.2.2 InAs nanowires .................................................................................. 27

4 Conclusion and outlook ................................................................................. 31

References ............................................................................................................. 33

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1 Introduction

1.1 Nanotechnology and Nanoscience

During the last decades nanotechnology and nanoscience have emerged as key fields which play fundamental roles in various domains such as electronic device applications. Nanotechnology and nanoscience study the properties of structures with nanometer-size dimension since reducing the number of atoms in a material significantly affects its properties [1

In general, nano-sized objects are fabricated via bottom-up or top-down approaches. The bottom-up approach studies the matter construction through synthesis, reaction and self assembly [

].

2]. On the other hand, the top-down approach miniaturize the structures by using sophisticated techniques such as lithography [3

Material could have nano-size in one, two or three dimensions, with respective thin layer, nanowire (nano-sized wires) and nanoparticle (nano-sized particles) geometries. In fact, reducing the material dimensions enables integration of various materials with dissimilar atomic structures (lattice mismatch). Thin layers and

]. In fact, reducing the size of the material changes its properties by introducing some interesting geometrical and physical effects. As an example, the size reduction increases the surface to volume ratio and hence a greater proportion of the surface comes in contact with the environment. As a result, more dangling bonds can form on the surface which can then influence the material’s stability and affect its chemical properties. Another significant effect comes from the different physical properties of the nano-sized materials (compared to the bulk materials) where different aspects of physics laws (quantum effects) should be considered.

Chapter1 Introduction

4

nanowires have demonstrated interesting and important properties and have been applied in wide range of applications. Particularly the small and scalable dimensions of nanowires offer superior properties for the future device scaling.

1.2 III/V semiconductor materials

Semiconducting III/V materials (compounds of group III and group V elements) demonstrate several outstanding properties which make them interesting candidates for various device applications. The term semiconductor refers to a group of materials with electrical conductivity in between metals and insulators. In general, electrons inside a material are allowed to occupy certain energy levels known as bands. The term valence band denotes the upper energy band filled by electrons where the maximum level is called Ev. The fermi level denotes the chemical potential of the electrons in the semiconductor material at 0K. The allowed energy band above Fermi level is called the conduction band and its minimum is defined by Ec. The separation between Ev and Ec

Si is the most dominant semiconductor material due to its abundance in nature and beneficial oxide form, it has been extensively used in various electronic applications. However, future electronics will require high-speed devices, which highlights the importance of non-Si materials. In general, III/V semiconductor materials present interesting properties, such as direct band gap, which are important for optical applications. Also, III/V materials have higher mobility compared to Si. In particular, InAs and GaSb are attractive candidates since InAs has a high electron mobility [

is defined as the band gap. As a result, materials are classified into three categories depending on their band gap known as metals, semiconductors and insulators. In general, semiconductor materials have a band gap smaller than 2-3 eV where applying an electric filed, light or thermal energy to a semiconducting material can excite the electron from the valence band to the conduction band.

4] and GaSb has a very high hole mobility [5]. Therefore, integration of these materials with the current Si technologies seems an interesting approach to design and fabricate higher speed devices.

1.2 III/V Semiconductor materials

5

This thesis studies the integration of InAs and GaSb materials with Si substrates in both thin layers and nanowire structures. In particular, the nanowires’ geometry makes them suitable structures to combine dissimilar materials with very high material quality.

1.3 Epitaxy

Epitaxy is a technique used for ordered deposition of a material on a monocrystalline substrate. Homoepitaxy is the term used when the epitaxial layer and the underlying substrate are of the same type; otherwise it is called heteroepitaxy. In fact, epitaxy is a common bottom-up technique used for the growth of high quality monocrystalline materials, required for the device applications.

In principle, the epitaxial growth process is controlled by two key factors, thermodynamics and kinetics. Thermodynamics determines the direction of a reaction, and kinetics determines the speed of the reaction.

1.3.1 Thermodynamics

Thermodynamics is the driving force for the epitaxial growth process which causes precursor molecules to react and form the epitaxial structures. Basically, thermodynamics deals with energy change of a system during the growth process. If we consider a simple system composed of only one component where R indicates the reactant and P indicates the product, equilibrium is reached when the chemical potential of the reactants (𝜇𝑅)

equals the chemical potential of the products (𝜇𝑃).

R ↔ P → µR = µP R

In a non-equilibrium condition, thermodynamics acts as a driving force for the reaction to proceed to lower the energy of the system. In general vapor phase epitaxy growth, the reactants have higher chemical potential and hence the reaction

(1.1)

Chapter1 Introduction

6

moves forward to produce some solid products and to lower the energy of the system [6

R → P ∆µ = µR − µP = RT ln PP0

R

]. Here the chemical potential difference is expressed in terms of temperature (T) and supersaturation ( P

P0). It should be mentioned that the partial

pressure ratio ( PP0

) is only one way of measuring supersaturation.

The above discussion is only a simple picture of a thermodynamic system. In case of binary or even ternary systems where there is more than one reactant involved, more parameters need to be considered.

(1.2)

As stated before, the reactants in the vapor phase have quite high chemical potential. This chemical potential first decreases at the boundary layer (ΔμD) and then at the growth interface (ΔμS) to form the products, as shown in figure 1.1. The boundary layer is a layer adjacent to the growth interface where the vapor transport occurs only by diffusion (laminar flow) [7

].

Figure 1.1 Schematic structure of the chemical potential with respect to the reaction coordinate where the solid line and dashed line illustrate kinetics-limited and diffusion-limited growth regimes, respectively.

1.3.1 Thermodynamics

7

Depending on the chemical potential drop, two different growth regimes are defined. If the chemical potential drop at the boundary layer is higher than at the interface (ΔμD > ΔμS

6

), the growth is diffusion-limited since the diffusion is the limiting factor (dashed line in figure 1.1). In diffusion-limited growth, the growth rate is typically not affected by the temperature change. As reported in the literature [ ], diffusion-limited growth mainly applies for layer growth.

On the other hand, if the chemical potential drop at the interface is larger than at the boundary layer (ΔμD < ΔμS

) the growth is kinetics-limited (solid line in figure 1.1). The nanowire growth is primarily performed in this regime where a temperature change significantly affects the chemical reaction rate.

1.3.2 Kinetics

All vapor phase epitaxial growth processes involve several chemical reactions to form the solid products, including reactions in the gas phase (homogeneous reactions) and on the surface (heterogeneous reactions). A simple picture of an epitaxial process is shown in figure 1.2.

Figure 1.2 A simple illustration of various reactions occurring during the epitaxial growth process including homogeneous and heterogeneous reactions.

As shown in figure 1.2, after the homogeneous reactions, some reactants diffuse toward the substrate and then several heterogeneous reactions happen. Also, after landing on the surface, several processes can occur: some reactants diffuse on the

Chapter1 Introduction

8

substrate toward preferential nucleation sites (steps) and some might desorb back to the gas phase.

In the kinetic limited growth regime where the reaction rate is dependent on the temperature, the reaction rate (r) can be expressed by an Arrhenius function. In equation 1.3, pre-exponential factor A and kB are constant, and Ea

r = A e−Ea

kBT� (1.3)

is the activation energy.

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2 Experimental details

2.1 Metalorganic Vapor Phase Epitaxy

Epitaxial growth of semiconductor materials is performed by several techniques such as chemical beam epitaxy (CBE), molecular beam epitaxy (MBE), and metalorganic vapor phase epitaxy (MOVPE). Among all the existing techniques, MOVPE provides a robust process and it is used for large scale applications [6].

In this thesis, all the growths were performed with a cold wall and low pressure (100mbar) MOVPE system (Aixtron 200/4). The schematic structure of MOVPE system is shown in Figure 2.1. The main part of the MOVPE system is where the growth takes place, called the reactor. During the growth, Hydrogen with the total flow of 13 l/min is used as a carrier gas to transfer metallorganics (mainly group III) and hydrides (group V) to the reaction chamber. As shown in the Figure 2.1, each material flow is controlled by so-called mass flow controller (MFC). Metallorganic group III materials are mainly liquid except Indium source trimethylindium (TMIn) which is solid. The metallorganic sources are kept in so called bubblers to maintain their temperature constant where their flows are then controlled by the Hydrogen flow through the bubbler. As shown in figure 2.1, one Hydrogen pipe enters the liquid and the second collects the precursors in the vapor phase. On the other hand, the group V precursors used are mainly in the hydride form, except the metallorganic Antimonide source trimethylantimony (TMSb). During a growth process, the reactants are transferred to the reactor which it is heated by infrared lamps located underneath.

Chapter 2 Experimental details

10

The MOVPE system used for this work has a horizontal reactor designed for three 2” wafers or one 4” wafer. It has a graphite susceptor on which the substrate is places, which can be heated up to 750 o

C. During and after epitaxial process, un-reacted and also waste materials are sent to the exhaust line and burned safely. Typically, the epitaxial growth processes are controlled by several accessible parameters such as temperature and reactants molar fractions.

Figure 2.1 Schematic structure of MOVPE system where Hydrogen is used as the carrier gas. Metallorganic sources are kept in the bubblers and their flow is controlled by the corresponding MFC. The epitaxial growth process occurs inside the reactor and then waste materials are transported to the exhaust pipe.

2.2 Atomic Force Microscopy

For this thesis, the surface morphology of the epitaxially grown InAs and GaSb layers were characterized by D3100 Nanoscope IIIa Atomic force microscopy (AFM). AFM is one of the scanning probe microscopy (SPM) techniques where a sharp tip scans across the surface. It has three primary modes which are contact, non-contact, and tapping mode (TM). TM applies less damage to the soft samples compared to contact mode AFM and also provides higher resolution data compared to non-contact AFM mode [8

]. All the measurements of this study are operated in the TM and hence we only focus on that.

2.2 Atomic Force Microscopy

11

The basic principle of the TM AFM is quite simple. As demonstrated in Figure 2.2, an oscillating cantilever with a fine sharp tip at its end (typically made of Si) taps across the sample surface. The cantilever is connected to a piezoelectric scanner and a laser beam is reflected off from the cantilever’s back which is monitored by a photodiode detector. During the scan time, constant oscillation amplitude is maintained via a feedback loop sent by a controller electrics unit. In this way, a 3D picture of the surface morphology is created by analyzing the collected data from many scan lines. In this study, AFM was used to determine the root mean square (RMS) value of surface roughness. The RMS value represents the average height deviation from the mean value.

AFM is a powerful tool which can resolve atomic step roughness on the surface. However, it is unable to resolve smaller features such as kinks and adatoms on the surface.

.

Figure 2.2 A schematic structure of AFM technique where a cantilever with a sharp tip connected to its end scans across the surface. The cantilever deflection is measured through the beam reflection by the photodiode detector. A controller electronics unit sends a feedback loop to maintain constant oscillation amplitude.

Chapter 2 Experimental details

12

2.3 X-Ray Diffraction

Another technique used to investigate the quality, composition and stain of the grown layers is X-ray diffraction (XRD). High resolution XRD characterization was performed with Bruker-AXS D8 system with a Cu κ-α X-ray source.

X-rays are electromagnetic waves and their wavelength is in Ångstrom size, smaller than the atomic distance. In a crystalline material, atoms are completely ordered and they can be considered as two dimensional planes sitting on top of each other like pages of a book (Figure 2.3a). In XRD measurements, an X-ray beam with certain angle (θ) hits the surface of the material. Then, a part of it is reflected by the individual planes of atoms like a mirror reflecting light. It is worth noting that we only treat elastic scattering and neglect inelastic scattering, meaning that the energy of the reflected beam is the same as the energy of the incident beam. Diffraction happens when the reflected beam from the individual planes interfere constructively. This criteria is satisfied only when the path difference (2d sinθ) is equal to an integer multiple of the wavelength, known as the Bragg condition (equation 2.1). Figure 2.3b schematically shows the Bragg condition where d is the atomic plane distance and θ is the angle of the incident beam.

2d sinθ = nλ (2.1)

Figure 2.3 (a) Schematic structure of 2D planes of atoms in a crystalline material positioned on top of each other with d atomic distance. (b) Schematic structure of Bragg condition where d is the atomic plane distance and θ is the angle of the incident beam.

2.3 X-Ray Diffraction

13

In an XRD set up (shown in figure 2.4), both the X-ray tube and the detector angles should be adjusted to satisfy the Bragg condition. However, the θ angle is often adjusted by tilting the sample holder.

Figure 2.4 Schematic structure of a XRD set up which demonstrates an X-ray tube hitting the sample at Bragg angle and the detector collecting reflected beam with the same angle.

2.4 Scanning Electron Microscopy

Scanning electron microscopy (SEM) is another powerful technique to characterize the surface of micro and nano-sized objects since people’s eyes are unable to resolve objects smaller than 0.1mm. SEM produces an image of the sample by scanning a high energy focused beam over the sample in a raster scan fashion. The electron beam is created either by thermionic filaments such as W and LaB6

Inelastic interaction of the focused beam with the sample material can produce several electrons and electromagnetic radiation. One type of signal produced by inelastically scattered electrons is called Secondary electrons (SEs). Those which are detected are produced from the topmost part of the surface (depth of ~5-50 nm)

or by a field emission gun. Afterwards, the beam is focused by passing through several condenser lenses to decrease the beam diameter. Also, the beam passes through the scan coils which control the scan procedure.

Chapter 2 Experimental details

14

and typically have energies less than 50 eV. Electrons can also scatter back elastically, and are then called backscattered electrons (BEs). Typically, they have much higher energy than SEs and they originate from deeper parts of the sample, which means they also have much poorer spatial resolution. SEs have high spatial resolution and are commonly detected and analyzed to obtain the surface topography of the sample. For this thesis, the surface morphology of the grown layers and nanowires were evaluated by FEI Nova NanoLab 600.

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3 Growth results

The work in this thesis focuses on the epitaxial growth of InAs and GaSb layers on the Si substrates and further discusses InAs and GaSb nanowire growth on the aforementioned substrates. Section 3.1 discusses III/V layer growth on the Si (111) substrates. Section 3.1.1, and 3.1.2 present the results of GaSb and InAs layer growth on Si (111), respectively. Section 3.1.3 further discusses the result of GaSb layer growth on the InAs epitaial layer.

Introduction to nanowire growth is discussed in section 3.2 and GaSb and InAs nanowire growth results are further discussed in section 3.2.1 and 3.2.2, respectively.

3.1 Layer growth

As stated before, the integration of high mobility III/V semiconductors such as InAs and GaSb with the Si substrates has significant potential for various electronic applications. However, epitaxial growth of InAs and GaSb on the Si substrates presents several main challenges such as lattice mismatch, thermal mismatch and formation of anti phase domains.

In crystalline materials, atoms are placed in a periodic fashion and the corresponding interatomic distance is called lattice constant (a). Epitaxial growth of lattice mismatched materials forces atoms of the epitaxial layer to follow the periodic order of the substrate material, which results in creation of strain (ε) in the epitaxial layer where the created strain is linearly related to the lattice mismatch value (equation 3.1).

Chapter 3 Growth results

16

ε = a0−aa0

, (3.1)

where a0

is the epitaxial layer lattice constant and a is substrate lattice constant. Depending on the lattice mismatch value, several layers can be grown epitaxially until the strain energy becomes excessively large. At this stage, the epitaxial layer tends to relax and release this energy. The strain energy can be released either by dislocation formation (for rather low lattice-mismatch systems, figure 3.1a) or by so called Stranski-Krastanov (SK) island formation (figure 3.1b). One type of dislocation often occurring during the epitaxial process is called misfit dislocation. In a misfit dislocation, the epitaxial layer minimizes the created strain through omission of some atomic planes, as shown by dashed lines in figure 3.1a.

Figure 3.1 The schematic structure of (a) misfit dislocation formation when the lattice mismatch is rather low. (b) SK island formation for high lattice mismatch.

Often, it is useful to think about the magnitude and the direction of lattice distortion, known as the Burgers vector. In the case of misfit dislocation, the Burgers vector is parallel to the growth plane (the growth interface), shown by red arrow in figure 3.1a. This type of dislocation is often preferred since it does not propagate along the growth direction and the strain is sufficiently released. However, there are other types of dislocation where the Burgers vector is angled with respect to the substrate and dislocations can propagate upward to the grown layer. These types of dislocations are not favorable since they could degrade the film quality and adversely affect electrical and optical properties of the grown epitaxial layer (epilayer). Another type of dislocation observed in this work is called a screw dislocation (figure 3.1c). Screw dislocations happen when the shear stress forces half

3.1 Layer growth

17

of a plane to slip across the other and distorts the atomic arrangement, and hence the Burgers vector is perpendicular to the growth interface (shown by red arrow in figure 3.1c).

As mentioned before, the thermal mismatch between the substrate and epilayer could be another source of dislocation formation. Thermal mismatch originates from different thermal expansion coefficient of substrate and epilayer. In case of severe thermal expansion coefficient mismatch, thermal cracks can also happen [9]. The last main challenge originates from the growth of a polar material on the non-polar substrate. If we consider InAs layer growth on the Si substrates, there are two precursors (Indium and Arsenic) binding to the Si atoms on the substrate. The presence of atomic steps on the Si substrate could therefore create two different types of domain, group III-terminated and group V-terminated domains, known as anti phase domains (APD) [9,10

].

3.1.1 GaSb layer growth on Si (111)

Antimonide-based materials have attracted significant attention due to their beneficial properties, such as narrow band gaps required for optical laser applications [11,12,13]. In particular, GaSb has considerably high hole mobility (850cm2 5/Vs) suitable for high speed devices [ ]. On the other hand, Si substrates offer key advantages such as low price, robustness and large available sizes. Therefore, the growth of GaSb layers on Si (111) substrates seems interesting for a variety of applications. Moreover, it could serve as a substrate for the growth of vertical GaSb nanowires. We have studied epitaxial growth of GaSb thin layers on Si (111) substrates.

Before the growth, samples were cleaned by standard RCA cleaning [14

9

] which removes surface contaminations and also protects the surface by oxide formation. Afterward, the oxide layer was etched by HF treatment to form H-terminated surface and then the samples were directly transformed to the growth reactor. The growth of GaSb epitaxial layers on Si substrates was studied through a two-step growth approach due to the large lattice mismatch between GaSb and Si (~12%). In the two-step growth approach, the growth starts at a low temperature (nucleation layer) and subsequently continues at a higher temperature (second layer). This method has been applied in various material systems with rather large lattice mismatch such as GaAs layer growth on Si substrate [ ,15].

Chapter 3 Growth results

18

In this work, the nucleation layer was grown at relatively low temperature and high V/III ratio to limit surface diffusion of the reactants and form a high density of Stranski–Krastanov (SK) islands. Then, the surface was annealed shortly at higher temperature to enhance Ostwald ripening and improve surface coverage. Ostwald ripening is a consequence of the size dependence of the vapor pressure, where smaller islands have higher vapor pressure than larger ones. This gives rise to a concentration gradient in the vapor phase so that material is transferred from smaller to larger islands. Thus, larger islands will grow and smaller islands will shrink and finally disappear [16

9]. Afterwards, the second layer was grown at high

temperature and low V/III ratio to favor adatom mobility [ ]. Triethylgallium (TEGa) and and trimethylantimony (TMSb) were used as the precursors.

Several processes were investigated during the GaSb layer growth including formation of Sb-terminated surface, nucleation, annealing and second layer growth. The first parameter to study was replacing H-terminated surface by Sb-terminated surface to initiate the growth. For that, we studied a series of samples with the same nucleation growth parameters and varied the initial annealing temperature and Sb flow time from 500-600oC and 10 sec-1 min, respectively. Then, we characterized the surface morphology of those samples by both AFM and SEM techniques. The results showed that 10 sec Sb flow at 600oC could provide the most surface coverage and lowest RMS value of roughness (~8.25 nm). AFM and SEM micrographs of this sample are shown in figure 3.2a and b, respectively. Probably, this morphology improvement by reducing Sb flow time is related to the low equilibrium vapor pressure of Antimony which causes the excess material landing on the surface to remain there [17,18]. The initial Sb termination is very important in obtaining high quality GaSb layers [19]. However, the low equilibrium vapor pressure of Antimony makes it challenging to obtain such a layer. Therefore, several groups have considered using a thin buffer layer of AlSb to initiate the growth [20,21,22,23

The nucleation layer was grown with TEGa and TMSb and respective molar fractions of 1.1x10

].

-4 and 4.01x10-4 (V/III~3.6). Further AFM studies on the nucleation growth temperature and time indicated that 10 min growth at 450oC provides highest surface coverage and smoothest sample. Figure 3.2a and b show the SEM and AFM images of the sample with the mentioned nucleation growth parameters. Also due to the large lattice mismatch between GaSb and Si substrates, there should be some stacking faults presents at the interface [24].

3.1.1 GaSb layer growth on Si (111)

19

The effect of annealing on the samples was also investigated, by changing the annealing temperature and time from 550-600oC and 2-5 min, respectively. AFM study of the annealing conditions showed an improvement in surface morphology (at those areas without holes) by annealing at 600o

C for 5 min, shown in figure 3.2d. However, according to the SEM images (figure 3.2c), the size of the holes on the surface increased as well, probably due to the longer diffusion length of reactant on surface.

Figure 3.2 (a) Top surface SEM image of the GaSb nucleation layer. (b) 10x10μm2 AFM image of GaSb nucleation layer growth. (c) Top SEM image of the same sample after annealing at 600oC for 5 min, indicating larger holes on the surface. (d) 5x5μm2 AFM image of the sample, showing smoother surface.

Chapter 3 Growth results

20

Additional investigation of the effect of V/III ratio on the second layer growth (at 600oC) revealed that lowering the V/III ratio considerably improves the surface roughness. It should be mentioned that only the TMSb molar fraction was decreased, from 2.17x10-4 (V/III~2) to 1.08x10-4 (V/III~1) and that the second layer growth was performed at 600o

AFM and SEM images of the sample with TMSb molar fraction of 2.17x10

C for 10 min.

-4 are shown in figure 3.3a and b where the RMS value of roughness was ~40 nm. However, the sample with lower TMSb molar fraction (1.08x10-4

17

) looked almost mirror like (figure 3.3d). As shown in figure 3.3c, the RMS value of roughness was ~15nm with a few nm roughness in those areas without holes. Indeed, the considerable effect of V/III ratio on the surface morphology observed is in agreement with the other reports [ ,18,25

].

Figure 3.3 (a) 2.5x5μm2 AFM image of GaSb surface after the second layer growth (V/III~2), indicating very rough surface. (b) Top SEM image of the same sample. (c) 2.5x5μm2

AFM image of GaSb layer with lower TMSb flow (V/III~1), showing quite smooth surface. (d) Top SEM image of lower TMSb flow sample showing some holes remained on the surface.

3.1.2 InAs layer growth on Si (111)

21

3.1.2 InAs layer growth on Si (111)

InAs is another promising material for various device applications due to its high electron mobility and narrow band gap [26]. There are several successful reports about the growth of InAs layers on the GaAs substrates [27,28,29,30,31

26

]. However, there are only a few reports about the growth of InAs on Si substrates [ ,32

The growth of InAs on the Si substrates was also performed with a two-step growth approach, due to the large lattice mismatch between InAs and Si (11.6%). Trimethylindium (TMIn) and arsine (AsH3) were used as precursors. The nucleation layer was grown at 350

].

oC for 10 min. Then, the samples were annealed at 600oC for 6 min to enhance Ostwald ripening of islands and improve surface coverage. Afterwards, the so-called second layer growth was performed at the same temperature (600o

C) for 45 min. Further growth details are completely described in paper I.

Figure 3.4 Top view SEM images of InAs epitaxial layer with (a) one (b) two (c) three (d) four nucleation layers. (e) The hole density on the surface decreases significantly by adding more number of nucleation layers.

As previously shown [33,34], the growth of InAs layers on Si (111) with one

nucleation layer results in the formation of a high density of holes on the surface. However, the results of our study showed that adding more nucleation layers considerably decreases the density of the holes on the surface (shown in figure 3.4e). Figure 3.4a-d show top surface SEM images of samples with one to four

Chapter 3 Growth results

22

nucleation layers, respectively. It should be mentioned that on top of the nucleation layers a ~200 nm thick epitaxial layer (second layer) was grown.

AFM study on the multiple nucleated samples revealed that surface root mean square roughness (RMS) of a sample with one nucleation layer in a flat region (areas without holes) is 1.5 nm. This value decreases to 0.7 nm for the sample with 2 nucleation layers and to 0.4 for more than three nucleation layers. Figure 3.5a shows an AFM image of InAs epitaxial layer with five nucleation layers and figure 3.5b shows its derivative image. As suggested by the AFM results, InAs grows as triangular shaped nuclei in a step-flow like fashion where the step heights correspond to the InAs lattice constant.

Figure 3.5 5x5μm2

(a) AFM image (b) derivative AFM image of InAs epitaxial layer growth with five nucleation layers.

XRD characterization of the samples with one to six nucleation layers indicated film quality improvement by incorporating additional nucleation layers due to the clear presence of Pendellösung fringes on both sides of the InAs peak. 2θ/ω-scans spectra of samples with one to four nucleation layers are shown in figure 3.6 where the inset shows FWHM values. Also, the decrease in FWHM value from 70 to 53 arcsec is another indication of the quality improvement. Further details can be found in paper I.

3.1.2 InAs layer growth on Si (111)

23

Figure 3.6 High resolution 2θ/ω scans of samples with one to four number of nucleation layers, respectively where from 2 nucleation layers, the signal is shifted upward for clarity. The inset shows FWHM values taken from the rocking curve for one to six nucleation layers.

The abovementioned structural characterization data confirmed the high quality of the InAs epitaxial layer by adding four nucleation layers. Also, it was observed that adding more than four nucleation layers did not improve film quality further. After successful growth on the small size samples, InAs epitaxial layers (with four nucleation layers) were grown on full 2” Si wafer. Further investigation showed that this epitaxial layer could successfully serve as the substrate for nanowire growth. Section 3.2.2 studies InAs nanowire growth on the InAs epitaxial layer over 2” wafer size (paper II) where the growth results confirms homogeneity across the entire 2” wafer.

Chapter 3 Growth results

24

3.1.3 GaSb layer growth on InAs/Si (111)

Type II band alignment of the InAs/GaSb heterostructure provides an interesting system for device application purposes [35,36]. InAs and GaSb are almost lattice matched which makes it possible to grow GaSb on top of InAs in a one step growth approach (unlike the two-step growth approaches used on mismatched substrates). As reported by other groups, different switching sequences could construct GaAs-type or InSb-type interface [37,38

In this study, we have constructed InSb-type interfaces (figure 3.7a) with simultaneous switching between In and Sb and 3 sec pause for Ga and As. As discussed in section 3.1.1, V/III ratio has a significant effect on the surface morphology of the GaSb layer on Si. Indeed, the same behavior was observed for the growth of GaSb layer on the InAs under various TMSb molar fractions [

].

39]. Detailed growth parameters are further discussed in paper I. Figure 3.7b and c show AFM images of the GaSb surface morphology grown with V/III of 2 and 1, respectively. AFM results illustrate several clockwise and anti-clockwise spiral mounds on the GaSb surface [40,41

]. We correlate them to screw dislocations originating from the step heights on the InAs surface. It can be seen that reducing TMSb molar fraction has reduced the size and height of spiral mounds on the surface and hence improved the surface morphology. Also, the rather low density of the spiral mounds further demonstrates the high quality of the InAs epitaxial layer [41].

Figure 3.7 (a) schematic structure of GaSb layer grown on the InAs epitaxial layer on Si (111) substrates. 5x5μm2

AFM images of GaSb surface grown with (b) V/III~2 and (c) V/III~1 showing morphology improvement.

3.2 Nanowire growth

25

3.2 Nanowire growth

Nanowires, as the name signifies, are classified as structures with nano-size in two dimensions and micro-size in the third dimension. So far the capabilities of nanowires have been explored in various applications such as solar cells [42], diodes [43], optoelectronic devices [44,45] and transistors [46,47

It should be noted that all the nanowires discussed in this thesis are grown via Au catalysts. Au nanoparticles are deposited with two different techniques. In the first approach, Au aerosol nanoparticles with certain size and diameter are deposited randomly on the surface [

]. Nanowires can be fabricated with two different approaches: top-down and bottom-up. In this thesis, we only focus on the bottom-up approach where nanowires are epitaxially grown from the corresponding precursors.

48]. In the second approach, Au nanoparticles are lithographically patterned on the surface. While the first approach is fast and cheap, the second approach offers a key advantage in “positioning” which is essential for the device fabrication purpose. Figure 3.8a shows a schematic structure of an Au nanoparticle on the substrate. The state of Au nanoparticles during the nanowire growth is the matter of debate. The first model describing the growth of Au seeded Si whisker was suggested by Wagner and Ellis [49]. They proposed the vapor liquid solid (VLS) growth mechanism to explain the growth of the Si whiskers. In this model, during the annealing/de-oxidation step, the Au nanparticles form some kind of liquid alloy (figure 3.8b) which acts as the preferential nucleation site for the incoming precursors until they become supersaturated. At this point, the supersaturated Au alloys start to precipitate out at the alloy-substrate interface which results in the nanowire growth, shown in figure 3.8c. Hence, the diameter of nanowires is defined by the Au nanoparticle size. As long as the vapor precursors are supplied, this trend continues and nanowires grow longer. VLS is the most common growth mechanism and it is still applicable to variety of systems [50]. However, the growth of GaAs nanowires by chemical beam epitaxy (CBE) is explained by another similar mechanism known as vapor solid solid (VSS) growth mode [51

In this thesis, we have studied the growth of GaSb and InAs nanowires on the obtained GaSb and InAs epitaxial layers, respectively.

], where the Au nanoparticles are solid during growth.

Chapter 3 Growth results

26

Figure 3.8 The schematic structure of (a) Au nanoparticle on a substrate. (b) Alloy formation during annealing step, acting as the preferential nucleation site for the supplying precursors. (c) Nanowire growth by precipitation of supersaturated alloy particle at the alloy-substrate interface. If the supersaturation is maintained, the nanowire will continue to grow by precipitation at the alloy-nanowire interface.

3.2.1 GaSb nanowires

Recently, GaSb nanowires have attracted considerable attention due to their high

hole mobility and scalable dimensions [52,53]. We have studied the growth of GaSb nanowires by Au aerosol nanoparticles on the GaSb/InAs/Si (111) substrates described in section 3.1.3 (figure 3.9a). In particular, the effects of temperature and material flow on the nanowire nucleation were investigated. The temperature study in the range of 400-530oC showed no nanowire growth for temperature above 470oC, and the optimum growth temperature was 420o

C.

Figure 3.9 (a) Schematic structure of GaSb nanowires grown on the GaSb/InAs/Si (111) substrates. (b) 30o tilted SEM image of nucleated GaSb nanwires at 420oC.

3.2.1 GaSb nanowires

27

Also, increasing the precursors molar fractions while keeping the same V/III (3.2) improved the yield of nucleated nanowires. However, higher molar fraction also favored the radial growth of nanowires. Figure 3.9b shows a SEM micrograph of the nucleated GaSb nanowires at 420 oC for 30 min with respective TMGa and TMSb molar fractions of 2.13x10-5 and 6.84x10-5, indicating very low growth rate and high radial growth. It is worth mentioning that there are several challenges for the growth of GaSb nanowires on the GaSb epitaxial layer. One main challenge is the presence of native oxide on the GaSb surface which might need special chemical treatment right before loading the sample inside the reactor (not performed in this study) [54,55

17]. Another challenge is the low melting point of the GaSb which

limits the initial annealing/de-oxidation step [ ]. The results presented here were achieved without any annealing step. Also, the formation of Au-Sb alloy is different from typical hydride group V precursors which could complicate the growth behavior.

3.2.2 InAs nanowires

During last years, the growth of InAs nanowires has been the subject of several studies [56,57]. The recent advanced studies on the InAs nanowire growth have gained deep knowledge into stacking faults formation and crystal structure tuning [58,59,60,61

47

]. Nevertheless, there has always been an interest to grow high mobility InAs nanowires on Si substrates for various device applications such as field effect transistors (FET) and Photovoltaics [ ,62,63,64]. It should be mentioned that several research groups have investigated the direct growth of InAs nanowires on the Si (111) substrates by patterning an oxide mask with MOVPE [65,66] and MBE [67,68]. However, in their approach the control over diameter and yield for large surface area is confined by the mask patterning. Additionally, from a device viewpoint the indirect growth of InAs on Si is preferable due to the Si-InAs conduction band discontinuity [69,70

The InAs epitaxial layer (described in section 3.1.2) was used as the substrate for InAs nanowire growth. To investigate the quality of the InAs epitaxial layer over large surface area, the growth of InAs nanowire across 2” wafer size has been investigated (figure 3.10a). In order to grow nanowires, five 0.3x0.8 mm

]. Also, in our approach the InAs epitaxial layer has been used as the contact in the FET device application (discussed in paper II).

2 size

Chapter 3 Growth results

28

patterns were lithographically defined with various diameters and pitches (figure 3.10b). Figure 3.10c shows the schematic structure of InAs nanowires grown on the InAs/Si (111). Further growth details are completely explained in paper II.

Figure 3.10 (a) The mirror-like of the InAs epitaxial layer on the 2” Si wafer size. Schematic structure of (b) Five mm-sized lithographical patterns across a 2” wafer (c) InAs nanowires epitaxially grown on the InAs/Si (111) substrates.

The overview SEM image of one pattern with various diameters and pitches is shown in figure 3.11a. Figure 3.11b displays an image of nanowires with 40 nm diameter and 500 nm pitch. As shown in figure 3.11c, high resolution transmission electron microscopic (HRTEM) characterization of the Sn-doped nanowires showed mainly wurtzite crystal structure (figure 3.11c) with some stacking faults, expected for Sn-doped nanowires [71

]. The inset of figure 3.11c shows fast Fourier transform of center of the image.

3.2.2 InAs nanowires

29

Figure 3.11 SEM images of grown nanowires with (a) various diameters and pitches (b) 40 nm diameter and 500 nm pitch. (c) TEM image demonstrating wurtzite crystal structure, the inset shows the fast Fourier transform from a 40 nm square area in the middle of the image, typical for a hexagonal crystal phase.

Moreover, we have performed some statistical analysis on the grown nanowires by analyzing SEM images taken from entire 2” wafer size with Nanodim software [72

56

]. This software enables us to get good statistics on the nanowires diameters and lengths. The results showed 6 nm diameter shifts around the nominal diameter, similar to InAs nanowires grown on InAs substrates. The length variation for various diameters is shown in figure 3.12, representing an inverse relation between length and diameter [ ]. Additionally, the results confirmed 100% yield of nanowire growth across 2” wafer size.

All the above mentioned results confirm the high quality of the InAs epitaxial layer and reveal no difference compared to growth on commercial InAs substrates. Indeed, InAs nanowires on the InAs epitaxial layer could be applied in various device applications. In paper II, we demonstrate one possible application in the FET structure.

Chapter 3 Growth results

30

Figure 3.12 The distribution of average nanowire length for the corresponding average diameters measured by nanodim software for entire 2” wafer size.

31

4 Conclusion and outlook

This work focused on the integration of two interesting III/V materials with Si substrates. The growth behavior of thin layers (<500nm) of InAs and GaSb on the Si (111) substrates was investigated and the growth of InAs and GaSb nanowires on the respective epilayers were further studied. In particular, the InAs nanowires on the thin InAs epitaxial layer have high potential for various applications such as n-FETs.

In the InAs epitaxial layer, further studies on controlling the doping level (not discussed in this work) and reducing the layer thickness while maintaining its high quality could improve this structure even more. The growth of GaSb nanowires on the grown GaSb epitaxial layer is another interesting structure which could be used for p-FET application. In this respect, further investigations on improving the GaSb nanowire growth yield are desired. Possible approaches could be removing the native oxide from the surface of GaSb epilayer prior to the nanowire growth and additional fine-tuning of the nanowire growth parameters.

During the work of this thesis, I became more interested to explore the fundamental aspects of nanowire growth, such as incorporation of the additional precursors which could be studied via ternary systems. Also, the growth behavior of both axial and radial nanowire heterostructure geometries is another interesting system which could provide some insight into processes occurring during the growth of mismatched materials, such as dislocation formation.

Moreover, further studies will be devoted to explore the growth behavior of interesting and challenging Sb-based nanowires which are promising elements for various applications. In particular, ternary Sb-based nanowires are of great interest.

32

33

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