Intel® Itanium® Architecture Software Developer’s ManualVolume 2: System Architecture

Revision 2.2

January 2006

Document Number: 245318-005

ii Volume 2: Intel® Itanium® Architecture Software Developer’s Manual

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ContentsPart I: System Architecture Guide

1 About this Manual .................................................................................................................. 2:11.1 Overview of Volume 1: Application Architecture.......................................................... 2:1

1.1.1 Part 1: Application Architecture Guide ........................................................... 2:11.1.2 Part 2: Optimization Guide for the Intel® Itanium® Architecture ..................... 2:2

1.2 Overview of Volume 2: System Architecture ............................................................... 2:21.2.1 Part 1: System Architecture Guide ................................................................. 2:21.2.2 Part 2: System Programmer’s Guide.............................................................. 2:31.2.3 Appendices..................................................................................................... 2:4

1.3 Overview of Volume 3: Instruction Set Reference....................................................... 2:41.3.1 Part 1: Intel® Itanium® Instruction Set Descriptions ....................................... 2:41.3.2 Part 2: IA-32 Instruction Set Descriptions....................................................... 2:4

1.4 Terminology................................................................................................................. 2:51.5 Related Documents..................................................................................................... 2:51.6 Revision History .......................................................................................................... 2:6

2 Intel® Itanium® System Environment ................................................................................. 2:112.1 Processor Boot Sequence......................................................................................... 2:112.2 Intel® Itanium® System Environment Overview ........................................................ 2:12

3 System State and Programming Model.............................................................................. 2:153.1 Privilege Levels ......................................................................................................... 2:153.2 Serialization............................................................................................................... 2:15

3.2.1 Instruction Serialization ................................................................................ 2:163.2.2 Data Serialization ......................................................................................... 2:163.2.3 Definition of In-flight Resources ................................................................... 2:17

3.3 System State ............................................................................................................. 2:173.3.1 System State Overview ................................................................................ 2:183.3.2 Processor Status Register (PSR)................................................................. 2:203.3.3 Control Registers.......................................................................................... 2:263.3.4 Global Control Registers .............................................................................. 2:283.3.5 Interruption Control Registers ...................................................................... 2:313.3.6 External Interrupt Control Registers ............................................................. 2:373.3.7 Banked General Registers ........................................................................... 2:37

3.4 Processor Virtualization............................................................................................. 2:38

4 Addressing and Protection ................................................................................................. 2:414.1 Virtual Addressing ..................................................................................................... 2:41

4.1.1 Translation Lookaside Buffer (TLB).............................................................. 2:434.1.2 Region Registers (RR) ................................................................................. 2:534.1.3 Protection Keys ............................................................................................ 2:544.1.4 Translation Instructions ................................................................................ 2:554.1.5 Virtual Hash Page Table (VHPT).................................................................. 2:56

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4.1.6 VHPT Hashing...............................................................................................2:594.1.7 VHPT Environment........................................................................................2:614.1.8 Translation Searching ...................................................................................2:634.1.9 32-bit Virtual Addressing ...............................................................................2:654.1.10 Virtual Aliasing...............................................................................................2:66

4.2 Physical Addressing ...................................................................................................2:664.3 Unimplemented Address Bits .....................................................................................2:67

4.3.1 Unimplemented Physical Address Bits..........................................................2:674.3.2 Unimplemented Virtual Address Bits.............................................................2:684.3.3 Instruction Behavior with Unimplemented Addresses ...................................2:68

4.4 Memory Attributes ......................................................................................................2:694.4.1 Virtual Addressing Memory Attributes ...........................................................2:694.4.2 Physical Addressing Memory Attributes........................................................2:704.4.3 Cacheability and Coherency Attribute ...........................................................2:714.4.4 Cache Write Policy Attribute..........................................................................2:724.4.5 Coalescing Attribute ......................................................................................2:724.4.6 Speculation Attributes ...................................................................................2:734.4.7 Sequentiality Attribute and Ordering .............................................................2:754.4.8 Not a Thing Attribute (NaTPage)...................................................................2:794.4.9 Effects of Memory Attributes on Memory Reference Instructions .................2:794.4.10 Effects of Memory Attributes on Advanced/Check Loads .............................2:804.4.11 Memory Attribute Transition ..........................................................................2:81

4.5 Memory Datum Alignment and Atomicity ...................................................................2:86

5 Interruptions ......................................................................................................................... 2:895.1 Interruption Definitions ...............................................................................................2:895.2 Interruption Programming Model................................................................................2:915.3 Interruption Handling during Instruction Execution.....................................................2:925.4 PAL-based Interruption Handling ...............................................................................2:955.5 IVA-based Interruption Handling ................................................................................2:95

5.5.1 Efficient Interruption Handling .......................................................................2:965.5.2 Non-access Instructions and Interruptions ....................................................2:975.5.3 Single Stepping .............................................................................................2:985.5.4 Single Instruction Fault Suppression.............................................................2:985.5.5 Deferral of Speculative Load Faults ..............................................................2:98

5.6 Interruption Priorities ................................................................................................2:1025.6.1 IA-32 Interruption Priorities and Classes.....................................................2:105

5.7 IVA-based Interruption Vectors ................................................................................2:1065.8 Interrupts ..................................................................................................................2:108

5.8.1 Interrupt Vectors and Priorities....................................................................2:1125.8.2 Interrupt Enabling and Masking...................................................................2:1135.8.3 External Interrupt Control Registers ............................................................2:1155.8.4 Processor Interrupt Block ............................................................................2:1215.8.5 Edge- and Level-sensitive Interrupts...........................................................2:125

6 Register Stack Engine ....................................................................................................... 2:1276.1 RSE and Backing Store Overview............................................................................2:1276.2 RSE Internal State....................................................................................................2:129

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6.3 Register Stack Partitions ......................................................................................... 2:1306.4 RSE Operation ........................................................................................................ 2:1316.5 RSE Control ............................................................................................................ 2:132

6.5.1 Register Stack Configuration Register ....................................................... 2:1326.5.2 Register Stack NaT Collection Register ..................................................... 2:1336.5.3 Backing Store Pointer Application Registers .............................................. 2:1346.5.4 RSE Control Instructions ............................................................................ 2:1356.5.5 Bad PFS used by Branch Return ............................................................... 2:136

6.6 RSE Interruptions .................................................................................................... 2:1376.7 RSE Behavior on Interruptions................................................................................ 2:1396.8 RSE Behavior with an Incomplete Register Frame ................................................. 2:1396.9 RSE and ALAT Interaction ...................................................................................... 2:1396.10 Backing Store Coherence and Memory Ordering ................................................... 2:1406.11 RSE Backing Store Switches .................................................................................. 2:140

6.11.1 Switch from Interrupted Context ................................................................. 2:1416.11.2 Return to Interrupted Context ..................................................................... 2:1416.11.3 Synchronous Backing Store Switch ........................................................... 2:141

6.12 RSE Initialization ..................................................................................................... 2:142

7 Debugging and Performance Monitoring......................................................................... 2:1437.1 Debugging ............................................................................................................... 2:143

7.1.1 Data and Instruction Breakpoint Registers ................................................. 2:1447.1.2 Debug Address Breakpoint Match Conditions............................................ 2:146

7.2 Performance Monitoring .......................................................................................... 2:1477.2.1 Generic Performance Counter Registers ................................................... 2:1487.2.2 Performance Monitor Overflow Status Registers (PMC[0]..PMC[3]) .......... 2:1517.2.3 Performance Monitor Events ...................................................................... 2:1537.2.4 Implementation-independent Performance Monitor Code Sequences....... 2:154

8 Interruption Vector Descriptions ...................................................................................... 2:1578.1 Interruption Vector Descriptions .............................................................................. 2:1578.2 ISR Settings ............................................................................................................ 2:1578.3 Interruption Vector Definition................................................................................... 2:158

9 IA-32 Interruption Vector Descriptions ............................................................................ 2:2039.1 IA-32 Trap Code...................................................................................................... 2:2039.2 IA-32 Interruption Vector Definitions ....................................................................... 2:203

10 Itanium®Architecture-based Operating System Interaction Model with IA-32 Applications...................................................................................................... 2:22910.1 Instruction Set Transitions....................................................................................... 2:22910.2 System Register Model ........................................................................................... 2:22910.3 IA-32 System Segment Registers ........................................................................... 2:231

10.3.1 IA-32 Current Privilege Level ..................................................................... 2:23210.3.2 IA-32 System EFLAG Register................................................................... 2:23310.3.3 IA-32 System Registers.............................................................................. 2:236

10.4 Register Context Switch Guidelines for IA-32 Code................................................ 2:24210.4.1 Entering IA-32 Processes........................................................................... 2:243

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10.4.2 Exiting IA-32 Processes ..............................................................................2:24310.5 IA-32 Instruction Set Behavior Summary .................................................................2:24410.6 System Memory Model.............................................................................................2:250

10.6.1 Virtual Memory References.........................................................................2:25110.6.2 IA-32 Virtual Memory References ...............................................................2:25110.6.3 IA-32 TLB Forward Progress Requirements ...............................................2:25110.6.4 Multiprocessor TLB Coherency ...................................................................2:25210.6.5 IA-32 Physical Memory References ............................................................2:25210.6.6 Supervisor Accesses...................................................................................2:25310.6.7 Memory Alignment ......................................................................................2:25310.6.8 Atomic Operations.......................................................................................2:25410.6.9 Multiprocessor Instruction Cache Coherency..............................................2:25510.6.10 IA-32 Memory Ordering...............................................................................2:255

10.7 I/O Port Space Model ...............................................................................................2:25810.7.1 Virtual I/O Port Addressing..........................................................................2:25910.7.2 Physical I/O Port Addressing.......................................................................2:26010.7.3 IA-32 IN/OUT instructions ...........................................................................2:26110.7.4 I/O Port Accesses by Loads and Stores......................................................2:262

10.8 Debug Model ............................................................................................................2:26310.8.1 Data Breakpoint Register Matching.............................................................2:26310.8.2 Instruction Breakpoint Register Matching....................................................2:264

10.9 Interruption Model ....................................................................................................2:26410.9.1 Interruption Summary..................................................................................2:26510.9.2 IA-32 Numeric Exception Model..................................................................2:267

10.10 Processor Bus Considerations for IA-32 Application Support ..................................2:26710.10.1 IA-32 Compatible Bus Transactions............................................................2:268

11 Processor Abstraction Layer ............................................................................................ 2:26911.1 Firmware Model........................................................................................................2:269

11.1.1 Processor Abstraction Layer (PAL) Overview .............................................2:27211.1.2 Firmware Entrypoints ..................................................................................2:27311.1.3 PAL Entrypoints...........................................................................................2:27311.1.4 SAL Entrypoints...........................................................................................2:27411.1.5 OS Entrypoints ............................................................................................2:27411.1.6 Firmware Address Space ............................................................................2:274

11.2 PAL Power On/Reset ...............................................................................................2:27911.2.1 PALE_RESET .............................................................................................2:27911.2.2 PALE_RESET Exit State.............................................................................2:28011.2.3 PAL Self-test Control Word .........................................................................2:285

11.3 Machine Checks.......................................................................................................2:28611.3.1 PALE_CHECK.............................................................................................2:28611.3.2 PALE_CHECK Exit State ............................................................................2:28811.3.3 Returning to the Interrupted Process ..........................................................2:295

11.4 PAL Initialization Events...........................................................................................2:29611.4.1 PALE_INIT ..................................................................................................2:29611.4.2 PALE_INIT Exit State ..................................................................................2:296

11.5 Platform Management Interrupt (PMI)......................................................................2:30011.5.1 PMI Overview ..............................................................................................2:300

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11.5.2 PALE_PMI Exit State ................................................................................. 2:30111.5.3 Resume from the PMI Handler ................................................................... 2:303

11.6 Power Management ................................................................................................ 2:30311.6.1 Power/Performance States (P-states) ........................................................ 2:304

11.7 PAL Virtualization Support ...................................................................................... 2:31011.7.1 Virtual Processor Descriptor (VPD)............................................................ 2:31111.7.2 Interruption Handling in a Virtual Environment ........................................... 2:31511.7.3 PAL Intercepts in Virtual Environment........................................................ 2:31811.7.4 Virtualization Optimizations ........................................................................ 2:320

11.8 PAL Glossary .......................................................................................................... 2:33011.9 PAL Code Memory Accesses and Restrictions....................................................... 2:33211.10 PAL Procedures ...................................................................................................... 2:332

11.10.1 PAL Procedure Summary........................................................................... 2:33411.10.2 PAL Calling Conventions............................................................................ 2:33711.10.3 PAL Procedure Specifications.................................................................... 2:344

11.11 PAL Virtualization Services ..................................................................................... 2:46311.11.1 PAL Virtualization Service Invocation Convention...................................... 2:46311.11.2 PAL Virtualization Service Specifications................................................... 2:465

Part II: System Programmer’s Guide

1 About the System Programmer’s Guide .......................................................................... 2:4791.1 Overview of the System Programmer’s Guide ........................................................ 2:4791.2 Related Documents................................................................................................. 2:481

2 MP Coherence and Synchronization ................................................................................ 2:4832.1 An Overview of Intel® Itanium® Memory Access Instructions ................................. 2:483

2.1.1 Memory Ordering of Cacheable Memory References ................................ 2:4832.1.2 Loads and Stores ....................................................................................... 2:4842.1.3 Semaphores ............................................................................................... 2:4842.1.4 Memory Fences.......................................................................................... 2:486

2.2 Memory Ordering in the Intel® Itanium® Architecture.............................................. 2:4862.2.1 Memory Ordering Executions..................................................................... 2:4862.2.2 Memory Attributes ...................................................................................... 2:4992.2.3 Understanding Other Ordering Models: Sequential

Consistency and IA-32 ............................................................................... 2:5002.3 Where the Intel® Itanium® Architecture Requires Explicit Synchronization ............ 2:5002.4 Synchronization Code Examples ............................................................................ 2:501

2.4.1 Spin Lock.................................................................................................... 2:5012.4.2 Simple Barrier Synchronization .................................................................. 2:5022.4.3 Dekker’s Algorithm ..................................................................................... 2:5042.4.4 Lamport’s Algorithm ................................................................................... 2:505

2.5 Updating Code Images............................................................................................ 2:5072.5.1 Self-modifying Code ................................................................................... 2:5072.5.2 Cross-modifying Code................................................................................ 2:5082.5.3 Programmed I/O......................................................................................... 2:5092.5.4 DMA ........................................................................................................... 2:511

2.6 References .............................................................................................................. 2:511

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3 Interruptions and Serialization.......................................................................................... 2:5133.1 Terminology..............................................................................................................2:5133.2 Interruption Vector Table..........................................................................................2:5143.3 Interruption Handlers................................................................................................2:515

3.3.1 Execution Environment ...............................................................................2:5153.3.2 Interruption Register State ..........................................................................2:5163.3.3 Resource Serialization of Interrupted State.................................................2:5173.3.4 Resource Serialization upon rfi ...................................................................2:518

3.4 Interruption Handling ................................................................................................2:5183.4.1 Lightweight Interruptions .............................................................................2:5193.4.2 Heavyweight Interruptions...........................................................................2:5193.4.3 Nested Interruptions ....................................................................................2:521

4 Context Management......................................................................................................... 2:5234.1 Preserving Register State across Procedure Calls ..................................................2:523

4.1.1 Preserving General Registers .....................................................................2:5244.1.2 Preserving Floating-point Registers ............................................................2:525

4.2 Preserving Register State in the OS ........................................................................2:5254.2.1 Preservation of Stacked Registers in the OS ..............................................2:5264.2.2 Preservation of Floating-point State in the OS ............................................2:527

4.3 Preserving ALAT Coherency....................................................................................2:5284.4 System Calls ............................................................................................................2:528

4.4.1 epc/Demoting Branch Return ......................................................................2:5294.4.2 break/rfi .......................................................................................................2:5294.4.3 NaT Checking for NaTs in System Calls .....................................................2:530

4.5 Context Switching.....................................................................................................2:5304.5.1 User-level Context Switching ......................................................................2:5304.5.2 Context Switching in an Operating System Kernel......................................2:532

5 Memory Management ........................................................................................................ 2:5335.1 Address Space Model ..............................................................................................2:533

5.1.1 Regions .......................................................................................................2:5335.1.2 Protection Keys ...........................................................................................2:535

5.2 Translation Lookaside Buffers (TLBs) ......................................................................2:5375.2.1 Translation Registers (TRs) ........................................................................2:5375.2.2 Translation Caches (TCs) ...........................................................................2:539

5.3 Virtual Hash Page Table ..........................................................................................2:5425.3.1 Short Format ...............................................................................................2:5435.3.2 Long Format ................................................................................................2:5445.3.3 VHPT Updates ............................................................................................2:544

5.4 TLB Miss Handlers ...................................................................................................2:5455.4.1 Data/Instruction TLB Miss Vectors ..............................................................2:5455.4.2 VHPT Translation Vector.............................................................................2:5465.4.3 Alternate Data/Instruction TLB Miss Vectors...............................................2:5475.4.4 Data Nested TLB Vector .............................................................................2:5485.4.5 Dirty Bit Vector ............................................................................................2:5485.4.6 Data/Instruction Access Bit Vector ..............................................................2:5485.4.7 Page Not Present Vector.............................................................................2:548

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5.4.8 Data/Instruction Access Rights Vector ....................................................... 2:5485.5 Subpaging ............................................................................................................... 2:549

6 Runtime Support for Control and Data Speculation ....................................................... 2:5516.1 Exception Deferral of Control Speculative Loads.................................................... 2:551

6.1.1 Hardware-only Deferral .............................................................................. 2:5526.1.2 Combined Hardware/Software Deferral...................................................... 2:5526.1.3 Software-only Deferral................................................................................ 2:552

6.2 Speculation Recovery Code Requirements ............................................................ 2:5526.3 Speculation Related Exception Handlers ................................................................ 2:553

6.3.1 Unaligned Handler...................................................................................... 2:553

7 Instruction Emulation and Other Fault Handlers ............................................................ 2:5557.1 Unaligned Reference Handler ................................................................................. 2:5557.2 Unsupported Data Reference Handler .................................................................... 2:5567.3 Illegal Dependency Fault ......................................................................................... 2:5567.4 Long Branch ............................................................................................................ 2:557

8 Floating-point System Software ....................................................................................... 2:5598.1 Floating-point Exceptions in the Intel® Itanium® Architecture ................................. 2:559

8.1.1 Software Assistance Exceptions (Faults and Traps) .................................. 2:5598.1.2 The IEEE Floating-point Exception Filter.................................................... 2:562

8.2 IA-32 Floating-point Exceptions .............................................................................. 2:564

9 IA-32 Application Support ................................................................................................. 2:5659.1 Transitioning between Intel® Itanium® and IA-32 Instruction Sets .......................... 2:566

9.1.1 IA-32 Code Execution Environments ......................................................... 2:5669.1.2 br.ia ............................................................................................................ 2:5669.1.3 JMPE.......................................................................................................... 2:5679.1.4 Procedure Calls between Intel® Itanium® and IA-32 Instruction Sets ........ 2:567

9.2 IA-32 Architecture Handlers .................................................................................... 2:5689.3 Debugging IA-32 and Itanium®Architecture-based Code........................................ 2:570

9.3.1 Instruction Breakpoints ............................................................................... 2:5709.3.2 Data Breakpoints ........................................................................................ 2:5709.3.3 Single Step Traps....................................................................................... 2:5719.3.4 Taken Branch Traps................................................................................... 2:571

10 External Interrupt Architecture ......................................................................................... 2:57310.1 External Interrupt Basics ......................................................................................... 2:57310.2 Configuration of External Interrupt Vectors ............................................................. 2:57310.3 External Interrupt Masking ...................................................................................... 2:574

10.3.1 PSR.i .......................................................................................................... 2:57410.3.2 IVR Reads and EOI Writes......................................................................... 2:57510.3.3 Task Priority Register (TPR)....................................................................... 2:57510.3.4 External Task Priority Register (XTPR) ...................................................... 2:575

10.4 External Interrupt Delivery....................................................................................... 2:57510.5 Interrupt Control Register Usage Examples............................................................ 2:577

10.5.1 Notation ...................................................................................................... 2:577

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10.5.2 TPR and XPTR Usage Example .................................................................2:57710.5.3 EOI Usage Example....................................................................................2:57810.5.4 IRR Usage Example....................................................................................2:57910.5.5 Interval Timer Usage Example ....................................................................2:57910.5.6 Local Redirection Example..........................................................................2:58010.5.7 Inter-processor Interrupts Layout and Example ..........................................2:58110.5.8 INTA Example .............................................................................................2:582

11 I/O Architecture .................................................................................................................. 2:58311.1 Memory Acceptance Fence (mf.a) ...........................................................................2:58311.2 I/O Port Space..........................................................................................................2:584

12 Performance Monitoring Support ..................................................................................... 2:58712.1 Architected Performance Monitoring Mechanisms...................................................2:58712.2 Operating System Support .......................................................................................2:588

13 Firmware Overview ............................................................................................................ 2:59113.1 Processor Boot Flow Overview ................................................................................2:591

13.1.1 Firmware Boot Flow ....................................................................................2:59113.1.2 Operating System Boot Steps .....................................................................2:593

13.2 Runtime Procedure Calls .........................................................................................2:59613.2.1 PAL Procedure Calls ...................................................................................2:59613.2.2 SAL Procedure Calls ...................................................................................2:59813.2.3 EFI Procedure Calls ....................................................................................2:59813.2.4 Physical and Virtual Addressing Mode Considerations...............................2:598

13.3 Event Handling in Firmware .....................................................................................2:59913.3.1 Machine Check Abort (MCA) Flows ............................................................2:59913.3.2 INIT Flows ...................................................................................................2:60213.3.3 PMI Flows....................................................................................................2:60313.3.4 P-state Feedback Mechanism Flow Diagram..............................................2:604

A Code Examples .................................................................................................................. 2:607A.1 OS Boot Flow Sample Code ....................................................................................2:607

FiguresPart I: System Architecture Guide2-1 System Environment Boot Flow ..............................................................................................2:122-2 Intel® Itanium® System Environment ......................................................................................2:133-1 System Register Model ...........................................................................................................2:193-2 Processor Status Register (PSR)............................................................................................2:203-3 Default Control Register (DCR – CR0)....................................................................................2:283-4 Interval Time Counter (ITC – AR44)........................................................................................2:293-5 Interval Timer Match Register (ITM – CR1) ............................................................................2:293-6 Interruption Vector Address (IVA – CR2) ................................................................................2:303-7 Page Table Address (PTA – CR8) ..........................................................................................2:313-8 Interruption Status Register (ISR – CR17)..............................................................................2:323-9 Interruption Instruction Bundle Pointer (IIP – CR19)...............................................................2:33

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3-10 Interruption Faulting Address (IFA – CR20) ........................................................................... 2:343-11 Interruption TLB Insertion Register (ITIR) .............................................................................. 2:353-12 Interruption Instruction Previous Address (IIPA – CR22) ....................................................... 2:363-13 Interruption Function State (IFS – CR23)............................................................................... 2:363-14 Interruption Immediate (IIM – CR24)...................................................................................... 2:373-15 Interruption Hash Address (IHA – CR25) ............................................................................... 2:373-16 Banked General Registers ..................................................................................................... 2:384-1 Virtual Address Spaces .......................................................................................................... 2:424-2 Conceptual Virtual Address Translation for References ........................................................ 2:434-3 TLB Organization ................................................................................................................... 2:434-4 Conceptual Virtual Address Searching for Inserts and Purges .............................................. 2:474-5 Translation Insertion Format .................................................................................................. 2:494-6 Translation Insertion Format – Not Present ........................................................................... 2:514-7 Region Register Format ......................................................................................................... 2:534-8 Protection Key Register Format ............................................................................................. 2:544-9 Virtual Hash Page Table (VHPT) ........................................................................................... 2:564-10 VHPT Short Format................................................................................................................ 2:584-11 VHPT Not-present Short Format ............................................................................................ 2:584-12 VHPT Long Format ................................................................................................................ 2:584-13 VHPT Not-present Long Format............................................................................................. 2:594-14 Region-based VHPT Short-format Index Function................................................................. 2:604-15 VHPT Long-format Hash Function ......................................................................................... 2:614-16 TLB/VHPT Search.................................................................................................................. 2:644-17 32-bit Address Generation using addp4................................................................................. 2:664-18 Physical Address Bit Fields .................................................................................................... 2:674-19 Virtual Address Bit Fields ....................................................................................................... 2:684-20 Physical Addressing Memory ................................................................................................. 2:704-21 Addressing Memory Attributes ............................................................................................... 2:715-1 Interruption Classification ....................................................................................................... 2:915-2 Interruption Processing .......................................................................................................... 2:935-3 Interrupt Architecture Overview............................................................................................ 2:1085-4 PAL-based Interrupt States .................................................................................................. 2:1115-5 External Interrupt States....................................................................................................... 2:1115-6 Local ID (LID – CR64) .......................................................................................................... 2:1165-7 External Interrupt Vector Register (IVR – CR65) ................................................................. 2:1175-8 Task Priority Register (TPR – CR66) ................................................................................... 2:1175-9 End of External Interrupt Register (EOI – CR67) ................................................................. 2:1185-10 External Interrupt Request Register (IRR0-3 – CR68, 69, 70, 71) ....................................... 2:1185-11 Interval Timer Vector (ITV – CR72)...................................................................................... 2:1185-12 Performance Monitor Vector (PMV – CR73) ........................................................................ 2:1195-13 Corrected Machine Check Vector (CMCV – CR74) ............................................................. 2:1195-14 Local Redirection Register (LRR – CR80,81) ...................................................................... 2:1205-15 Processor Interrupt Block Memory Layout ........................................................................... 2:1225-16 Address Format for Inter-processor Interrupt Messages...................................................... 2:1235-17 Data Format for Inter-processor Interrupt Messages ........................................................... 2:1236-1 Relationship Between Physical Registers and Backing Store.............................................. 2:1286-2 Backing Store Memory Format............................................................................................. 2:1286-3 Four Partitions of the Register Stack.................................................................................... 2:1307-1 Data Breakpoint Registers (DBR) ........................................................................................ 2:1447-2 Instruction Breakpoint Registers (IBR) ................................................................................. 2:1447-3 Performance Monitor Register Set ....................................................................................... 2:1487-4 Generic Performance Counter Data Registers (PMD[4]..PMD[p]) ....................................... 2:149

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7-5 Generic Performance Counter Configuration Register (PMC[4]..PMC[p]) ............................2:1497-6 Performance Monitor Overflow Status Registers (PMC[0]..PMC[3]).....................................2:1527-7 Performance Monitor Interrupt Service Routine (Implementation Independent) ...................2:1557-8 Performance Monitor Overflow Context Switch Routine .......................................................2:1569-1 IA-32 Trap Code....................................................................................................................2:2039-2 IA-32 Trap Code....................................................................................................................2:2039-3 IA-32 Intercept Code .............................................................................................................2:22410-1 IA-32 System Segment Register Descriptor Format (LDT, GDT, TSS) ................................2:23110-2 IA-32 EFLAG Register ..........................................................................................................2:23310-3 Control Flag Register (CFLG, AR27) ....................................................................................2:23610-4 Virtual Memory Addressing ...................................................................................................2:25010-5 Physical Memory Addressing................................................................................................2:25310-6 I/O Port Space Model ............................................................................................................2:25810-7 I/O Port Space Addressing....................................................................................................2:25911-1 Firmware Model ....................................................................................................................2:27011-2 Firmware Services Model......................................................................................................2:27111-3 Firmware Entrypoints Logical Model .....................................................................................2:27311-4 Firmware Address Space......................................................................................................2:27511-5 Firmware Address Space with Processor-specific PAL_A Components...............................2:27611-6 Firmware Interface Table ......................................................................................................2:27811-7 Firmware Interface Table Entry.............................................................................................2:27811-8 SALE_ENTRY State Parameter............................................................................................2:28211-9 Geographically Significant Processor Identifier.....................................................................2:28411-10 Self Test State Parameter.....................................................................................................2:28411-11 Self-test Control Word...........................................................................................................2:28511-12 Processor State Parameter ...................................................................................................2:28911-13 Processor Min-state Save Area Layout.................................................................................2:29211-14 Processor State Saved in Min-state Save Area ....................................................................2:29411-15 SALE_ENTRY State Parameter............................................................................................2:29511-16 Processor State Parameter ...................................................................................................2:29711-17 SALE_ENTRY State Parameter............................................................................................2:29911-18 PMI Entrypoints.....................................................................................................................2:30011-19 Power States.........................................................................................................................2:30311-20 Power and Performance Characteristics for P-states ...........................................................2:30511-21 Example of a P-state Transition Policy .................................................................................2:30611-22 Computation of performance_index ......................................................................................2:30911-23 Interaction of P-states with HALT State ................................................................................2:31011-24 Virtualization Acceleration Control (vac) ...............................................................................2:31411-25 Virtualization Disable Control (vdc) .......................................................................................2:31411-26 PAL Virtualization Intercept Handoff Opcode (GR25)...........................................................2:32011-27 operation Parameter Layout..................................................................................................2:35011-28 config_info_1 Return Value...................................................................................................2:35311-29 config_info_2 Return Value...................................................................................................2:35511-30 config_info_1 Return Value...................................................................................................2:35811-31 config_info_2 Return Value...................................................................................................2:35811-32 config_info_3 Return Value...................................................................................................2:35911-33 cache_protection Fields ........................................................................................................2:35911-34 Layout of line_id Return Value ..............................................................................................2:36011-35 Layout of proc_n_cache_info1 Return Value ........................................................................2:36311-36 Layout of proc_n_cache_info2 Return Value ........................................................................2:36311-37 Layout of line_id Return Value ..............................................................................................2:36611-38 Layout of platform_info Input Parameter ...............................................................................2:368

xii Volume 2: Intel® Itanium® Architecture Software Developer’s Manual

11-39 I/O Size and Type Information Layout.................................................................................. 2:38611-40 Layout of power_buffer Return Value................................................................................... 2:38811-41 Layout of log_overview Return Value................................................................................... 2:39211-42 Layout of proc_n_log_info1 Return Value ............................................................................ 2:39211-43 Layout of proc_n_log_info2 Return Value ............................................................................ 2:39311-44 Pending Return Parameter................................................................................................... 2:39411-45 level_index Layout................................................................................................................ 2:39811-46 cache_check Layout............................................................................................................. 2:40111-47 tlb_check Layout .................................................................................................................. 2:40211-48 bus_check Layout ................................................................................................................ 2:40311-49 reg_file_check Layout .......................................................................................................... 2:40411-50 uarch_check Layout ............................................................................................................. 2:40611-51 err_type_info ........................................................................................................................ 2:40711-52 resources Return Value........................................................................................................ 2:40911-53 err_struct_info – Cache ........................................................................................................ 2:41011-54 capabilities Vector for Cache................................................................................................ 2:41111-55 Buffer Pointed to by err_data_buffer – Cache...................................................................... 2:41211-56 err_struct_info – TLB............................................................................................................ 2:41211-57 capabilities Vector for TLB ................................................................................................... 2:41311-58 Buffer Pointed to by err_data_buffer – TLB.......................................................................... 2:41411-59 err_struct_info – Register File .............................................................................................. 2:41411-60 capabilities Vector for Register File...................................................................................... 2:41511-61 Buffer Pointed to by err_data_buffer – Register File ............................................................ 2:41611-62 err_struct_info – Bus/Processor Interconnect ...................................................................... 2:41611-63 capabilities Vector for Bus/Processor Interconnect.............................................................. 2:41611-64 Layout of attrib Return Value................................................................................................ 2:42011-65 Layout of pm_info Return Value........................................................................................... 2:42311-66 Layout of pstate_buffer Entry ............................................................................................... 2:43411-67 Layout of dd_info Parameter ................................................................................................ 2:43511-68 Layout of hints Return Value ................................................................................................ 2:43811-69 Layout of test_info Argument ............................................................................................... 2:44411-70 Layout of test_param Argument ........................................................................................... 2:44511-71 Layout of min_pal_ver and current_pal_ver Return Values ................................................. 2:44711-72 Layout of tc_info Return Value ............................................................................................. 2:44811-73 Layout of vm_info_1 Return Value ....................................................................................... 2:45011-74 Layout of vm_info_2 Return Value ....................................................................................... 2:45111-75 Layout of TR_valid Return Value ......................................................................................... 2:452

Part II: System Programmer’s Guide2-1 Intel® Itanium® Ordering Semantics..................................................................................... 2:4882-2 Interaction of Ordering and Accesses to Sequential Locations............................................ 2:4992-3 Why a Fence During Context Switches is Required in the Intel® Itanium® Architecture...... 2:5012-4 Spin Lock Code .................................................................................................................... 2:5022-5 Sense-reversing Barrier Synchronization Code ................................................................... 2:5032-6 Dekker’s Algorithm in a 2-way System................................................................................. 2:5042-7 Lamport’s Algorithm ............................................................................................................. 2:5062-8 Updating a Code Image on the Local Processor.................................................................. 2:5072-9 Supporting Cross-modifying Code without Explicit Serialization .......................................... 2:5082-10 Updating a Code Image on a Remote Processor................................................................. 2:5105-1 Self-mapped Page Table...................................................................................................... 2:5445-2 Subpaging ............................................................................................................................ 2:549

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8-1 Overview of Floating-point Exception Handling in the Intel® Itanium® Architecture..............2:56113-1 Firmware Model ....................................................................................................................2:59213-2 Control Flow of Boot Process in a Multiprocessor Configuration ..........................................2:59413-3 Correctable Machine Check Code Flow................................................................................2:60013-4 Uncorrectable Machine Check Code Flow............................................................................2:60013-5 INIT Flow...............................................................................................................................2:60313-6 Flowchart Showing P-state Feedback Policy ........................................................................2:605

TablesPart I: System Architecture Guide3-1 Processor Status Register Instructions ................................................................................2:203-2 Processor Status Register Fields .........................................................................................2:213-3 Control Registers..................................................................................................................2:263-4 Control Register Instructions ................................................................................................2:273-5 Default Control Register Fields ............................................................................................2:283-6 Page Table Address Fields ..................................................................................................2:313-7 Interruption Status Register Fields .......................................................................................2:323-8 ITIR Fields ............................................................................................................................2:353-9 Interruption Function State Fields ........................................................................................2:363-10 Virtualized Instructions .........................................................................................................2:394-1 Purge Behavior of TLB Inserts and Purges..........................................................................2:474-2 Translation Interface Fields ..................................................................................................2:494-3 Page Access Rights .............................................................................................................2:514-4 Architected Page Sizes ........................................................................................................2:524-5 Region Register Fields .........................................................................................................2:534-6 Protection Register Fields ....................................................................................................2:544-7 Translation Instructions ........................................................................................................2:554-8 VHPT Long-format Fields.....................................................................................................2:594-9 TLB and VHPT Search Faults ..............................................................................................2:644-10 Virtual Addressing Memory Attribute Encodings ..................................................................2:694-11 Physical Addressing Memory Attribute Encodings...............................................................2:704-12 Permitted Speculation ..........................................................................................................2:744-13 Register Return Values on Non-faulting Advanced/Speculative Loads ...............................2:744-14 Ordering Semantics and Instructions ...................................................................................2:764-15 Ordering Semantics..............................................................................................................2:774-16 ALAT Behavior on Non-faulting Advanced/Check Loads.....................................................2:815-1 ISR Settings for Non-access Instructions.............................................................................2:975-2 Programming Models ...........................................................................................................2:995-3 Exception Qualification.........................................................................................................2:995-4 Qualified Exception Deferral...............................................................................................2:1015-5 Spontaneous Deferral ........................................................................................................2:1015-6 Interruption Priorities ..........................................................................................................2:1025-7 Interruption Vector Table (IVT)...........................................................................................2:1065-8 Interrupt Priorities, Enabling, and Masking.........................................................................2:1125-9 External Interrupt Control Registers ...................................................................................2:1155-10 Local ID Fields....................................................................................................................2:1165-11 Task Priority Register Fields ..............................................................................................2:1175-12 Interval Timer Vector Fields ...............................................................................................2:1195-13 Performance Monitor Vector Fields....................................................................................2:1195-14 Corrected Machine Check Vector Fields............................................................................2:119

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5-15 Local Redirection Register Fields...................................................................................... 2:1215-16 Address Fields for Inter-processor Interrupt Messages..................................................... 2:1235-17 Data Fields for Inter-processor Interrupt Messages .......................................................... 2:1246-1 RSE Internal State............................................................................................................. 2:1296-2 RSE Operation Instructions and State Modification .......................................................... 2:1326-3 RSE Modes (RSC.mode) .................................................................................................. 2:1336-4 Backing Store Pointer Application Registers ..................................................................... 2:1356-5 RSE Control Instructions ................................................................................................... 2:1366-6 RSE Interruption Summary................................................................................................ 2:1387-1 Debug Breakpoint Register Fields (DBR/IBR)................................................................... 2:1457-2 Debug Instructions............................................................................................................. 2:1457-3 Generic Performance Counter Data Register Fields ......................................................... 2:1497-4 Generic Performance Counter Configuration Register Fields (PMC[4]..PMC[p]).............. 2:1497-5 Reading Performance Monitor Data Registers.................................................................. 2:1507-6 Performance Monitor Instructions...................................................................................... 2:1517-7 Performance Monitor Overflow Register Fields (PMC[0]...PMC[3]) .................................. 2:1538-1 Writing of Interruption Resources by Vector...................................................................... 2:1588-2 ISR Values on Interruption ................................................................................................ 2:1598-3 ISR.code Fields on Intel® Itanium® Traps ......................................................................... 2:1618-4 Interruption Vectors Sorted Alphabetically ........................................................................ 2:1629-1 Intercept Code Definition ................................................................................................... 2:2249-2 Segment Prefix Override Encodings ................................................................................. 2:2249-3 Gate Intercept Trap Code Identifier ................................................................................... 2:2259-4 System Flag Intercept Instruction Trap Code Instruction Identifier.................................... 2:22610-1 IA-32 System Register Mapping........................................................................................ 2:23010-2 IA-32 System Segment Register Fields (LDT, GDT, TSS)................................................ 2:23110-3 IA-32 EFLAG Field Definition ............................................................................................ 2:23410-4 IA-32 Control Register Field Definition .............................................................................. 2:23710-5 IA-32 Instruction Summary ................................................................................................ 2:24410-6 Instruction Cache Coherency Rules .................................................................................. 2:25510-7 IA-32 Load/Store Sequentiality and Ordering.................................................................... 2:25610-8 IA-32 Interruption Vector Summary ................................................................................... 2:26510-9 IA-32 Interruption Summary .............................................................................................. 2:26511-1 FIT Entry Types ................................................................................................................. 2:27911-2 GR38 Reset Layout ........................................................................................................... 2:28111-3 function Field Values ......................................................................................................... 2:28211-4 status Field Values ............................................................................................................ 2:28211-5 Geographically Significant Processor Identifier Fields ...................................................... 2:28411-6 state Field Values .............................................................................................................. 2:28411-7 Processor State Parameter Fields..................................................................................... 2:28911-8 Software Recovery Bits in Processor State Parameter ..................................................... 2:29111-9 function Field Values ......................................................................................................... 2:29511-10 Processor State Parameter Fields..................................................................................... 2:29811-11 function Field Values ......................................................................................................... 2:29911-12 PMI Events and Priorities .................................................................................................. 2:30011-13 PMI Message Vector Assignments.................................................................................... 2:30111-14 Virtual Processor Descriptor (VPD) ................................................................................... 2:31211-15 Virtualization Acceleration Control (vac) Fields ................................................................. 2:31411-16 Virtualization Disable Control (vdc) Fields......................................................................... 2:31511-17 IVA Settings after PAL Virtualization-related Procedures and Services............................ 2:31611-18 PAL Virtualization Intercept Handoff Cause (GR24) ......................................................... 2:31911-19 Virtualization Accelerations Summary ............................................................................... 2:321

Volume 2: Intel® Itanium® Architecture Software Developer’s Manual xv

11-20 Detection of Virtual External Interrupts...............................................................................2:32211-21 Synchronization Requirements for Virtual External Interrupt Optimization ........................2:32211-22 Interruptions when Virtual External Interrupt Optimization is Enabled ...............................2:32211-23 Synchronization Requirements for Interruption Control Register Read Optimization ........2:32311-24 Interruptions when Interruption Control Register Read Optimization is Enabled ...............2:32311-25 Synchronization Requirements for Interruption Control Register Write Optimization.........2:32411-26 Interruptions when Interruption Control Register Write Optimization is Enabled ...............2:32411-27 Synchronization Requirements for MOV-from-PSR Optimization ......................................2:32511-28 Interruptions when MOV-from-PSR Optimization is Enabled.............................................2:32511-29 Synchronization Requirements for MOV-from-CPUID Optimization ..................................2:32511-30 Interruptions when MOV-from-CPUID Optimization is Enabled .........................................2:32611-31 Synchronization Requirements for Cover Optimization......................................................2:32611-32 Interruptions when Cover Optimization is Enabled ............................................................2:32611-33 Interruptions when Bank Switch Optimization is Enabled ..................................................2:32711-34 Virtualization Disables Summary........................................................................................2:32711-35 PAL Procedure Index Assignment .....................................................................................2:33311-36 PAL Cache and Memory Procedures.................................................................................2:33411-37 PAL Processor Identification, Features, and Configuration Procedures ............................2:33411-38 PAL Machine Check Handling Procedures ........................................................................2:33511-39 PAL Power Information and Management Procedures ......................................................2:33511-40 PAL Processor Self Test Procedures.................................................................................2:33611-41 PAL Support Procedures....................................................................................................2:33611-42 PAL Virtualization Support Procedures ..............................................................................2:33611-43 State Requirements for PSR ..............................................................................................2:33811-44 Definition of Terms .............................................................................................................2:34011-45 System Register Conventions ............................................................................................2:34011-46 General Registers – Static Calling Convention ..................................................................2:34111-47 General Registers – Stacked Calling Conventions ............................................................2:34111-48 Application Register Conventions ......................................................................................2:34311-49 Processor Brand Information Requested ...........................................................................2:34511-50 Processor Bus Features.....................................................................................................2:34611-51 cache_type Encoding .........................................................................................................2:34911-52 Cache Line State when inv = 0...........................................................................................2:35011-53 Cache Line State when inv = 1...........................................................................................2:35111-54 Cache Memory Attributes...................................................................................................2:35411-55 Cache Store Hints ..............................................................................................................2:35411-56 Cache Load Hints...............................................................................................................2:35411-57 PAL_CACHE_INIT level Argument Values ........................................................................2:35611-58 PAL_CACHE_INIT restrict Argument Values.....................................................................2:35611-59 method Values ...................................................................................................................2:35911-60 t_d Values ..........................................................................................................................2:35911-61 part Input Values ................................................................................................................2:36111-62 part Input Values and corresponding data Return Values..................................................2:36111-63 mesi Return Values ............................................................................................................2:36111-64 part Input Values ................................................................................................................2:36611-65 mesi Return Values ............................................................................................................2:36611-66 Interpretation of data Input Field ........................................................................................2:36711-67 IA-32 System Environment Entry Parameters....................................................................2:37211-68 MP Information Table .........................................................................................................2:37411-69 SAL I/O Intercept Table......................................................................................................2:37411-70 IA-32 Resources at IA-32 System Environment Entry .......................................................2:37511-71 Register Values at IA-32 System Environment Termination ..............................................2:376

xvi Volume 2: Intel® Itanium® Architecture Software Developer’s Manual

11-72 Hardware policies returned in cur_policy........................................................................... 2:38211-73 PAL_GET_PSTATE type Argument .................................................................................. 2:38411-74 I/O Detail Pointer Description ............................................................................................ 2:38611-75 I/O Type Definition............................................................................................................. 2:38611-76 I/O Size Definition.............................................................................................................. 2:38611-77 Pending Return Parameter Fields ..................................................................................... 2:39411-78 info_index Values .............................................................................................................. 2:39811-79 level_index Fields .............................................................................................................. 2:39911-80 err_type_index Values....................................................................................................... 2:39911-81 error_info Return Format when info_index = 2 and err_type_index = 0 ............................ 2:40011-82 cache_check Fields ........................................................................................................... 2:40111-83 tlb_check Fields................................................................................................................. 2:40211-84 bus_check Fields............................................................................................................... 2:40311-85 reg_file_check Fields......................................................................................................... 2:40511-86 uarch_check Fields............................................................................................................ 2:40611-87 err_type_info...................................................................................................................... 2:40811-88 resources Return Value..................................................................................................... 2:40911-89 err_struct_info – Cache ..................................................................................................... 2:41011-90 capabilities Vector for Cache............................................................................................. 2:41111-91 Buffer Pointed to by err_data_buffer – Cache................................................................... 2:41211-92 err_struct_info – TLB......................................................................................................... 2:41211-93 capabilities Vector for TLB................................................................................................. 2:41311-94 Buffer Pointed to by err_data_buffer – TLB....................................................................... 2:41411-95 err_struct_info – Register File ........................................................................................... 2:41411-96 capabilities Vector for Register File ................................................................................... 2:41511-97 Buffer Pointed to by err_data_buffer – Register File ......................................................... 2:41611-98 err_struct_info – Bus/Processor Interconnect ................................................................... 2:41611-99 capabilities Vector for Bus/Processor Interconnect ........................................................... 2:41611-100 control_word Layout .......................................................................................................... 2:42111-101 pm_info Fields ................................................................................................................... 2:42311-102 pm_buffer Layout............................................................................................................... 2:42311-103 Processor Features ........................................................................................................... 2:43011-104 Values for ddt Field............................................................................................................ 2:43511-105 info_request Return Value................................................................................................. 2:43711-106 RSE Hints Implemented .................................................................................................... 2:43811-107 Processor Hardware Sharing Policies ............................................................................... 2:43911-108 notify_platform Layout ....................................................................................................... 2:44211-109 vp_env_info – Virtual Environment Information Parameter ............................................... 2:45411-110 config_options – Global Configuration Options ................................................................. 2:45711-111 Format of pal_proc_vector................................................................................................. 2:45911-112 PAL Virtualization Services ............................................................................................... 2:46311-113 State Requirements for PSR for PAL Virtualization Services............................................ 2:46411-114 Virtual Processor Settings in Architectural Resources for

PAL_VPS_RESUME_NORMAL and PAL_VPS_RESUME_HANDLER ........................... 2:46611-115 vhpi – Virtual Highest Priority Pe