The clock

10/23/2008 1ECE 561 - Lecture

Clocking Issues

• Clock Skew• Gating the clock

• Section 8.8 of text

10/23/2008 2ECE 561 - Lecture

Clock Skew

• A definition – The difference in the arrival time of the clock at different devices.

• What gives rise to clock skew?

10/23/2008 3ECE 561 - Lecture

CLK

Clock Skew parameters

• For proper operation– tffpd(min) + tcomb(min) – thold – tskew(max) > 0

– Where– tffpd(min)-the propagation delay of F/F clk->Q

– tcomb(min) –the time for the combinational logic of the F/F

– Thold –the hold time of the F/F

– tskew(max) –the clock skew. Note that it subtracts from the hold time margin

10/23/2008 4ECE 561 - Lecture

Best to buffer the clock

• Take input clock into buffers that have less load then the entire chip/circuit

10/23/2008 ECE 561 - Lecture 5

CLK

Gating the clock

• When some elements of the circuit need to be sensitive at times and ignore the clock at others

• A simple AND gate approach– Can produce glitches– Causes excessive skew

10/23/2008 ECE 561 - Lecture 6

Preferred gating the clock

• This is a method that addresses the disadvantages of a simple AND gate.

10/23/2008 ECE 561 - Lecture 7

CLK

GCLK1

GCLK2

CLKEN1

CLKEN2