The Chip Design Crisis
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Transcript of The Chip Design Crisis
![Page 1: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/1.jpg)
Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms
The Chip Design Crisis
Univ.-Prof. Dr.-Ing. Markus Rupp
June,2 2008
![Page 2: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/2.jpg)
slide 2Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Outline Why Mobile Communications?
Problems in the Design of Wireless Systems Complexity Gap Design Productivity Gap
Problems and Solutions Parallelism, IP-Reuse, Predictive Design Inconsistent Design, Lack of Tool Support, Refinement Techniques,
Design Languages, Automatic HW/SW Partitioning Virtual Prototyping, Automatic Testing and Verification, Automatic Float
to Fix Conversion Static Code Analysis, automatic DFG and CFG Generation, Code
Understanding and Interpretation Low Power and Power aware Designs
Software Defined Radio Conclusions
![Page 3: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/3.jpg)
slide 3Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Why Mobile Communications?
Communication is a deep, human requirement In particular in oral form
We would like to speak with arbitrary persons any time at any location.
![Page 4: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/4.jpg)
slide 4Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Mobile communication of the past C-Netz Autotelefonnetz C Start Nov.1984 First only in automobiles (later portable 10 kg) Starting price ca. 50.000 öS First fully automatic
mobile cellular net (radius about 15 km)
![Page 5: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/5.jpg)
slide 5Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
How do we communicate today?
GSM Developed to support speech only (intro Austria in
94) Although, today also SMS (in Austria 95) and with
GPRS also data transmission possible. UMTS
Supports equally speech and various data services
Even Multimedia Application with Video Streaming WLAN
Originally planned as pure data communication (Internet)
Supports also speech services (VoIP)
![Page 6: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/6.jpg)
slide 6Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Is Mobile Communication successful?
Until selling of one Million units, it took…
![Page 7: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/7.jpg)
slide 7Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Is Mobile Communication successful?
http://www.rtr.at/en/tk/TeilnehmerstaendeMF2007
User in Austriain Millions
2005
8,4
2006
9,6
2006
9,7
![Page 8: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/8.jpg)
slide 8Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
What makes Mobile Communications a difficult
task? Limited Spectrum
Most of Spectrum is used by ORF!
![Page 9: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/9.jpg)
slide 9Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Spectrum
2 G H z 3 G H z1 G H z
G S M1 80 0
G S M1 80 0
D E C T
U M T S U M T S
U M T S S ate llite
G S M 9 00
T E T R A IS M
D -N etz
IR ID IU M
3 00 M H z
8 7 28 9 0
9 0 5 9 1 79 3 5 9 6 09 1 5
9 5 0 M H z1 9 0 0 1 9 8 0 2 0 1 0 2 11 0 2 1 7 0 2 2 0 0
1 7 1 0 1 7 8 5 1 8 0 5 1 8 8 0 1 9 0 01 6 2 1 .3 5
1 6 2 6 .54 1 0
4 3 04 3 3 .5
4 3 4 .7 94 5 0 4 7 0
M H z
M H z
M H z
UHF Band
8 8 0 9 2 5
E G S M
Q u e lle : , E u ro p ea n R a d io co m m u n ic a tio n s O ffice , e rs te llt:T. N eu b au e rE R O
![Page 10: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/10.jpg)
slide 10Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
What makes Mobile Communications a difficult
task? Limited Spectrum
Most of Spectrum is used by ORF! Limited Battery Power
Battery increases with 2% per year
![Page 11: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/11.jpg)
slide 11Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Power
Handy requires only 0,000 000 000 000 1 Watt for reception!
![Page 12: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/12.jpg)
slide 12Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
What makes Mobile Communications a difficult
task? Limited Spectrum
Most of Spectrum is used by ORF! Limited Battery Power
Battery increases with 2% per year Multi-path propagation
![Page 13: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/13.jpg)
slide 13Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Multi Path Propagation
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slide 14Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Multi Path Propagation
![Page 15: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/15.jpg)
slide 15Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
What makes Mobile Communications a difficult
task? Limited Spectrum
Most of Spectrum is used by ORF! Limited Battery Power
Battery increases with 2% per year Multi-path propagation Complexity
![Page 16: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/16.jpg)
slide 16Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Complexity Gap in 3rd G. Wireless
Processor Performance
(Moore)
![Page 17: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/17.jpg)
slide 17Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Design Productivity Gap
Logic Tr./Chip
Tr./S.M.
Source: SEMATECH
.001
.01
.1
1
10
100
1,000
10,000
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
58%/Yr. compoundComplexity growth rate
21%/Yr. compoundProductivity growth rate
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2003
2001
2005
2007
2009
xxx
x xx
x
2.5
.10
.35
Transistors per Chip (M) Productivity Trans./Staff - Mo.
x
![Page 18: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/18.jpg)
slide 18Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Some Observations in 3rd Generation Wireless
Today, about 70% of development time is verification.
90% of the product cost are predetermined by its detailed specification.
Standards (UMTS R99 in Dec.1999, R4 in March 2001, R5 in March 2003, R6 (Dez 04), R7 (Sep 05), R8 (Nov 07?). change faster than the product design cycle.
The required time to market becomes decisive: launching six months early, triples profits, six months late results in breaking even.
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slide 19Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Sematech‘s Answer (1999)
For every $1 invested in EDA tools, an additional $2 to $5 are spent on integration into the design flow.
No EDA vendor or using company can supply all the tools needed today.
Promote rapid integration of new tools from industry and university research.
Create Chip Hierarchical Design System technical standard (CHDStd)
This has not happened until today!
![Page 20: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/20.jpg)
slide 20Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Outline Why Mobile Communications?
Problems in the Design of Wireless Systems Complexity Gap Design Productivity Gap
Problems and Solutions Parallelism, IP-Reuse, Predictive Design Inconsistent Design, Lack of Tool Support, Refinement Techniques,
Design Languages, Automatic HW/SW Partitioning Virtual Prototyping, Automatic Testing and Verification, Automatic Float
to Fix Conversion Static Code Analysis, automatic DFG and CFG Generation, Code
Understanding and Interpretation Low Power and Power aware Designs
Software Defined Radio Conclusions
![Page 21: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/21.jpg)
slide 21Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Problems and Solutions
Solutions to the Complexity Problem: Predictive Design Parallelism Hardware Accelerators Re-using IP
= “Classical Approaches”
![Page 22: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/22.jpg)
slide 22Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Problems and Solutions
Solutions to the Design Productivity Problem:
No Solutions currently in Products
Multitude of Problems exist:
![Page 23: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/23.jpg)
slide 23Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Inconsistent Design
Research
System-Design
Implementation
Marketing
![Page 24: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/24.jpg)
slide 24Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Ptolemy
Lack in Tool SupportHigh Level of abstraction Low
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slide 25Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Lack in Tool Support
A multitude of EDA Tools exists already . However, they all cover only a certain part of
the design flow. Major disadvantage of existing EDA Tools:
not compatible to each other! Basic lack exists in:
HW/SW/FW partitioning Platform based designs Float-to-Fix conversion Power aware design at High Level description
![Page 26: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/26.jpg)
slide 26Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Dream: Consistent Design Flow
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slide 27Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Dream: Consistent Design Flow
Can be achieved... Via a single design representation
covering all design steps equally Via one-code paradigm Via refinement steps Via closing the tool gap...
![Page 28: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/28.jpg)
slide 29Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Open Tool Integration Environment (OTIE)
![Page 29: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/29.jpg)
slide 30Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Design Database (DBB) Internal View
For static code analysis property tables, process table, and basic block tablesof the DDB are used.
Process
BasicBlockProperty
Alias
BasicBlock
Instance has
has
has
has
hierarchy
Module
realized by
BasicBlockConnection
connectedby
DataFlowElement
consistsof
DataFlowAttribute
specifiedby
DataFlowConnection
connectedby
ProcessProperty
has
Data
has
has
Structure
Code
Properties
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slide 31Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Automatic HW/SW Partitioning Example
Correlation
CCGSCG
SqrAndSum
PeakDetection
NonCohAccu
CoherentAccu
PathProfiling
Finger Placement
Inputs, I,Q,Parameters
Delay Profile Estimator (a UMTS receiver component)
Cost = ρ CostCC + (1- ρ) CostGC
ρ = 0.68 .. 0.7
We basically achieved the same resultas well-trained design groupWe needed about 6 seconds!
Process HW(M)
SW(M)
HW(A)
SW(A)
SCG X X
CCG X X
Correlation X X
CoherentAccu
X X
SqrAndSum X X
NonCohAccu X X
PeakDetection
X X
PathProfiling X X
FingerPlacem.
X X
![Page 31: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/31.jpg)
slide 32Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Outline Why Mobile Communications?
Problems in the Design of Wireless Systems Complexity Gap Design Productivity Gap
Problems and Solutions Parallelism, IP-Reuse, Predictive Design Inconsistent Design, Lack of Tool Support, Refinement Techniques,
Design Languages, Automatic HW/SW Partitioning Virtual Prototyping, Automatic Testing and Verification, Automatic Float
to Fix Conversion Static Code Analysis, automatic DFG and CFG Generation, Code
Understanding and Interpretation Low Power and Power aware Designs
Software Defined Radio Conclusions
![Page 32: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/32.jpg)
slide 33Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Virtual Prototyping (1)
Algorithmic DesignArchitectural DesignHW RealisationSW ImplementationFW Development
Algorithmic DesignArchitectural DesignVP ImplementationHW RealisationSW ImplementationFW Development
Algorithmic DesignArchitectural DesignVP ImplementationHW RealisationSW ImplementationFW Development
![Page 33: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/33.jpg)
slide 34Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
VPHW
Virtual Prototype: Whole system behavior can be tested via
simulation but not as fast as having a prototype available
After HW is available, VP can be replaced
Virtual Prototyping (2)
SW/FWHW/SW Interface
![Page 34: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/34.jpg)
slide 35Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Supporting Platform Based Designs in VP
DMA
HA1
DSP
HA2
RAM
. .
.
Systembus
Direct I/O
. .
.
![Page 35: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/35.jpg)
slide 36Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Automatic VP Generation Environment
COSSAP Project
W X
Y
Z
*.gc v_arc v_ent
Fileset
System Description
Interface (SDI)for
COSSAP
DesignDataBase (DDB)
HW/SWpartitioninginformation
table
VPG
Bus Interface
B
AC
Scheduler
VP components forW,X,Y,Z
COSSAP-Guidelines
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slide 37Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Results of Industrial Deployment
Component Structural Functional Total
DPE 8 25 33
SYNC 17 39 56
DUD 12 43 55
Design effort for manual VP creation
Total = 144 person-hours
[Person-hours]
A matter of seconds!!!
![Page 37: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/37.jpg)
slide 38Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Verification (1)
Today, about 70% of development time is verification
![Page 38: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/38.jpg)
slide 39Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Verification (2)
With such high complexity, a complete verification on every level is not possible!
The higher the design level, the faster the simulation time Run all but one module (DUT) on highest
possible design levels. Generate test vectors automatically for
all design levels.
![Page 39: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/39.jpg)
slide 40Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Automatic Test Pattern Reuse
DSP
C testprogram
DMA
Memory
Bus
HA1 HA2…
Registers
Memory image
Direct I/O
![Page 40: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/40.jpg)
slide 42Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Float/Fixed Conversion Environment
SSD
SDIFloat
Evaluation
Generation
Hybrid OptimisationSSD
![Page 41: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/41.jpg)
slide 43Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Float to Fix Conversion Results
{8,16,32} {16}
![Page 42: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/42.jpg)
slide 44Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Float to Fix Conversion Results
![Page 43: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/43.jpg)
slide 45Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Outline Why Mobile Communications?
Problems in the Design of Wireless Systems Complexity Gap Design Productivity Gap
Problems and Solutions Parallelism, IP-Reuse, Predictive Design Inconsistent Design, Lack of Tool Support, Refinement Techniques,
Design Languages, Automatic HW/SW Partitioning Virtual Prototyping, Automatic Testing and Verification, Automatic Float
to Fix Conversion Static Code Analysis, automatic DFG and CFG Generation, Code
Understanding and Interpretation Low Power and Power aware Designs
Software Defined Radio Conclusions
![Page 44: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/44.jpg)
slide 46Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Process Graph RepresentationProcess (CFG)
Process is represented as CFG One Basic Block consists of a DFG
Basic Block (DFG)
+
*
a b c
z
BB1
BB4
BB5
BB3
BB2
![Page 45: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/45.jpg)
slide 47Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Control Flow Graph of an FIR Filter
![Page 46: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/46.jpg)
slide 48Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
CFG Example
E.g. function of aDelay Profile Estimator
Basic Blocks and function are annotated with properties
Operations +,-,* Control if, jmp Loop counter
![Page 47: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/47.jpg)
slide 49Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Power Aware Design
SYSTEM LEVEL
BEHAVIORAL LEVEL
RT LEVEL
LOGIC LEVEL
TRANSISTOR LEVEL
LAYOUT LEVEL
7 - 20X
2 – 5X
20 – 50 %
POWER REDUCTION OPPORTUNITIES
![Page 48: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/48.jpg)
slide 50Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Power Reduction Dynamic Methods
Sleep modes Dynamic frequency scaling (DFS) Dynamic voltage scaling (DVS)
Reducing Switching Activity Clock gating Minimization of glitches Reducing number of operations
Adapting Process Technology Reducing capacitance Reducing leakage current Reducing supply voltage
![Page 49: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/49.jpg)
slide 51Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Outline Why Mobile Communications?
Problems in the Design of Wireless Systems Complexity Gap Design Productivity Gap
Problems and Solutions Parallelism, IP-Reuse, Predictive Design Inconsistent Design, Lack of Tool Support, Refinement Techniques,
Design Languages, Automatic HW/SW Partitioning Virtual Prototyping, Automatic Testing and Verification, Automatic Float
to Fix Conversion Static Code Analysis, automatic DFG and CFG Generation, Code
Understanding and Interpretation Low Power and Power aware Designs
Software Defined Radio Conclusions
![Page 50: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/50.jpg)
slide 52Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Software Defined Radio
What is the next step in direction automatic chip design?
Software design is cheaper than Hardware design (also faster).
Why not designing a new and very flexible HW platform, so flexible that algorithmic descriptions can directly be run on it runtime reconfigurable HW?
![Page 51: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/51.jpg)
slide 53Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Software Defined Radio
Channel RF access
(front-end)
IF processing
BasebandModem
Processing
Bitstreamprocessin
g
InformationSecurity
DataInterface
Speech CODEC &Interface
Joint Control
Man Machine Interface
![Page 52: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/52.jpg)
slide 54Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Software Defined Radio
RF front-end in software form? Yes, in FM receiver for cars (100MHz) No, for low power
Fascinating Research topic for the coming years!
![Page 53: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/53.jpg)
slide 55Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Software Defined Radio
One platform could support many different standards like GSM,UMTS,WLAN, Bluetooth, UWB…
New standards would simply require a software download and then the terminal would already work…
![Page 54: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/54.jpg)
slide 56Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Benefits SDR Manufacturer‘s view:
Concentrate R&D on smaller HW platform Applicable to every cellular system Spread development cost not over one product but entire product
family. Mass production at lower costs, SW can be updated/debugged in
steps Operator‘s view:
New services can be implemented later Differentiation from other operators All services available regardless of standards Multi-standard base stations
User‘s view: Roaming in every cellular system Personal terminal configuration Increased HW lifetime
![Page 55: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/55.jpg)
slide 57Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Software Defined Radio
Activity already in this direction by www.sdrforum.org A forum to support Open Architecture
Reconfigurable Wireless Technology With more than 130 members
However, after some years of visionary ideas, now mode of practical applications…
![Page 56: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/56.jpg)
slide 58Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Software Defined Radio SCA: Software Communication Architecture
developed by Communication Research centre Canada (CRC), HarrisCorporation and supported by SDR-Forum
Open architecture Java (CRC) , C++ (Harris) based Experimental RTOS von Wind River (Posix compliant) The SCA can be seen as an operating environment responsible for
deploying and interconnecting the signal processing objects of an SDR. Standardization started 2002.
Start-ups for flexible HW structures Need to be power aware Need to be reprogrammed quickly RTOS for HW?
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slide 59Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Conclusions Gap between algorithmic demands and
design productivity increases. Not one tool suite from one vendor will
be the single solution for an efficient design flow.
A new design flow environment has to make manual tasks automatic has to provide the flexibility for the user to
incorporate new tools, and has to give the freedom to adapt the flow to
his specific needs. SDR technology emerges…
![Page 58: The Chip Design Crisis](https://reader035.fdocuments.in/reader035/viewer/2022081420/568134c4550346895d9be7a3/html5/thumbnails/58.jpg)
slide 60Christian Doppler Laboratory
for Design Methodology of
Signal Processing Algorithms
Contacts
Markus Rupp: [email protected]
Link: http://www.nt.tuwien.ac.at/cdlab/
Diplom- und Forschungsarbeiten mit Hintergrundwissen in: Compilerbau, XML, Graphentheorie, nichtlineare Optimierung, Datenbanken, Java…