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The Characteristics and Simulations of The Characteristics and Simulations of Si/SiGe Heterojunction at Strained-Si Si/SiGe Heterojunction at Strained-Si

DevicesDevices

指導教授：劉致為 博士學生：魏潔瑩

台灣大學電子工程學研究所

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OutlineOutline

• Introduction

• Introduction to Si-based Heterostructure

• Device Fabrication

• Simulation and Result Discussion

• Conclusion

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How much more scaling is left?

• New technology generation introduced every 3 or 2 years. (0.18um, 0.13um, 90nm,.… )

• Scaling improves cost and performance-- leading to new applications and growth.

•Question:Question:

Technology ScalingTechnology Scaling

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Smaller FET Needs Thinner Gate OxidesSmaller FET Needs Thinner Gate OxidesThe conduction channel must be controlled by the gate, not byThe drain. As L is reduced, drain-to-channel capacitance increases.Therefore, gate-to-channel capacitance must also be raised,i.e., oxide must be thinner.

1975: 100nm, 2003: 1.2nm. How much thinner can it get?

Gate

Oxide

Source Drain

Cg

Cd

L

Ref [1]

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12Å Gate Oxide -- 3 SiO12Å Gate Oxide -- 3 SiO2 2 molecules thickmolecules thick

Ref [1]

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High-k Dielectrics Reduce Gate High-k Dielectrics Reduce Gate LeakageLeakage

1.E-08

1.E-06

1.E-04

1.E-02

1.E+00

1.E+02

1.0

Jg (

A/c

m2 )

1.5 2.0 2.5

Effect Oxide Thickness (nm)

Jg reduction > 6 orders

SiO2

High-k Dielectric

High-kDielectric

Gate

Ref [1]

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II mobility x charge mobility x charge = mobility x ( V-V = mobility x ( V-Vt t ) / T) / Toxox

• In order to reduce power use, V is reduced and Vt and Tox are kept large. Unfortunately, I drops.

• Large I is needed to keep circuit speed high.

• What is needed : high mobility material

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OutlineOutline

• Introduction

• Introduction to Si-based Heterostructure

• Device Fabrication

• Simulation and Result Discussion

• Conclusion

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Lattice Structure and Heterostructures Lattice Structure and Heterostructures

Ref [2]

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Strained Silicon TransistorStrained Silicon Transistor

Tensile strain can

increase silicon electron

holes mobilities.

Need strained silicon film

with low defect density at

low cost.

Strained Si

Si1-x Gex

Si

Graded SiGeRegion

Si Substrate

RelaxedSiGe

20nmStrained Si

Ref [1]

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The Effect of Strain on Si The Effect of Strain on Si Conduction BandConduction Band

Ref [2]

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Band Alignment between Si and Band Alignment between Si and SiSi0.70.7GeGe0.3 0.3

1% Ge = 6meV for CB and VB

Ref [3]

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Effective Mobility of Strained-SiEffective Mobility of Strained-Si

μ= eτ/ m*

τ= scattering time constant

m*=effective mass

65% enhancementat 1.0 MV/cm

Ref [4]

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OutlineOutline

• Introduction

• Introduction to Si-based Heterostructure

• Device Fabrication

• Simulation and Result Discussion

• Conclusion

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The Structure of the surface-channel The Structure of the surface-channel Strained-Si n-MOSFETStrained-Si n-MOSFET

• 0.8 μm design rule

• 100 mm-wafer line

• ~1 μm graded SiGe buffer layer

• ~1 μm uniform relaxed Si0.8Ge0.2

• 12-24nm strained layer thickness

are grown by UHV/CVD

• 20 nm LTO as gate oxide

• Dit = 1E11 cm-2eV-1

Ref [5]

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OutlineOutline

• Introduction

• Introduction to Si-based Heterostructure

• Device Fabrication

• Simulation and Result Discussion

• Conclusion

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ParametersParameters

• χSS = 4.05 + 0.6x• Eg,SS = 1.12 - 0.4x• εr, SS = 11.8• χSiGe = 4.05• Eg,SiGe = 1.12 - 0.4x• εr, SiGe = 11.8 + 4.2x x : Ge content, χ: affinity, Eg : bandgap energy, SS : strained-Si

Simulator: ISE TCAD 8.5 DESSIS

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Structure and Band Diagram of Structure and Band Diagram of Strained-Si/SiGe/Si MOS CapacitorStrained-Si/SiGe/Si MOS Capacitor

Al

oxide 20 nm

strained-Si

relaxed-Si1-xGex

1000 nm

graded-Si1-xGex

1000 nm

Si substrate

VG

GND

EV EC

Not to Scale

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Simulated Band Diagrams for Simulated Band Diagrams for Different Gate BiasesDifferent Gate Biases

0.00 0.01 0.02 0.03 0.04 0.05-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

EF- pinning

(a)

VG= -2V

VG= -1V

NMOS capacitor

EF

Ener

gy [e

V]

Depth [um]0.00 0.01 0.02 0.03 0.04 0.05

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

(b)

VG= 0V

VG= -0.5V

PMOS capacitor

EF

Ener

gy [e

V]

Depth [um]

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Measured and Simulated Measured and Simulated Quasi Static C-V CharacteristicsQuasi Static C-V Characteristics

-5 -4 -3 -2 -1 0 1 2 3 4

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1(a)

Ge=20%

NMOS capacitor

C/Co

x

VG [V]

fitting data

-5 -4 -3 -2 -1 0 1 2 3 4

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1(b)

PMOS capacitor

Ge=20%

C/Co

x

VG[V]

fitting data

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Measured NMOS Capacitor C-V wiMeasured NMOS Capacitor C-V with Different Strained-Si Thicknessth Different Strained-Si Thickness

-2 -1 0 1 260.0n

80.0n

100.0n

120.0nNMOS capacitor

Strained-Sithickness

12 nm 18 nm 24 nm

Cap

acit

an

ce [

F/c

m2 ]

VG [V]

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Simulated NMOS Capacitor C-V wiSimulated NMOS Capacitor C-V with Different Strained-Si Thicknessth Different Strained-Si Thickness

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.50.4

0.5

0.6

0.7

0.8

0.9

1.0

NMOS capacitor

C

/Co

x

VG

[V]

tsi = 10nm

tsi = 20nm

tsi = 30nm

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Simulated NMOS Capacitor C-V as Simulated NMOS Capacitor C-V as A Function of Ge Content A Function of Ge Content

-4 -3 -2 -1 0

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1NMOS capacitor

C

/Co

x

VGS

[V]

Ge=10% Ge=20% Ge=30%

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Simulated Energy Band Diagram for DiffeSimulated Energy Band Diagram for Different Ge Content in PMOS Capacitorrent Ge Content in PMOS Capacitor

0.00 0.01 0.02 0.03 0.04 0.05-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

VG = -1V

EF

PMOS capacitor

E

ner

gy

[eV

]

Depth [um]

Ge = 30% Ge = 20%

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Hole Density Ratio in Strained-Si Hole Density Ratio in Strained-Si

10 15 20 25 30 35 4010-1

100

101

102

103

104

105

106

10710 15 20 25 30 35 40

VG-V

T= -1V

tSi with Ge=20%

Ge with tsi=20nm

nFET

pFET

VG-V

T=1V

strained-Si thickness [nm]

s

urf

ac

e /

bu

rie

d c

ha

nn

el

ho

le d

en

sit

y r

ati

o

Ge [%] in the relaxed SiGe

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Asymmetric Strain Asymmetric Strain

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Simulated Current Enhancement in Simulated Current Enhancement in Asymmetric Strain Asymmetric Strain

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.50.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05Asymmetric strain

cu

rren

t en

han

cem

ent(

rati

o)

Vd

2_region(30,10)

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OutlineOutline

• Introduction

• Introduction to Si-based Heterostructure

• Device Fabrication

• Simulation and Result Discussion

• Conclusion

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ConclusionConclusion

• Due to Fermi level pinning effect, the C-V characteristics in NMOS capacitor exhibits a more obvious plateau than in PMOS capacitor.

• Less Ge content and larger strained layer thickness must be chosen to sustain enough great inversion hole density ratios in strained-Si pMOSFET.

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• Since more strain and thinner strained layer are taken to keep mobility enhancement, the compromise must be made.

• Modeling of hole confinement on the C-V characteristics in strained-Si must be investigated.

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ReferenceReference

[1] Chenming Hu, IEDMS 2002 presentation.[2] Kern Rim, Ph. D. dissertation 1999.[3] J. J. Welser, Ph. D. dissertation 1994.[4] M. H. Lee et al., “Comprehensive Low-Fre

guency and RF Noise Characteristics in Strained-Si NMOSFETs”, IEDM 2003.

[5] C. C. Lee et al., ”The effects of mobility and saturation velocity on deep submicron strained Si NMOSFETs,” IDEMS, 2002.