Ch. 2 Lecture Slides for Chenming Hu book: Modern Semiconductor Devices for ICs
The Changing IC Devices - ISQED · Introduced a New Scaling Rule . Chenming Hu, March 2013 ....
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The Changing IC Devices Chenming Hu University of California Berkeley http://www.eecs.berkeley.edu/~hu/ ISQED 2013 Santa Clara, CA
Transcript of The Changing IC Devices - ISQED · Introduced a New Scaling Rule . Chenming Hu, March 2013 ....
The Changing IC Devices
Chenming Hu University of California Berkeley
http://www.eecs.berkeley.edu/~hu/ISQED 2013Santa Clara, CA
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May 4, 2011 Exclusive News The New York Times Front Page
• Intel will use 3D FinFET at 22nm
• Most radical change in 4 decades
• There is a competing SOI technology
Chenming Hu, March 2013 2
Long Channel Transistor
Chenming Hu, March 2013
Gate
Source Drain
Oxide Cg
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Short Channel – Problem
Chenming Hu, October 2012
MOSFET becomes “resistor” at small L.
Gate
Source Drain
Oxide Cg
Cd
Making Oxide Thin is Not Enough
Chenming Hu, March 2013
Gate
Source Drain
Leakage Path
Gate cannot control the leakage current paths that are far from the gate.
C.Hu, “Modern Semicon. Devices for ICs” 2010, Pearson
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A Structure without Si Far from Gate
Thin body controlled by multiple gates.
Chenming Hu, March 2013
Gate
Gate
Source Drain
FinFET body is a thin Fin.
N. Lindert et al., DRC paper II.A.6, 2001
Gate Length
Sour
ce
Dra
in
Fin Width Fin Height
Gate Length
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40nm FinFET – 1999
Chenming Hu, March 2013
30nm Fin allows 2.7nm SiO2 & undoped body ridding random dopant fluctuation.
66mV/dec
X. Huang et al., IEDM, p. 67, 1999 7
Introduced a New Scaling Rule
Chenming Hu, March 2013
Leakage is well suppressed if Fin thickness < Lg
10nm Lg AMD
2002 IEDM
5nm Lg TSMC
2004 VLSI
3nm Lg KAIST
2006 VLSI
Silicon fin
Poly-si Gate
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STI
Gate
SiSTISTI
Gate
SiSTI
Two Improvements Since 1999
Chenming Hu, March 2013
• 2002 FinFET with thin oxide on fin top. F.L.Yang et al. (TSMC) 2002 IEDM, p. 225. • 2003 FinFET on bulk substrate. T. Park et al. (Samsung) 2003 VLSI Symp. p. 135.
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D
Planar FET
Si Si
FinFET
20nm FinFET
Chenming Hu, March 2013
C.C. Wu et al., 2010 IEDM
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D
Planar FET
Si Si
FinFET
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BSIM
• Berkeley Short-channel IGFET Model
• First industry standard SPICE model for IC simulation
• Used by hundreds of companies for IC design since 1997
• BSIM FinFET model became industry standard in March 2012
Chenming Hu, March 2013
It’s Free 11
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Y-K. Choi, IEEE EDL, p. 254, 2000
Another Structure
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Ultra-Thin-Body FET (UTB-FET)
with no Si far from the gate
SiO2
Si
UTB Source Drain
Gate
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2001 UTB-FET
Chenming Hu, March 2013
3nm Silicon Body, Raised S/D
Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001 15
2009 20nm UTB-FET using 5nm-Body
Chenming Hu, March 2013
K. Cheng et al, IEDM, 2009
Other Names: • FDSOI • UTBB
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Outlook
Chenming Hu, March 2013
Intel uses it at 22nm and foundries at 14nm or sooner FinFET
ST uses UTB-FET at 28nm, 20nm… against regular CMOS UTB-FET
Competition will bring out the best of both.
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Chenming Hu, March 2013
WSe2 UTB-FET
H. Fang et al., Nano Lett., Vol 12, 3788 (2012)
60mV/decade experimentally demonstrated
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• How to reduce Vdd to 0.1V?
• Need a new transistor turning on/off with 0.1V change in Vg.
e.g. Tunneling Transistor
Chenming Hu, March 2013
P = f C V2
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Scale Vdd by Scaling Eg - Simulation
C. Hu, 2008 VLSI-TSA, p.14, April, 2008
Chenming Hu, March 2013
1E - 11
1E - 10
1E - 09
1E - 08
1E - 07
1E - 06
1E - 05
1E - 04
1E - 03
1E - 02
0.0 0.2 0.4 0.6 0.8 1.0
Eg=0.36eV Eg=0.69eV
Eg=1.1eV
Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS
Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS
Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS
Gate Voltage, VGS (V)
I D /
µm
Lg=40nm
µA
mA
nA
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Must: Thin body thickness/diameter < αLg
Want: High mobility + low contact resistance Future Must: 2D-crystal semiconductor for 3D IC,
e.g., graphene, MoS2, WSe2... (WSe2 UTB with 60mV/dec: Fang, Javey,.., Nanolett., 2012) Future Must: 100mV Vdd, e.g., TFET, Negative
Capacitance FET (Salahudin,..,Nanolett., 2008) ,…
Chenming Hu, March 2013
FinFET UTB Pillar/nano-Wire
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Gradually Add New Technologies
1. FinFET, UTB, Pillar structure 2. 1 + SiGe/III-V 3. 2 + 0.1V TFET 4. 3 + 2D-crystal materials for true 3D ICs
using deposited stacks of semiconductor, dielectric, metal, e.g., MoS2/BN/grapheen
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Summary
• Ultra thin body allows device scaling beyond 10nm. • 2D-crystal semiconductors are the ultimate UTB-FET materials, great for 3D IC. • A new transistor will enable 0.1V IC in the 2020’s.
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