The Bridge Between Semiconductor Design and Manufacturing · Common HSPICE modeling in FastSPICE...

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Standard SPICE ModelsThe Bridge Between Semiconductor

Design and Manufacturing

Hany ElhakJune 2, 2014


Agenda

Overview: Standard SPICE models

Model development and qualification

Compact model support in Synopsys simulators


SPICE Models in the Chip Design Flow

• The contract on transistor behavior between the foundry and its customer• Used by SPICE simulators to analyze foundation libraries and analog IP• The basis of timing, noise and power models used in digital implementation

SPICEModel

SynthesisPlace & route

Sign-off(STA, SI)

Fabless Semiconductor CompanyFoundry

GDSIIFabrication

Device Modeling

Library Characterization

SPICE Simulation

Liberty timing, noise, power

Digital Implementation

Custom Design


SPICE Models in Advanced Nodes• Layout-dependent effects

– Well Proximity effect– Length of Diffusion (LOD)– Poly Spacing Effect (PSE)– OD to OD Spacing effect (OSE)

• Mechanical stress– Dual stress liners (SiN)– Stress memorization– Embedded SiGe

• Random variation/local mismatch– Random dopant fluctuation– Line-edge roughness

• MOS aging (HCI, BTI)

• Self heating

Models # Lines of codeBSIM4 ~27,000BSIM-CMG ~41,000


Standard Models Save Design Costs

• In the past SPICE simulators supported proprietary models – e.g. HSPICE Level 28

• The cost of library and IP qualification increase with feature size reduction

• Foundries save costs by qualifying standard models

• Designers are free to use the best tool for the job

0

50

100

150

200

250

Cost ($

M)

Cost of Technology Participation *

Library development Library qualificationBasic IP development Basic IP qualification

* Source: IBS, August 2013


Examples of Standard SPICE Models

BSIM3 HiSIM_HV

MOSVAR

MOSFET:

BSIM4

PSP

HiSIM

BSIMSOI

HiSIM_SOI

MEXTRAM

HICUMBSIM-CMG

DIODE

FinFET:

SOI:

BJT:

LDMOS:

Other:

R2, R3


Model Development and Qualification


SPICE Model Ecosystem

HSPICE

UniversityModel

development

EDAImplementationOptimization

FoundryModel extraction& qualification

Fabless Design

CMC


\

Types of SPICE Models

• Numerical models– Carrier transport equation– TCAD– Too slow for SPICE

• Table models– Tables for device behavior vs.

device size, bias and temp.– Used in FastSPICE

• Compact models – Balance between physical

detail and computational efficiency (compactness)

XG

Cgd,ov

Ies Ied

XS XD

IG

MG

Rs Rd

Rgeltd

Rii

ISID

IgbIds

Igs IgcsIgdIgcd

Igisl

Igidl+Iii

Cgs,ov

Cge,ov

Cgs,f Cgd,f

Cds,f

Process simulationDevice Physics

Circuit simulationDevice behavior


SPICE Model Development in Academia

• Compact model equations:– Current– Charge– Conductance– Capacitance

• Development steps– Examine device behavior– Compact model formulation– Model execution– Silicon data fitting

Source: Mohan Vamsi Dunga,, UC Berkeley 2008


SPICE Model Implementation in EDA

1.9

3.6

6.6

1X

3X

5X

7X

1 2 4 8CPU Cores

Improved BSIM-CMG Scalability *

• Model implementation– Convert Verilog-A models to C language– Numerical efficiency and robustness

• Model optimization– Evaluation speed– Memory footprint– Multi-threading

• Layout and process awareness– TMI2 jointly developed by Synopsys & TSMC– One infrastructure for layout depended effects,

statistical modeling, aging/self-heating … etc.

BerkeleyBSIM-CMG

0

10

20

30

40

2012.06-SP2 2013.03 2013.12

Tim

e pe

r ite

ratio

n (u

s)

Improved BSIM-CMG model evaluation time *

* Data is based on HSPICE model regression suite for TSMC 16nm


Simulation Stages Transient flow

eval_transistor(){

if (allow_limiting)call limiting function();

Eval_function(){

get device biases

Calculate individual I,Q,G,C

stamping: sum up individual I,Q,G,C

}}

start

readin

initialization

element list

op

transient

end

@ each time pointfor each NR iteration

convergence check if (converged){

check LTE for time step rejection and next step size prediction

}

device info

Device evaluation

V, TV, T

I/Q/G/CI/Q/G/C

for each device

factor and solve Jacobianupdate voltages

Gather/predict terminal voltagesCall eval_transistorscatter I,Q,G,C

Mod

el A

PI

Typical Device Operation in SPICE

Total


Model Qualification by Foundry and EDA

Model Libs

Corners

Variations

LDE

RDR

.Model cards

Modeled Device Char

Model equation

• Current (I)

• Charge (Q)

• Conductance (G)

• Capacitance (C)

Circuit Analyses

• OP/DC

• Tran

• AC/noise

• Monte Carlo

• HF/RF

• Accurate• Scalable• Robust

• Accurate• Robust• Efficient


Automatic Testing of Models – ATOM Test case generation, model QA, and simulator regression

ModelTopologiesParameters

SimulatorOptions

Unit/ckttemplates

Test Cases

Distribution to computer farms

Simulations and output (Reference and target)

Reports(Text/Measurement)

Code, parameter, and flow debug & fix

Next run

Pass/Fail check with pre-specified criteria

Unit test P/V/T sweeping All instance parameters All model parameters Parameter range checking All topologies NFIN, TFIN, HFIN, NF, M, and DTEMP MT thread safety

Analysis type: OP/DC/AC/Tran/Noise/PZ/MC Output templates GMIN and GMINDC 3rd-party formats Simulator specificsPerformance and memory


Model Support in Synopsys Simulators


Synopsys Circuit Simulation Solutions

• HSPICE – Best Silicon Correlated SPICE Trusted reference at all top foundries

• CustomSim - Post-layout FastSPICE Performance Primary simulator at 10 of top 10 semiconductor

• FineSim - Scalable multi-CPU SPICE & FastSPICE Primary simulator at top DRAM and Flash memory

• VCS AMS –Fastest Engines + AMS Testbench Deployed at top processor and SoC companies

Giga-scalePrecision

HSPICE

Performance

CustomSim

FineSim

VCS® AMSVCS® AMS

CustomSimCustomSimVCS


HSPICE - Best in Silicon Correlation

Comprehensive ModelsGolden Reference

• Used by foundries to qualify models for new processes• The Reference circuit simulator for 5 out 5 top foundries!

Foundry HSPICE

TSMC GLOBALFOUNDRIES Samsung UMC SMIC

Device Type Models SupportMOS BSIM,PSP, HiSIM …

FinFET BSIM-CMG …

High Voltage HVMOS, HiSIM HV

SOI BSIMSOI, UTSOI …

Bipolar VBIC, HICUM …

LCD RPI-TFT …

Foundry Models TMI2 …


FineSimCustomSim

Shared Technology

Common HSPICE modeling in FastSPICE

• HSPICE Models built into CustomSim and FineSim

• 1st in model availability– Synchronized with HSPICE

• Quality– Consistent model quality– Correlation to HSPICE

• 3rd party model interface

HSPICE Modeling Engine

HSPICE Modeling Interface

2013.122x faster

2013.122x faster


• TSMC certifies HSPICE, CustomSim and FineSim for 16nm– FinFET device modeling and

accurate circuit simulation for the latest FinFET-based designs

• New capabilities for CustomSim Electro-Migration and IR-Drop Analysis

Production Ready for 16 nmHSPICE, FineSim, CustomSim Certified


Summary

• SPICE models are “the contract” on transistor behavior between the foundry and the fabless chip company

• Standard compact models save time and cost

• Universities, EDA companies and foundries collaborate to develop, implement and qualify compact models

• HSPICE, the golden reference of SPICE simulation supports all standard compact models

• All Synopsys simulators share HSPICE models to ensure best Silicon correlation


See More Synopsys AMS at DAC

• Demonstrations– Custom Design Solution

Monday 4-5 PMTuesday 10-11 AM, 4-5 PMWednesday 10-11 AM, 2-3 PM

Synopsys Booth

• Presentations– Standard SPICE models: the bridge between

semiconductor design and manufacturingMonday 4:00-4:30 PM SI2 Booth

– Accelerating mixed-signal verification of FinFET-based designs

Tuesday 4:30-5:00 PM TSMC OIP Theatre

Register at the Synopsys Booth

• AMS Luncheon– Complex Mixed-Signal SoCs: How to Conquer

the Next Verification Frontier Monday, June 2, 2014 11:30 a.m. to 1:30 p.m. San Francisco Westin Hotel, Market Street, Metropolitan III Ballroom

• Custom Design Luncheon– Innovations in Custom Design

Tuesday, June 3, 2014 11:30 a.m. to 1:30 p.m. San Francisco Westin Hotel, Market Street, Metropolitan III Ballroom


Thank You

The Bridge Between Semiconductor Design and Manufacturing · Common HSPICE modeling in FastSPICE...

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