The AMD Athlon™ Processor:Future Directions

Fred WeberFred Weber

Vice President, EngineeringVice President, Engineering

Computation Products GroupComputation Products Group

AG

P

PC

I

DR

AM

System Logic

Forward Clocks

AMD Athlon™ Processor

L2 CACHE

Snoops/

SysC

MD

Requests

DA

TA

72

b

AMD Athlon™ Processor

L2 CACHE

Snoops/

SysC

MD

Requests

DA

TA

72

b

Workstation & Server Capabilities 200 MHz FSB (1.6GB/sec) 200 MHz FSB (1.6GB/sec)

that can scale to 400 MHz that can scale to 400 MHz (3.2GB/sec) per processor(3.2GB/sec) per processor

Backside L2 Cache Backside L2 Cache interface supports up to interface supports up to 8MB8MB

Up to 24 Outstanding Up to 24 Outstanding Transactions per ProcessorTransactions per Processor

13-Pin Address Bus13-Pin Address Bus

13-Pin Snoop Bus13-Pin Snoop Bus

72-Pin Data Bus w/ ECC72-Pin Data Bus w/ ECC

Scales to 43-bit Physical Scales to 43-bit Physical AddressAddress

Processor ScalabilityProcessor Scalability 1MB and 2MB Full Speed, 16-way associative L2 Cache1MB and 2MB Full Speed, 16-way associative L2 Cache

266MHz Front Side Bus266MHz Front Side Bus

System Scalability: 2-way; 4 to 8 way multiprocessingSystem Scalability: 2-way; 4 to 8 way multiprocessing AMD: 2 processor designAMD: 2 processor design

266MHz Front Side Bus with DDR DRAM (PC-2100266MHz Front Side Bus with DDR DRAM (PC-2100™ ™ ))

4X AGP-Pro, PCI 66/644X AGP-Pro, PCI 66/64

Multi-way: Infrastructure development underway (API and HotRail)Multi-way: Infrastructure development underway (API and HotRail)

ReliabilityReliability ECC Protected L2 Cache, DRAM and Front Side BusECC Protected L2 Cache, DRAM and Front Side Bus

Execution Signature GenerationExecution Signature Generation

Product Features In 2000

LDTLDT

The System Bus The System Bus

of the Futureof the Future

AMD’s System Bus Initiative:Lightning Data Transport (LDT)

GoalsGoals Simplify design and flexibility with a single data link for “in-Simplify design and flexibility with a single data link for “in-

chassis” connection to I/O, multi-processing and co-chassis” connection to I/O, multi-processing and co-processorsprocessors

Improve system performance with increased I/O Improve system performance with increased I/O performance and scalable bandwidthperformance and scalable bandwidth

Enable flexibility of system I/O technologies through a Enable flexibility of system I/O technologies through a modular bridge architecturemodular bridge architecture

Complement externally visible bus standardsComplement externally visible bus standards

AMD’s LDT: I/O

I/O can be daisy chainedI/O can be daisy chained Multiple bridges on a single Multiple bridges on a single

I/O link I/O link Multiple “pass through” Multiple “pass through”

devices can be devices can be interconnectedinterconnected

Bridges are independent Bridges are independent (reusable for many (reusable for many designs)designs)

The System I/O SANIC The System I/O SANIC (HCA) is independent of (HCA) is independent of the memory controllerthe memory controller

PCI 33/32

SIOSANIC

LDT

DRAM

AMD Athlon™ AMD Athlon™

EV6 Bus

North Bridge AGP

PCI 66/64PCI-X

SouthbridgePCI 66/64PCI-X

AMD’s LDT: Multiprocessing

Coherent link provides Coherent link provides scalable multiprocessingscalable multiprocessing

Memory capacity scalesMemory capacity scales

Memory bandwidth scalesMemory bandwidth scales

I/O capacity scalesI/O capacity scales

I/O bandwidth scalesI/O bandwidth scales

LDT

AMD Athlon™

EV6 Bus

North Bridge

AMD Athlon™

AMD Athlon™

EV6 Bus

North Bridge

AMD Athlon™

AMD Athlon™

EV6 Bus

AMD Athlon™

AMD Athlon™

EV6 Bus

AMD Athlon™

Multiple LDT System Links (I/O)

Multiple LDT System Links (I/O)

DRAMDRAM

DRAM North Bridge DRAMNorth Bridge

LDT Features

Unidirectional point-to-point links in each directionUnidirectional point-to-point links in each direction Differential signaling with source synchronous clock forwardingDifferential signaling with source synchronous clock forwarding

Variable widths negotiated at initializationVariable widths negotiated at initialization Upstream and downstream links can be of different sizeUpstream and downstream links can be of different size

16/16-bit link provides 6.4 GB/sec each way16/16-bit link provides 6.4 GB/sec each way Multiple logical channels in each linkMultiple logical channels in each link

Guaranteed isochronous bandwidthGuaranteed isochronous bandwidth

In-band system management and legacy signal transportIn-band system management and legacy signal transport PCI like configuration mechanismPCI like configuration mechanism

Up to 1.6 Gbits/sec per pin

Isochronous Transfer Receive Priority to ensure They Arrive On Time

CtrlClk

CtrlClk

8, 16 or 32 - bitsin each direction