Testing of logic arrayes to be programmed

Levels of abstraction

While I>k then ..

ROM

ALU

RAM

&

&1

Behaviouralmodel

Functionalmodel

Logic level model

Electric level modell

Geometric model

Leve

l of a

bstra

ctio

n in

crea

ses

Abi

lity

to lo

calis

e/di

scov

er a

n er

ror i

ncre

ases

Tests (stimula) can be generated at the level wherethe hardware to be realised is described. Usually it is possible to use either logical, functional or behavioural level model.

Boundary Scan

TI

TO

Elements of memory (triggers)

All larger arrays (FPGA; CPLD) have boundary scan hardware support that corresponds to IEEE 1149.1 standard

The concept of boundary scanning

There are triggers between the logic and each output of every microcircuit within the system. It is possible to connect the triggers into a single shift register. Thus it is possible to test each microcircuit separately, of course, in a specialised mode.

BoundaryScan Cell

MUX

S1

0

ShiftDR

Scan In(SI)

TD TD

MUX

S1

0

Mode

Data Out(PO)

ClockDR UpdateDR

Shift RegisterParallel OutputRegister

Scan Out(SO)Data In

(PI)

Modes of Boundary Scan Cell I

MUX

S1

0

ShiftDR

Scan In(SI)

TD TD

MUX

S1

0

Mode

Data Out(PO)

ClockDR UpdateDR

Shift RegisterParallel OutputRegister

Scan Out(SO)Data In

(PI)

MUX

S1

0

ShiftDR

Scan In(SI)

TD TD

MUX

S1

0

Mode

Data Out(PO)

ClockDR UpdateDR

Shift RegisterParallel OutputRegister

Scan Out(SO)Data In

(PI)

Normal Mode

Update Mode

Modes of Boundary Scan Cell II

MUX

S1

0

ShiftDR

Scan In(SI)

TD TD

MUX

S1

0

Mode

Data Out(PO)

ClockDR UpdateDR

Shift RegisterParallel OutputRegister

Scan Out(SO)Data In

(PI)

MUX

S1

0

ShiftDRScan In(SI)

TD TD

MUX

S1

0

Mode

Data Out(PO)

ClockDR UpdateDR

Shift RegisterParallel OutputRegister

Scan Out(SO)

Data In(PI)

Capture Mode

Shift Mode

IEEE 1149.1 Device Architecture

Core Logic

MUX MUXTDI TDOBypass

IdentificationRegister

InstructionRegister

TAP(Test Access Port)

Controller

(TestDataIn)

(TestDataOut)

Test Reset (Optional)

L0 L1 Li Ln-1

Li

X X

Y

Y

W W

X X

Y

W W

Y

IN

OUT

Iterative logic arrays -The elements of the array are identical and the regularity gives certain additional possibilitiesfor testing

An one-dimensional array is given as an example, but the same case applies also for two-dimensional arrays.

Test(one element)

The transport of the effect of the fault to the observed output. (through k-element)

Restoration(m elements)

In the case of C-tested array the duration of the test does not depend upon the number of elements in the array.

C-testability

The test consists of the following steps: Test for controlling certain overlap in an

element of the array; The transport of the effect of the fault to

the observed output (in case of a two-dimensional array through the elements of the second dimension);

Restoring of the test. The values of the test are restored through the elements of the array in the input of some following element

. . . . . .

Test(oneelement)

It is possible to realise one test on all elements of the array by k+m+1 steps, notwithstanding the number of the elements (i.e. dimensions of the array). If it is possible to do it with all tests we have C-tested array.

ExampleTest for one element in the array

Li

0

1

0

0

0/1

0

Due to faults, 0 in the right hand side output may turn into 1

The possible effect of the fault must be brought to the observed output (in this example – down)

Li+1 Li+2

0/1

0

1

0

1/0

1

0

0

0

1/0

In order to apply the same test to some following element we must restore the original value of thetest after having brought the effect of the fault to the observed output. On the right hand side theremust be the combination 0 1.

Li+3 Li+4

0

0

1

0

1

1

0

0

1

0

Example...continued

Li

0

1

0

0/1

0

0 1

0

1/0

1

0

0

0

1/0

1

0

1

1

0

0

1

0

Li+1 Li+2 Li Li Li

0

0/1

0

0

Test(oneelement)

The transport of the effect of the fault to the observed output. (through 2 elements)

Restoration(2 elements)

Test(oneelement)

It took five steps to realise the test on the whole of the array notwithstanding its size(number of elements)

It took five steps to realise the test on the whole of the array notwithstanding its size (number of elements).

Example...continued

COMPARATOR(comparison circuit)

Functional/faulty

I-testability

I In the case of I-tested arrays the values for all elements are identical at all tests. There is no need to keep the etalons (excpected values), as the difference in values duing the test is considered a fault.

CI-testability

CI-tested array has both charactersitics: it is C-tested and I-tested. An array can be turned into C-tested array by adding hardware and additional inputs. The same rule applies for turning an array into I-tested. A balance must be found between needs and possibilities – additional hardware reaquires more crystal space and it slows the array down. The possible maximum number of inputs is alaos limited.