Test.bench
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Transcript of Test.bench
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test isport (clk : in std_logic;
count : out std_logic_vector(3 downto 0);reset :in std_logic);
end test;
architecture Behavioral of test issignal c : std_logic_vector(3 downto 0) :=(others => '0'); --initializing count to zero.begincount <= c;process(clk,reset)beginif(clk'event and clk='1') then-- when count reaches its maximum(that is 15) reset it to 0if(c = "1111") then c <="0000";end if;c <= c+'1'; --increment count at every positive edge of clk.end if;if(reset='1') then --when reset equal to '1' make count equal to 0.c <=(others => '0'); -- c ="0000"end if;end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;
-- entity declaration for your testbench.Dont declare any ports hereENTITY test_tb IS END test_tb;
ARCHITECTURE behavior OF test_tb IS-- Component Declaration for the Unit Under Test (UUT) COMPONENT test --'test' is the name of the module needed to be tested.--just copy and paste the input and output ports of your module as such. PORT( clk : IN std_logic;
count : OUT std_logic_vector(3 downto 0);reset : IN std_logic);
END COMPONENT;--declare inputs and initialize themsignal clk : std_logic := '0';signal reset : std_logic := '0';--declare outputs and initialize themsignal count : std_logic_vector(3 downto 0);-- Clock period definitionsconstant clk_period : time := 1 ns;BEGIN -- Instantiate the Unit Under Test (UUT)uut: test PORT MAP (
clk => clk,count => count,reset => reset);
-- Clock process definitions( clock with 50% duty cycle is generated here.clk_process :process begin
clk <= '0';wait for clk_period/2; --for 0.5 ns signal is '0'.clk <= '1';wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;-- Stimulus process stim_proc: processbegin
wait for 7 ns;reset <='1';wait for 3 ns;reset <='0';wait for 17 ns;reset <= '1';wait for 1 ns;reset <= '0';wait;
end process;
END;