Test Pattern Generation Test Pattern Generation -- Organization...

Test Pattern Generation Test Pattern Generation -- OrganizationOrganization

�� Types of Test PatternsTypes of Test Patterns

�� CountersCounters

�� Finite State MachinesFinite State Machines

�� Linear Feedbak Shift RegistersLinear Feedbak Shift Registers

��Primitive PolynomialsPrimitive Polynomials

��Producing the All 0s PatternProducing the All 0s Pattern

C. Stroud 9/09 Test Pattern Generation 1

��Producing the All 0s PatternProducing the All 0s Pattern

��Reciprocal PolynomialReciprocal Polynomial

�� Cellular AutomataCellular Automata

�� Weighted PseudoWeighted Pseudo--Random Test PatternsRandom Test Patterns

�� Other TPGsOther TPGs

�� Comparing TPGsComparing TPGs

Types of Test PatternsTypes of Test Patterns

�� Deterministic Deterministic -- specific to CUT developed via ATPG or fault specific to CUT developed via ATPG or fault

simulationsimulation

�� Algorithmic Algorithmic -- used to test regular structures and specific fault used to test regular structures and specific fault

modelsmodels

�� Exhaustive Exhaustive -- all possible input test patternsall possible input test patterns

��Example: 2Example: 2nn patterns for patterns for nn--input combinational logic circuitinput combinational logic circuit


��Example: 2Example: 2nn patterns for patterns for nn--input combinational logic circuitinput combinational logic circuit

�� PseudoPseudo--exhaustive exhaustive -- each partitioned subeach partitioned sub--circuit is exhaustively circuit is exhaustively

testedtested

�� PseudoPseudo--random random -- properties similar to random sequences but properties similar to random sequences but

repeatablerepeatable

�� Weighted pseudoWeighted pseudo--random random -- specific bits produce more 1s or 0sspecific bits produce more 1s or 0s

�� Random Random -- true random patternstrue random patterns

Examples of Test Pattern GeneratorsExamples of Test Pattern Generators�� Deterministic (limited applicability)Deterministic (limited applicability)

��ROM stores test patterns, counter addresses ROMROM stores test patterns, counter addresses ROM�� AlgorithmicAlgorithmic

��FSMsFSMs�� Exhaustive (not practical for large Exhaustive (not practical for large nn))

��nn--bit counter produces all 2bit counter produces all 2nn test patternstest patterns�� PseudoPseudo--exhaustiveexhaustive


�� PseudoPseudo--exhaustiveexhaustive��counter, LFSR, or CA w/ MUXs for partitioningcounter, LFSR, or CA w/ MUXs for partitioning

�� PseudoPseudo--random (most common in BIST)random (most common in BIST)��LFSR or CA with maximalLFSR or CA with maximal--length sequencelength sequence

�� Weighted pseudoWeighted pseudo--randomrandom��LFSR or CA with AND/OR gates for weightingLFSR or CA with AND/OR gates for weighting

�� RandomRandom��difficult to implement true random vectorsdifficult to implement true random vectors

CountersCounters�� Generates all possible 2Generates all possible 2nn patternspatterns

�� Easy to implementEasy to implement

�� Moderate area overheadModerate area overhead

�� 1 FF, 1 XOR, and 1 AND per bit1 FF, 1 XOR, and 1 AND per bit

�� Good for testing combinational logicGood for testing combinational logic

�� Not so good for testing sequential logicNot so good for testing sequential logic

�� Due to fixed, regular transitionsDue to fixed, regular transitions

enablein

enablein

enableoutenableout

QiQi

QQ22 QQ11 QQ00

00 00 00


�� Due to fixed, regular transitionsDue to fixed, regular transitions�� LSB toggles every clock cycleLSB toggles every clock cycle

�� MSB toggle half way through sequenceMSB toggle half way through sequence

�� Care in which bits are assigned to which inputs of CUTCare in which bits are assigned to which inputs of CUT

�� Other types of counters to considerOther types of counters to consider

�� Gray codeGray code�� distance=1 for consecutive patterns (only 1 bit changes)distance=1 for consecutive patterns (only 1 bit changes)

�� NN--outout--ofof--M code (constant weight) M code (constant weight) �� example: 3 out of 8 bits are always 1sexample: 3 out of 8 bits are always 1s

00 00 1100 11 0000 11 1111 00 0011 00 1111 11 0011 11 1100 00 00

Finite State MachinesFinite State Machines�� Good for algorithmic test pattern generationGood for algorithmic test pattern generation

��Designed specifically for algorithmDesigned specifically for algorithm

�� Example: March Y test algorithm for RAMExample: March Y test algorithm for RAM

��↨(w0); ↑(r0, w1,r1); ↓(r1, w0, r0);↨(w0); ↑(r0, w1,r1); ↓(r1, w0, r0);↑(r0);↑(r0);��w0 = write 0w0 = write 0

�� r1 = read 1r1 = read 1

��↑ address up↑ address up


��↑ address up↑ address up

��↓ address down↓ address down

��↨ address either way↨ address either way

��Series of 4 march sequencesSeries of 4 march sequences��Each march addresses through RAMEach march addresses through RAM

Linear Feedback Shift Registers (LFSRs)Linear Feedback Shift Registers (LFSRs)

�� Efficient design for TPGs and ORAsEfficient design for TPGs and ORAs

��FFs plus a few XOR gatesFFs plus a few XOR gates

��better than counterbetter than counter�� fewer gatesfewer gates

�� higher clock frequencyhigher clock frequency

�� Two types of LFSRsTwo types of LFSRs

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

External Feedback LFSRExternal Feedback LFSR

D Q

CK

D Q

CK

D Q

CK

D Q

CK

External Feedback LFSRExternal Feedback LFSR


�� Two types of LFSRsTwo types of LFSRs

��External Feedback External Feedback

��Internal FeedbackInternal Feedback�� higher clock frequencyhigher clock frequency

�� Characteristic polynomialCharacteristic polynomial

��defined by XOR positionsdefined by XOR positions

��PP((xx) = ) = xx4 4 + + xx3 3 + + x x + 1 in both examples+ 1 in both examples

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

Internal Feedback LFSRInternal Feedback LFSR

D Q

CK

D Q

CK

D Q

CK

D Q

CK

Internal Feedback LFSRInternal Feedback LFSR

LFSRs (cont)LFSRs (cont)

Characteristic polynomial of LFSRCharacteristic polynomial of LFSR

�� n n = # of FFs = degree of polynomial= # of FFs = degree of polynomial

�� XOR feedback connection to FF XOR feedback connection to FF ii ⇔⇔ coefficient of coefficient of xxii

��Coefficient = 0 if no connectionCoefficient = 0 if no connection

��Coefficient = 1 if connectionCoefficient = 1 if connection

��Coefficients always included in characteristic polynomial:Coefficients always included in characteristic polynomial:


��Coefficients always included in characteristic polynomial:Coefficients always included in characteristic polynomial:�� xxnn (degree of polynomial & primary feedback)(degree of polynomial & primary feedback)

�� xx00 = 1 (principle input to shift register)= 1 (principle input to shift register)

�� Note: state of the LFSR Note: state of the LFSR ⇔⇔ polynomial of degree polynomial of degree nn--11

�� Example: Example: PP((xx) = ) = xx33 + + xx + 1+ 1

D D QQFF#1FF#1

CKCK

D D QQFF#1FF#1

CKCK

D D QQFF#2FF#2

CKCK

D D QQFF#2FF#2

CKCK

D D QQFF#3FF#3

CKCK

D D QQFF#3FF#3

CKCK

1x01x0 1x11x1 0x20x2 1x31x3

D D QQFF#1FF#1

CKCK

D D QQFF#2FF#2

CKCK

D D QQFF#3FF#3

CKCK

1x0 1x1 0x2 1x3

LSFRs (cont)LSFRs (cont)�� An LFSR generates periodic sequenceAn LFSR generates periodic sequence

��Must start in a nonMust start in a non--zero state,zero state,

�� The maximumThe maximum--length of an LFSR sequence is 2length of an LFSR sequence is 2nn --11

��Does not generate all 0s pattern (gets stuck in that state)Does not generate all 0s pattern (gets stuck in that state)

�� The characteristic polynomial of an LFSR generating a The characteristic polynomial of an LFSR generating a

maximummaximum--length sequence is a length sequence is a primitive polynomialprimitive polynomial


maximummaximum--length sequence is a length sequence is a primitive polynomialprimitive polynomial�� A maximumA maximum--length sequence is length sequence is pseudopseudo--randomrandom::

��Number of 1s = number of 0s + 1Number of 1s = number of 0s + 1

��Same number of runs of consecutive 0s and 1sSame number of runs of consecutive 0s and 1s

��1/2 of the runs have length 11/2 of the runs have length 1

��1/4 of the runs have length 21/4 of the runs have length 2

��… (as long as fractions result in integral numbers of runs)… (as long as fractions result in integral numbers of runs)

LFSRs (cont)LFSRs (cont)�� Example: Characteristic polynomial is Example: Characteristic polynomial is PP((xx) = ) = xx33 + + xx + 1+ 1

�� Beginning at all 1s stateBeginning at all 1s state

�� 7 clock cycles to repeat7 clock cycles to repeat

�� Maximal length = 2Maximal length = 2nn--11

�� Polynomial is primitivePolynomial is primitive

�� Properties:Properties:

�� Four 1s and three 0sFour 1s and three 0s

D QD QFF1FF1

CKCK

D QD QFF1FF1

CKCK

D QD QFF2FF2

CKCK

D QD QFF2FF2

CKCK

D QD QFF3FF3

CKCK

D QD QFF3FF3

CKCK

11xx0011xx00 11xx1111xx11 00xx2200xx22 11xx3311xx33

11 11 11 1111 00 11 2211 00 00 33

11 11 11 1111 00 11 2211 00 00 33

D QD QFF1FF1

CKCK

D QD QFF2FF2

CKCK

D QD QFF3FF3

CKCK

11xx00 11xx11 00xx22 11xx33

11 11 11 1111 00 11 2211 00 00 33


�� 4 runs:4 runs:�� 2 runs of length 1 (one 0 & one 1)2 runs of length 1 (one 0 & one 1)

�� 1 run of length 2 (0s)1 run of length 2 (0s)

�� 1 run of length 3 (1s)1 run of length 3 (1s)

�� Note: external & internal LFSRs with same primitive polynomial do not Note: external & internal LFSRs with same primitive polynomial do not

generate same sequence (only same length)generate same sequence (only same length)

11 00 00 3300 11 00 4400 00 11 5511 11 00 6600 11 11 7711 11 11

11 00 00 3300 11 00 4400 00 11 5511 11 00 6600 11 11 7711 11 11

11 00 00 3300 11 00 4400 00 11 5511 11 00 6600 11 11 7711 11 11

LFSRs (cont)LFSRs (cont)�� Reciprocal polynomial, Reciprocal polynomial, PP*(*( xx))

��PP*(*( xx) = ) = xxnn PP(1/(1/xx))��Example: Example: PP((xx) = ) = xx33 + + xx + 1+ 1

��Then: Then: PP*(*( xx) = ) = xx33 ((xx--33 + + xx--11 +1) = 1 + +1) = 1 + xx22 + + xx33 = = xx33 + + xx22 +1+1

��If If PP((xx) is primitive, ) is primitive, PP*(*( xx) is also primitive) is also primitive��Same for nonSame for non--primitive polynomialsprimitive polynomials

�� Polynomial arithmeticPolynomial arithmetic


�� Polynomial arithmeticPolynomial arithmetic

��ModuloModulo--2 (2 (xxnn + + xxnn = = xxnn -- xxnn = 0)= 0)

Addition/SubtractionAddition/Subtraction((xx55 + + xx22 + 1) + (+ 1) + (xx44 + + xx22))xx55 xx22 11+ + xx44 xx22

xx55 xx44 11= = xx55 + + xx44 + 1+ 1


xx55 xx44 11= = xx55 + + xx44 + 1+ 1


xx55 xx44 11= = xx55 + + xx44 + 1+ 1

MultiplicationMultiplication((xx22 + + xx + 1) + 1) ×××××××× ((xx22 + 1)+ 1)

xx22 + + xx + 1+ 1×××××××× xx22 + 1+ 1xx22 + + xx + 1+ 1

xx44 + + xx33 + + xx22

= = xx44 + + xx33 + + xx + 1+ 1


xx22 + + xx + 1+ 1×××××××× xx22 + 1+ 1xx22 + + xx + 1+ 1

xx44 + + xx33 + + xx22

= = xx44 + + xx33 + + xx + 1+ 1


xx22 + + xx + 1+ 1×××××××× xx22 + 1+ 1xx22 + + xx + 1+ 1

xx44 + + xx33 + + xx22

= = xx44 + + xx33 + + xx + 1+ 1

DivisionDivisionxx22 + + xx + 1+ 1

xx22 + 1 + 1 xx44 + + xx33 + + xx + 1+ 1xx44 + + xx22

xx33 + + xx22 + + xx + 1+ 1xx3 3 + + xx

xx22 + 1+ 1xx22 + 1+ 1

00


xx22 + 1 + 1 xx44 + + xx33 + + xx + 1+ 1xx44 + + xx22

xx33 + + xx22 + + xx + 1+ 1xx3 3 + + xx

xx22 + 1+ 1xx22 + 1+ 1

00


xx22 + 1 + 1 xx44 + + xx33 + + xx + 1+ 1xx44 + + xx22

xx33 + + xx22 + + xx + 1+ 1xx3 3 + + xx

xx22 + 1+ 1xx22 + 1+ 1

00

LFSRs (cont)LFSRs (cont)

�� NonNon--primitive polynomials produce sequences < 2primitive polynomials produce sequences < 2nn--11

��Typically primitive polys desired for TPGs & ORAsTypically primitive polys desired for TPGs & ORAs

�� Example of nonExample of non--primitive polynomialprimitive polynomial

��PP((xx) = ) = xx33 + + xx22 + + xx + 1+ 1

External Feedback LFSRExternal Feedback LFSRExternal Feedback LFSRExternal Feedback LFSR Internal Feedback LFSRInternal Feedback LFSRInternal Feedback LFSRInternal Feedback LFSR


D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

1 1 11 1 11 1 11 1 11 1 11 1 11 1 11 1 1

0 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 0

1 0 01 0 01 1 01 1 00 1 10 1 10 0 10 0 11 0 01 0 0

1 0 01 0 01 1 01 1 00 1 10 1 10 0 10 0 11 0 01 0 0

0 1 00 1 01 0 11 0 10 1 00 1 0

0 1 00 1 01 0 11 0 10 1 00 1 0

D Q

CK

D Q

CK

D Q

CK

1 1 11 1 11 1 11 1 1

0 0 00 0 00 0 00 0 0

1 0 01 0 01 1 01 1 00 1 10 1 10 0 10 0 11 0 01 0 0

0 1 00 1 01 0 11 0 10 1 00 1 0

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

1 1 11 1 11 0 01 0 00 1 00 1 00 0 10 0 11 1 11 1 1

1 1 11 1 11 0 01 0 00 1 00 1 00 0 10 0 11 1 11 1 1

1 1 01 1 00 1 10 1 11 1 01 1 0

1 1 01 1 00 1 10 1 11 1 01 1 0

0 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 0

1 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 1

D Q

CK

D Q

CK

D Q

CK

1 1 11 1 11 0 01 0 00 1 00 1 00 0 10 0 11 1 11 1 1

1 1 01 1 00 1 10 1 11 1 01 1 0

0 0 00 0 00 0 00 0 0

1 0 11 0 11 0 11 0 1

LFSRs (cont)LFSRs (cont)�� Primitive polynomials with minimum # of XORsPrimitive polynomials with minimum # of XORs

Degree (Degree (nn) Polynomial) Polynomial2,3,4,6,7,15,22 2,3,4,6,7,15,22 xxnn + + xx + 1+ 15,11,21,29 5,11,21,29 xxnn + + xx22 + 1+ 18,19 8,19 xxnn + + xx66 + + xx55 + + xx + 1+ 19 9 xxnn + + xx44 + 1+ 110,17,20,25,28 10,17,20,25,28 xxnn + + xx33 + 1+ 112 12 xxnn + + xx77 + + xx44 + + xx33 + 1+ 1




12 12 xxnn + + xx77 + + xx44 + + xx33 + 1+ 113,24 13,24 xxnn + + xx44 + + xx33 + + xx + 1+ 114 14 xxnn + + xx1212+ + xx1111+ + xx + 1+ 116 16 xxnn + + xx55 + + xx33 + + xx22 + 1+ 118 18 xxnn + + xx77 + 1+ 123 23 xxnn + + xx55 + 1+ 126,27 26,27 xxnn + + xx88 + + xx77 + + xx + 1+ 130 30 xxnn + + xx1616+ + xx1515+ + xx + 1+ 1



Problems with LFSRs for TPGsProblems with LFSRs for TPGs

�� Some faults are Some faults are randomrandom--pattern resistantpattern resistant��Low detection probability Low detection probability -- detected by only by a few vectorsdetected by only by a few vectors

��NonNon--functional patterns applied to CUT may cause problemsfunctional patterns applied to CUT may cause problems

�� How many vectors to apply?How many vectors to apply?

�� Have we reached the desired fault coverage?Have we reached the desired fault coverage?

�� Methods to reduce or eliminate randomMethods to reduce or eliminate random--pattern resistance:pattern resistance:


�� Methods to reduce or eliminate randomMethods to reduce or eliminate random--pattern resistance:pattern resistance:

��Weighted pseudoWeighted pseudo--random patternsrandom patterns��Add filter between TPG and CUT to get desired pattern probabilitiesAdd filter between TPG and CUT to get desired pattern probabilities

��Combine adCombine ad--hoc DFT techniqueshoc DFT techniques�� Insert additional control pointsInsert additional control points

�� Insert additional observation pointsInsert additional observation points

��Can use a parity tree to feed extra responses to ORACan use a parity tree to feed extra responses to ORA

Modifications to LFSRsModifications to LFSRs�� All 0s state can be included in the pseudoAll 0s state can be included in the pseudo--random sequencerandom sequence

��Cost: 1 XOR and nCost: 1 XOR and n--1 input NOR gate1 input NOR gate 11 11 11 1111 00 11 2211 00 00 3300 11 00 4400 00 11 5500 00 00 6611 11 00 7700 11 11 88

D Q1

CK

D Q1

CK

D Q2

CK

D Q2

CK

D Q3

CK

D Q3

CK

1x01x0 1x11x1 0x20x2 1x31x3

D Q1

CK

D Q2

CK

D Q3

CK

1x0 1x1 0x2 1x3


00 11 11 8811 11 11

�� Weighted pseudoWeighted pseudo--random patternsrandom patterns

��Probability of a logic 1 pProbability of a logic 1 p11≈≈0.5 for each LFSR bit (0.5 for each LFSR bit (pp00≈≈0.5)0.5)

��Probability can be weighted using AND/OR gatesProbability can be weighted using AND/OR gates��NN--input AND gate gives pinput AND gate gives p11≈≈0.50.5NN

��NN--input OR gate gives pinput OR gate gives p00≈≈0.50.5NND Q

1CK

D Q1

CK

D Q2

CK

D Q2

CK

D Q3

CK

D Q3

CK

p0≈≈0.25

D Q1

CK

D Q2

CK

D Q3

CK

p0≈≈0.25

Cellular Automata (CA) RegistersCellular Automata (CA) Registers�� Similar to an LFSRSimilar to an LFSR

�� Generates pseudoGenerates pseudo--random test patternsrandom test patterns�� Different from an LFSRDifferent from an LFSR

�� Does not have obvious shift in patterns like LFSRDoes not have obvious shift in patterns like LFSRExternalExternal Feedback LFSRFeedback LFSR11 11 11 11 11 11 11 1100 11 11 11 11 11 11 1111 00 11 11 11 11 11 1100 11 00 11 11 11 11 11

InternalInternal Feedback LFSRFeedback LFSR11 11 11 11 11 11 11 1111 00 11 11 11 00 00 1111 00 00 11 11 00 11 0000 11 00 00 11 11 00 11

Cellular Automata RegisterCellular Automata Register11 11 11 11 11 11 11 1111 00 11 00 11 00 11 1100 00 11 00 11 00 00 1100 11 11 00 11 11 11 00


00 11 00 11 11 11 11 1111 00 11 00 11 11 11 1100 11 00 11 00 11 11 1100 00 11 00 11 00 11 1100 00 00 11 00 11 00 1100 00 00 00 11 00 11 0011 00 00 00 00 11 00 1111 11 00 00 00 00 11 0011 11 11 00 00 00 00 1100 11 11 11 00 00 00 0000 00 11 11 11 00 00 0011 00 00 11 11 11 00 0011 11 00 00 11 11 11 00

00 11 00 00 11 11 00 1111 11 11 00 00 00 00 0000 11 11 11 00 00 00 0000 00 11 11 11 00 00 0000 00 00 11 11 11 00 0000 00 00 00 11 11 11 0000 00 00 00 00 11 11 1111 11 00 00 00 11 00 1111 00 11 00 00 11 00 0000 11 00 11 00 00 11 0000 00 11 00 11 00 00 1111 11 00 11 00 00 11 0000 11 11 00 11 00 00 11

00 11 11 00 11 11 11 0011 11 00 00 00 00 00 1111 11 11 00 00 00 11 0011 00 00 11 00 11 11 1100 11 11 00 00 11 11 1111 11 00 11 11 11 11 1111 11 00 11 11 00 11 1111 11 00 11 00 00 00 1111 11 00 00 11 00 11 0011 11 11 11 11 00 11 1111 00 11 00 00 00 00 1100 00 11 11 00 00 11 0000 11 00 11 11 11 11 11

CA Registers (continued)CA Registers (continued)

�� Next state for a CA register bit is a function ofNext state for a CA register bit is a function of

��The CA register bit before it: The CA register bit before it: xxii--11(t)(t)

��Itself: Itself: xxii(t)(t)

��The CA register bit after it: The CA register bit after it: xxi+1i+1(t)(t)

��There are 8 possible values for:There are 8 possible values for:��xxii--11(t) x(t) xii(t) x(t) xi+1i+1(t) (t) (000,…,111)(000,…,111)

xxiixxiixxii--11xxii--11 xxi+1i+1xxi+1i+1xxiixxii--11 xxi+1i+1


��xxii--11(t) x(t) xii(t) x(t) xi+1i+1(t) (t) (000,…,111)(000,…,111)

��This corresponds to values 0 through 7This corresponds to values 0 through 7

�� A CA register is constructed from rulesA CA register is constructed from rules

��The are 256 possible combinations of binary values for The are 256 possible combinations of binary values for

the 8 variations of the 8 variations of xxii--11(t) x(t) xii(t) x(t) xi+1i+1(t) (t)

��Each combination is a rule (0Each combination is a rule (0--255)255)

��Only rules 90 and 150 are useful for CAOnly rules 90 and 150 are useful for CA--based TPGsbased TPGs

CA Rules 90 and 150CA Rules 90 and 150

xxii--11(t) x(t) xii(t) x(t) xi+1i+1(t)(t)77

11111166

11011055

10110144

10010033

01101122

01001011

00100100

000000Rule 90Rule 90

64+16+8+2=9064+16+8+2=902266

(64)(64)2244

(16)(16)2233

(8)(8)2211

(2)(2)xxii(t+1)(t+1) 00 11 00 11 11 00 11 00

Rule 150Rule 150128+16+4+2=150128+16+4+2=150

2277

(128)(128)2244

(16)(16)2222

(4)(4)2211

(2)(2)

xx (t+1)(t+1) 11 00 00 11 00 11 11 00


xxii(t+1)(t+1) 11 00 00 11 00 11 11 00

Rule 90: Rule 90: xxii(t) = x(t) = xii--11(t) (t) ⊕⊕ xxi+1i+1(t)(t) Rule 150: Rule 150: xxii(t) = x(t) = xii--11(t) (t) ⊕⊕ xxii(t)(t) ⊕⊕ xxi+1i+1(t)(t)

xxiixxiixxii--11xxii--11 xxi+1i+1xxi+1i+1xxiixxii--11 xxi+1i+1 xxiixxiixxii--11xxii--11 xxi+1i+1xxi+1i+1xxiixxii--11 xxi+1i+1

0 1 1 01 0 0 10 1 1 01 0 0 1

xxii(t) x(t) xi+1i+1(t)(t)xxii--11(t) (t) 00 01 11 1000 01 11 10

0

1

0

1

0 1 1 01 0 0 1

xxii(t) x(t) xi+1i+1(t)(t)xxii--11(t) (t) 00 01 11 10

0

1

0 1 0 11 0 1 00 1 0 11 0 1 0

xxii(t) x(t) xi+1i+1(t)(t)xxii--11(t) (t) 00 01 11 1000 01 11 10

0

1

0

1

0 1 0 11 0 1 0

xxii(t) x(t) xi+1i+1(t)(t)xxii--11(t) (t) 00 01 11 10

0

1

CA Register ConstructionCA Register Construction�� CA registers are constructed given a rule for each bitCA registers are constructed given a rule for each bit

��Combinations of rules determine maximal length Combinations of rules determine maximal length sequence (or not)sequence (or not)��Rules obtained from tables just like LFSRRules obtained from tables just like LFSR��Just like primitive vs. nonJust like primitive vs. non--primitive polynomials in LFSRsprimitive polynomials in LFSRs

�� What about the ends of the register since there is no What about the ends of the register since there is no adjacent bit?adjacent bit?


adjacent bit?adjacent bit?��Two type of boundary conditionsTwo type of boundary conditions

��Null Null –– assume logic 0 for missing bitassume logic 0 for missing bit��Reduces number of XORsReduces number of XORs

��Cyclic Cyclic –– assume “wrapassume “wrap--around” of ends of registeraround” of ends of register

��So far only Null boundary conditions have been found So far only Null boundary conditions have been found that produce maximal length sequencethat produce maximal length sequence

�� CA register area overhead: CA register area overhead: NNxorxor = = NNffff + + RR150150 -- 22

Example CA RegisterExample CA Register

�� 66--bit CA constructed for rules: 150, 90, 90, 90, 90, 90bit CA constructed for rules: 150, 90, 90, 90, 90, 90��Produces a maximal length sequenceProduces a maximal length sequence

��All 2All 2nn--1 possible non1 possible non--0 values0 values��Just like LFSRJust like LFSR

��Note that we lock up in the all 0s stateNote that we lock up in the all 0s state��Just like LFSRJust like LFSR

��More XOR gates than LFSRMore XOR gates than LFSR


��More XOR gates than LFSRMore XOR gates than LFSR

Rule 150Rule 150w/ null BCw/ null BC

Rule 90Rule 90w/ null BCw/ null BC

Rule 90Rule 90Rule 90Rule 90 Rule 90Rule 90 Rule 90Rule 90

Other TPGsOther TPGs�� LFSR with shift registerLFSR with shift register

��Larger number of bits with small LFSRLarger number of bits with small LFSR

�� Accumulator with constant prime numberAccumulator with constant prime number

��Generates all 2Generates all 2nn patterns like counterpatterns like counter

Example: +Example: +550000 1 00000 1 00101 2 50101 2 51010 1010 3 103 101111 1111 4 154 150100 0100 5 45 41001 1001 6 96 91110 1110 7 147 140011 0011 8 38 3

LFSRLFSRLFSRLFSR Shift RegisterShift RegisterShift RegisterShift Register

NNNN MMMM

LFSRLFSR Shift RegisterShift Register

NN MM


��More MSB transitions than counterMore MSB transitions than counter

��Does not have random properties of LFSRDoes not have random properties of LFSR��LSB still togglesLSB still toggles

��2 LSBs still count2 LSBs still count

0011 0011 8 38 31000 1000 9 89 81101 1101 10 1310 130010 0010 11 211 20111 0111 12 712 71100 1100 13 1213 120001 0001 14 114 10110 0110 15 615 61011 1011 16 1116 110000 00000 0

adderadderadderadder

RegisterRegisterRegisterRegister

constantconstantconstantconstant

adderadder

RegisterRegister

constantconstant

Comparison of TPGsComparison of TPGs�� Area and performanceArea and performance

��LFSR most efficientLFSR most efficient�� Internal feedback has Internal feedback has

higher performancehigher performance

�� How well does the TPG How well does the TPG test itself?test itself?��Internal feedback Internal feedback

TPGTPG #FFs#FFs #XORs#XORs #gates#gates Gate I/OGate I/O

LFSRLFSR 88 33 88 3333WLFSRWLFSR 1313 33 1515 5151

CARCAR 88 99 88 5151CounterCounter 88 88 1515 6969MarchYMarchY 99 99 1919 9494


��Internal feedback Internal feedback LFSR wins again, LFSR wins again, but barely beats but barely beats CARCAR

��Note counterNote counter--based based TPGs achieve max TPGs achieve max fault coverage when fault coverage when MSB togglesMSB toggles

Test Pattern Generation Test Pattern Generation -- Organization...

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