1972 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 8, AUGUST 2019

Test-Friendly Data-Selectable Self-Gating (DSSG)Jihye Kim, Sangjun Lee, and Sungho Kang

Abstract— Low-power design is a key consideration in modern design.XOR self-gating (data-driven self-gating) is used for power reductionin clock networks, which is one of the main factors of dynamicpower consumption. When applying XOR self-gating, dynamic powerconsumption is reduced, but the number of required test patterns on thetesting side is inflated. In critical cases, more than three times the regularnumber of scan test patterns may be required for industrial designs, suchas GPUs. In this brief, we propose a novel self-gating structure. Data-selectable self-gating (DSSG) is designed to use functional data and scandata selectively to eliminate the unnecessary clock toggling of flip-flops.With this structure, the self-gating function can be used in the scan testmode, as well as the function mode. When the self-gating logic is usedduring scan shift operations, the stuck-at faults in the self-gating logiccan be tested with short test sequences; therefore, the rise in test costs canbe mitigated. It is possible to test the stuck-at faults in self-gating logicusing only four scan test patterns. The experimental results show thatthe average of the stuck-at test pattern increase ratio has been droppedfrom more than 90% to less than 8%. The low-power performance ofthe proposed method in the mission mode is the same as that of theconventional self-gating structures. When the DSSG method is used,the dynamic power of the shift operation which may increase excessivelyduring the scan test can be reduced.

Index Terms— Clock gating, low-power design, scan test,self-gating, test cost.

I. INTRODUCTION

Requirements for increased graphical performance in mobile GPUshave expanded based on recent technological advancements, such asthe Internet-of-Things (IoT) applications and deep learning based onlocal training. Parallel computation in multiple cores and higher oper-ating frequencies for superior performance has significantly increasedenergy consumption [1]–[4]. All possible low-power solutions shouldbe considered to prevent power consumption from becoming aperformance constraint. Clock gating is a commonly used low-powerdesign methodology for switching power reduction [5]. Synthesis-based clock gating is the most widely used method. However, evenadopting synthesis-based clock gating, many redundant clock pulsesare remaining. XOR self-gating (data-driven clock gating) has beenproposed to remedy this issue [6].

However, we have observed that scan test pattern inflation issignificant following the adoption of XOR self-gating in very largeand complex designs, such as GPUs. As design becomes largerand more complex, the number of scan test patterns increasesrapidly [7], [8]. As the application range of semiconductor devices hasexpanded and they have been applied to high value-added products,the demands for more reliable and high-quality testing requirementshave increased [9], [10]. Therefore, various test sets and a largernumber of test vectors are being generated and applied. From a

Manuscript received December 19, 2018; revised March 18, 2019 andApril 16, 2019; accepted May 3, 2019. Date of publication June 3, 2019;date of current version July 24, 2019. This work was supported by theIT R&D program of MOTIE/KEIT. [10052716, Design technology devel-opment of ultra-low voltage operating circuit and IP for smart sensor SoC].(Corresponding author: Sungho Kang.)

The authors are with the Department of Electrical and Electronic Engi-neering, Yonsei University, Seoul 03722, South Korea (e-mail: irene152@soc.yonsei.ac.kr; lsj920807@soc.yonsei.ac.kr; shkang@yonsei.ac.kr).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2019.2916637

Fig. 1. Conventional XOR self-gating structure.

power perspective, because test-mode power consumption can behigher than the functional-mode power consumption, various power-aware automatic test pattern generation (ATPG) methods are appliedduring the scan test pattern generation. Typically, the test patterncount is increased when using low-power ATPG features [11]–[13].Because XOR self-gating logic is structurally low testability circuit bynature, significant test cost increases may be incurred when testingself-gating logic. The test point insertion method for random resistantfaults [14] can be used in XOR self-gating inserted circuits to improvetestability. However, the increase in test pattern counts cannot beeliminated completely and expensive hardware overhead is required.

In this brief, we propose an effective self-gating structure for stuck-at test pattern reduction. This novel self-gating structure, called data-selectable self-gating (DSSG), is designed to obtain 100% stuck-attest coverage of the self-gating logic in a very short test cycle with asimilar area overhead. In addition, a self-gating function is also usedto reduce clock toggling in scan shift operations for low-power scantesting.

The remainder of this brief is organized as follows. In Section II,the conventional self-gating structure and current issues are described.Section III presents the proposed DSSG method. Section IV discussesthe experimental results, and Section V concludes this brief.

II. BACKGROUND

Clock networks consume large amounts of dynamic power [6].Clock gating is a common method for dynamic power reduction, andXOR self-gating is one of the useful clock gating methods for reducingmeaningless clock toggling to provide extreme power reduction.

A. Conventional xor Self-Gating Structure

A conventional XOR self-gating structure is presented in Fig. 1.By using the self-gating logic, unnecessary clock toggling is gatedby comparing the D and Q signals of the flip-flops. Several flip-flopsare gated together in one self-gating group to reduce the hardwareoverhead. The output signals of XOR cells inside a group areconnected to the OR cell. The output of the OR cell becomes anenabling signal (EN) for the clock-gating cell.

B. Pattern Inflation With xor Self-Gating

XOR self-gating is useful for power reduction, but the logic isvery hard to test. In the case of the stuck-at zero (SA0) faults ofeach XOR cell, they are not simply tested with a small numberof patterns. Because all fan-in and fan-out logic operations of theflip-flops in a group must be considered together to generate proper

1063-8210 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 8, AUGUST 2019 1973

Fig. 2. Proposed DSSG structure.

test patterns, the amount of calculation and the search space for ATPGare increased. In the case of stuck-at one (SA1) faults around the OR

cell in the self-gating logic shown in Fig. 1 are redundant faults. Theredundant faults can be misclassified as a not detected fault class,causing fault coverage degradation or increasing the pattern counts.These SA1 faults do not functionally affect circuit operations, butadditional hardware for testing or considerations to handling the faultclasses are needed. Through experimentation, more than 100% patterncount increases are observed in many cases and there is a case wherethe pattern count increased up to almost 300% with the conventionalself-gating.

III. DATA-SELECTABLE SELF-GATING METHOD

A. Motivation

In a conventional scan test, self-gating logic is enabled during scancapture operations. The output signals of scan flip-flops are easilyapplied by scan shift operations. Scan pattern inflation is caused bycontrolling the data signals of flip-flops. Because only one outputamong the XOR cells in a self-gating group should be set to one todetect SA0 faults in the self-gating logic, all combinational circuitsconnected to the data ports of the flip-flops must be controlledsimultaneously. Therefore, ATPG calculation complexity increases.Furthermore, multiple XOR cells in a self-gating group cannot betested simultaneously by a single scan pattern. Therefore, a largenumber of scan test patterns are required for testing self-gating logic.

The main idea of the proposed method is to make the self-gatinglogic enabled in scan shift modes by selecting the functional input orthe scan input (SI) for comparing data. In the scan shift mode, sincethe value of the scan in and output signals of the scan flip-flops isdirectly controlled through scan shift paths, proper scan patterns fortesting the self-gating logic can be generated easily. In addition, evenwith a single scan test pattern, many faults in the self-gating logiccan be tested by applying various signal combinations for each shiftcycle.

B. Structure

As shown in Fig. 2, the proposed DSSG structure is designed to useboth the functional data (D) signal and SI signal of the scan flip-flopsselectively, instead of using only the functional data signal. The use ofD and SI for clock gating is determined by scan enable (SE) signal.In this structure, redundant SA1 faults exist like the conventionalstructure. During the scan shift operation, the gating of clocks isdetermined by scan shifting values. In the mission mode, self-gatinglogic is driven by the D and Q signals of the flip-flops, just like theconventional structures.

Fig. 3. Example of initial scan shift operation with the DSSG structure.

In general, the clock-gating cell uses an SE signal to guaranteethat the clock is always toggled during the scan shift operation.However, in the DSSG structure, clock-gating cells of the self-gatinglogic should be turned on and off during the scan shift operation totest the self-gating logic itself, so the OR cells generally located insideof the clock-gating cells for self-gating logic should not be connectedto the SE signal. For a clock-gating cell inside of the self-gating logic,even though clock toggling is not guaranteed by SE, the clock appliedto the flip-flop in the gating group is deactivated only when the clocktoggling is meaningless, such as when SI and Q values are the same.Therefore, proper scan shift operations can be performed withoutSE connections and EN value checking for self-gating logic and theexisting OR cell inside of the clock-gating cell can be eliminated orset to zero to make it transparent. For a complete test, all flip-flopsin a self-gating group should be stitched into the same scan chain.

C. Fault Detection Mechanism

1) X-Clock Handling for Initialization: Before applying the testsequences for self-gating logic, the flip-flops should be initializedto zero or one values. Initially, all flip-flops have an X value ina simulation environment. The initial X values of the flip-flopscause X-clocking conditions because the clock toggling is determinedby flip-flop values. However, there is no X state in a physicalenvironment. Even flip-flops which have X values in a simulationenvironment must have values of zero or one physically. Fig. 3 showsan example of the shift operation with the DSSG structure. Forexample, there are nine flip-flops in a scan chain and each of threeflip-flops is grouped into the three DSSG groups, GRP_0, GRP_1,and GRP_2. If the scan chain is assumed to have initial values000001111 physically from FF0 to FF8 and 001100110 values areassumed to be shifted into the scan chain, then the gated clocks(GCKs), CK_0, CK_1, and CK_2, are internally toggled or nottoggled depending on the initial values of the flip-flops, but shift-in values, 001100110, are placed correctly in the chain after ninecycles. The initial values on the flip-flops are shifted out through thescan out port as in the circuit without the DSSG structure. The valuesof all flip-flops are physically the same as those without the DSSGstructure for all operations, regardless of the initial and shift values.The only difference is that meaningless internal clocking is removed.When the simulation is performed, it is considered that the clock istoggled regardless of the internal clock gating. Therefore, for propersimulation, it is necessary to perform the simulation that the flip-flopsare assumed to be driven by the source clock regardless of the clockgating in the DSSG structure.

2) Fault Detection: With the DSSG structure, self-gating logic isused during the scan shift operation. Therefore, the self-gating logiccan be tested with other circuits using normal scan test patterns.

1974 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 8, AUGUST 2019

Fig. 4. Test patterns for the XOR self-gating logic test. (a) Initializationpattern and first pattern. (b) Second pattern and unloading pattern.

However, a typical ATPG engine does not calculate the ON and OFF

states of clock-gating cells during scan shift operations for the sakeof efficiency; it is difficult to check the exact test coverage of theself-gating logic during normal scan tests. Therefore, we propose thegeneration of an independent test pattern set that is applied separatelyfrom the normal scan test.

First, all flip-flops in the circuit are initialized to zero or one.After initialization, the opposite values of the initial values are shiftedthrough the scan paths. As the flip-flop values change, the XOR cellsin one self-gating group are sequentially enabled in one-hot sequenceto toggle the clock. Fig. 4(a) presents the test sequences and detectedfaults for the first pattern. When the initialization values are zeros,the output of each XOR cell becomes one sequentially by shiftingall one shifting values. If there are no faults in the self-gating logic,the updated values are shifted out in the next pattern. If the sameoperation is applied again with opposite values, as shown in Fig. 4(b),the remaining faults, except for redundant faults (SA1 faults) in theself-gating logic, can be tested. Including the initialization pattern,four scan test patterns are sufficient to test the stuck-at faults of theself-gating logic.

This DSSG structure and testing method can be applied to scancompression inserted circuits as well. As long as all flip-flops inthe same self-gating group are stitched into the same scan chain,regardless of any position mixing with flip-flops in other groups orinverted shift values in the middle of the scan chain, the self-gatinglogic can be tested using only the four patterns described above. Even

Fig. 5. DSSG structure for testing redundant SA1 faults.

Fig. 6. Example for detecting SA1 faults.

if scan compression is applied, the same testing method can be usedfor self-gating logic if the same data can be continuously applied toeach internal scan chain through the compression logic.

D. Redundant SA1 Fault Testing

There are redundant SA1 faults inside of the self-gating logicshown in Fig. 5. To activate these faults, D and Q signals of eachflip-flop in the self-gating group must have the same values. In thiscase, even if a clock-gating cell is ungated because of SA1 faults,the values of the flip-flops will not be changed. Thus, whether faultyor not, the expected values of the flip-flops are the same, so theSA1 faults are redundant. In order to detect such redundant faults,an additional port like sg_test and additional cells such as OR or AND

should be inserted for each self-gating group.Even the input and output signals of the flip-flop are set to different

values in the self-gating group, the condition that the GCK is nottoggled can be made by the additional cells and the sg_test signalenables these additional cells. The additional cells (OR or AND) fortesting SA1 faults can be inserted anywhere within the self-gatinggroup. But, it makes easy to handle the test pattern generation processto insert the additional cells at the fixed position such as the firstor last flip-flop in the group. Also, if there are several self-gatinggroups in the same chain, it is effective to generate test patternsby adding two different type cells alternately, as shown in Fig. 6.Otherwise, multiple test patterns need to be generated because it isdifficult to make the condition to test all groups simultaneously withonly one pattern. The flip-flops in the same group must be stitchedwithin the same scan chain, and mixing with normal flip-flops withoutself-gating is allowed but mixing with flip-flops in other groups isnot allowed.

In the test patterns for SA1 faults, initialized data selection isimportant. The additional OR cell inserted groups should be initializedwith values of zero, and the AND cell inserted groups should be

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 8, AUGUST 2019 1975

Fig. 7. Clock gating with a low-power ATPG option.

TABLE I

DESIGN INFORMATION FOR EXPERIMENTAL CIRCUITS

initialized with values of one. Starting from scan-in, the initialvalue should be changed according to the additional cell type ofthe group each time the first flip-flop in the group is encountered.During initialization using the scan path, sg_test is set to zero. Afterinitialization, only one cycle is required to enable SA1 faults. For theone cycle, sg_test is set to a value one and clock pulse is applied.If there is no SA1 fault in the self-gating logic, the clock for theself-gating flip-flops will not be toggled, and the initial values of theflip-flops will be shifted out. For the SA1 fault testing, 2N +1 cycles(i.e., N cycles for initialization, one cycle for enabling faults, and Ncycles for observing faults) are required.

E. Power Reduction Effect

Because the proposed self-gating structure is also operated in thescan test mode, a dynamic power reduction effect can be obtainedby using the DSSG as in the mission mode. In the case of ascan test, because the flip-flops in the target circuit can be toggledsimultaneously during shift operations, scan test power may exceedthe mission-mode power limit. Excessive power consumption causesmalfunctions, and it leads to yield loss. For this reason, variouslow-power methods are used for scan test modes. The most commonlyused methods for reducing dynamic power consumption are methodsthat suppress the transition of scan shift data, such as an adjacentfilling. Adjacent filling, which fills in the same data as adjacent scancells for don’t-care bits, is applied in most cases by default. Similarly,various low-power ATPG methods are used to reduce data transitionsin scan chains. In the proposed structure, all the flip-flops withina group must be stitched to the same scan chain. In the examplein Fig. 7, if no self-gating (NO_SG) logic or random filling methodis adopted, every clock of the flip-flops will be toggled during scanshifting. However, if the DSSG method is adopted with low-powerATPG options, such as adjacent filling, the clocks of the self-gatinggroup are not toggled for five of the 15 cycles. Therefore, when theDSSG method is used together with the low-power ATPG method,synergistic effects on power reduction are expected.

IV. EXPERIMENTAL RESULTS

The test aspects impact of the conventional self-gating and theeffects of the proposed DSSG method were analyzed using fourindustrial circuits. Design information regarding the four circuits isprovided in Table I. Various sizes of circuits ranging from 1.3Mto 8.4M gate counts were used, and they are synthesized using thesame technology library for fair comparisons. The Synopsys softwarepackage was used for the experiments. Scan compressions wereinserted in each circuit, and only the adjacent fill option was appliedfor low-power ATPG.

Fig. 8. Effects of self-gated flip-flop ratio on test pattern increase.

First, to examine the changes in the number of test patterns accord-ing to the self-gating flip-flop ratio with the XOR self-gating method,ATPG was performed after self-gating insertion while varying theself-gating ratio (SG ratio) from 0% to 20% in 5% increments.Fig. 8 presents the test pattern increase ratio versus the SG ratio basedon the test pattern count of the circuits without self-gating (0%). Thegraph reveals that the higher the ratio of self-gating insertion, thehigher the ratio of increase in test pattern count is. In this experiment,up to 284% of the test pattern was observed to increase in the circuitwith self-gating. The amount of pattern increase depends on thecircuit, but the higher the target test coverage, the greater the patternincrease ratio is. Therefore, in a situation where the demand for higherquality test is increasing, self-gating may have a big influence on testtime.

The self-gating group size can be associated with the test patterncount. For XOR self-gating, the larger the group size, the more thetest pattern count is. However, setting the group size too small maycause an increase in area overhead. Therefore, the appropriate groupsize should be selected considering power and area constraints of thedesigns. As shown in Fig. 9, the test pattern increase ratio of the XOR

self-gating cases which have average group size 6 (XOR_GRP_6) ishigher than that of the XOR self-gating cases which have averagegroup size 3 (XOR_GRP_3). On the other hand, the number of testpatterns required to test the DSSG structure is constant independentof the group size. For all experiments, the maximum group size isset to 8 based on the design experience, and average six or sevenflip-flops are formed to make one self-gating group.

Table II shows the stuck-at test pattern increase ratio with self-gating methods at the target stuck-at test coverage (98.3%–99%). Theexperiments were performed with the SG ratio changed from 5% to20%. XOR represents the experiments using the circuits with the XOR

self-gating method. The experiments using the DSSG method weredivided into two classes. The DSSG + R cases are experiments ofthe DSSG test method that do not target redundant SA1 faults. ForATPG efficiency, the fault classes of the SA1 redundant faults in theDSSG structure were predefined to classify quickly and accurately.In the DSSG + D case, the ATPG results for the circuit with theDSSG structure designed to test redundant SA1 faults. As SG ratioincreases, the stuck-at test patterns of the circuits with the XOR self-gating method increase sharply as compared to those of the circuitswith the DSSG method. The average of test pattern increase ratioof each self-gating method is compared in Fig. 10. The average testpattern increase ratio is 91.37% for XOR self-gating, 7.67% for DSSG+ R, and 6.71% for DSSG + D, indicating that the pattern increaseratio is significantly lower when the DSSG method is used.

Table III shows area overhead and delay overhead at the prelayoutand the postlayout for XOR self-gating and the DSSG structures. Forthe comparison, design data of the circuit with NO_SG are used as thereference, and four different SG ratios are used. As expected, the areaoverhead of the DSSG structure is almost the same as that of XOR

self-gating since there is only difference in signal routing between theDSSG structure and the XOR self-gating structure. The performance

1976 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 8, AUGUST 2019

TABLE II

STUCK-AT TEST PATTERN INCREASE RATIO WITH THE SELF-GATING METHODS

Fig. 9. Average of the test pattern increase ratio according to the group size.

Fig. 10. Average of the test pattern increase ratio comparison.

TABLE III

DESIGN OVERHEAD COMPARISON

overheads are compared based on the worst negative slack (WNS) andtotal negative slack (TNS). As a result, the performance overheadsof the DSSG structure also have no significant difference to thereference and XOR self-gating cases. Thus, the design overheads ofthe proposed DSSG structure are similar to those of the existing XOR

self-gating without increasing the number of scan test patterns.

V. CONCLUSION

In this brief, a test-friendly low-power technique called DSSG wasproposed. The DSSG structure is designed to select the data signals

of flip-flops from the functional path or the scan path for clockgating. In the mission mode, the DSSG method is used for dynamicpower reduction by selecting the functional path of flip-flops. In thescan test mode, scan shift path of the flip-flops is selected for theDSSG structure test and the low-power test. Stuck-at test patternscan be generated very easily and rapidly using repeated regular scanshift operations. As a result, the DSSG structure can be tested usingonly four scan test patterns and the number of test patterns can bedramatically decreased compared to those of the conventional XOR

self-gating method. In addition, the DSSG structure can be used inboth test and mission modes. Therefore, the power reduction effectin the scan shift mode can be obtained.

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