Tessent cell library Generation Flow

Tessent cell library

Generation Flow

Marvin.Min

© 1999-2016 Mentor Graphics Corporation. All rights reserved.

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Initial version ………………………………………… 2017.08

Referenced by 2017.3

Edited version …..…………………………………... 2018.09

Referenced by 2018.3

History


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Contents

5 Chapter 4. Insertion Attributes Using Liberty

6 Chapter 5. Simulation Models Using LibComp

7 Chapter 6. Verification of Tessent Simulation models

4 Chapter 3. Cell Library

1 Chapter 0. Tessent Tools Install

3 Chapter 2. Tessent Library Model Information

8 Chapter 7. Shell Command Descriptions

2 Chapter 1. Tessent Library Generation

A Appendix(1), (2), (3), (4), (5), (6), (7), (8), (9)

9 Chapter 8. List of unsupported features of LIBCOMP


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■ Tessent Tool Installation

1) Mentor Support Center에 방문하여 Tool Download. (Tool + PDF Docu.)

1-1) Tessent common files, Documentation, RHEL 6/7 x86-64 or SLES 11u2/12 x86-64.

1-2) ‘tar’ 파일 기준으로 약 1.5GB ~ 2.0GB .

2) Linux rhel6.x 이상에서 install 진행.

2-1) 총 3개의 tar 파일을 각각 extract 한다.

2-2) > ./tessent_2017_2_lnx-x86 실행.

2-3) Dump Agree Automatic installed.

3) 환경파일 setting 및 실행

3-1) “set path = ( /cadtools/Tessent_2017.3/bin $path)

3-2) > source tessent_environment

3-3) > tessent –shell –log xx.log

3-4) install 확인 후 ‘pdfdocs’ 파일은 PC로 copy하여 참조.

Chapter 0. Tessent Tools Install


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4) 라이센스파일 및 세팅

4-1)License file check

4-2)License start/stop

- start : > lmgrd -c ./mentor_tessent.license -l ./mentor_license.log

- stop : > lmdown –c ./mentor_tessent.license

4-3)License(mentor_license.log) check


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5) 환경파일 예제


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6) Tool download

6-1) https://support.mentor.com ID/PW

https://support.mentor.com/


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6-2) select product and select version


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7) Tool community

7-1) detail Q&A : https://support.mentor.com

7-2) simple Q&A : http://www.ednc.com Community 제품 Q&A Tessent 제품관련 Q&A

https://support.mentor.com/

http://www.ednc.com/


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■ Tessent Library Generation/Conversion

1) Definition of Meaning

Tessent cell library is an integrated library format that binds all formats into one.

Tessent cell library is include that the functionality information used for Simulation

and DFT attributes for test logic insertion.

2) Checkpoints

2-1) Old ATPG library(‘.mdt’, ‘.atpg’ )는 FastScan & TK 진행에는 문제없지만 LBIST/MBIST는 문제발생.

2-2) LV flow library(cell.lib, pad.lib, scang.lib)는 Tessent cell library generate 필요.

3) Universal library

verilog

liberty

functionality for simulation

+

test attribute for test logic

Chapter 1. Tessent Library Generation

functionality

test attribute


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4) Useful points

4-1) tessent cell library를 생성하기 전

- Vendor에서 제공해 주는 지 먼저 확인

(STD-CELL, IO, Memory)

- SCAN mode 진행 시 Memory bypass를 이용한다면,

Memory library는 필요없음.

- Library 생성이 필요한 경우 아래 명령을 사용 함.

* > tessent –shell

* > libcomp, lcVerify


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4-2) Lab(2018.3_adk)을 참조

- 모든 과정에서 error가 없으려면,

Tessent license feature 중에 fastscan(TK) 와

Questa simulator license 가 반드시 필요함.

예를들어, MBIST only license를 가지고 있는 user 는

library 생성은 가능하지만, library 의 ATPG certification 은

FastScan license 가 없어서 진행할 수 없으며,

simulation 검증은 생성된 TB를 수정하여 third party simulator

에서 사용해야 함.

- 제공된 dofile 을 잘 활용하고, dofile을 이용하면 write_lib 의

파일이름을 정할 수 있고, dofile 없이 그냥 Verilog source

file 만 읽어서 실행하면 libcomp.atpg 로 생성된다.

실행하게 되면 생성한 후 verify 까지 tool 이 알아서 실행한다.


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5) Technote MG589099 참조.

Library generation method

6) Libcomp 관련 inform. & ref.

“/{installed}/lib/tools/libcomp”

7) Generating step (3 step)


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7-1) Step1 : simulation model 생성 및 검증 (결과:xx.atpg)

For example:

{Tessent_Tree_Path}/bin/libcomp

Verilog_source –dofile –log log_file

libcomp -help

{Tessent_Tree_Path}/bin/lcverify ATPG_library_name Verilog_library_names


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7-2) Step2 : sim. model에 attribute 넣기(add attribute)

- 4가지 방법이 있음. (2016.3이후 liberty를 지원)

7-2-1) method1 : text editor를 이용하여 Manually creation


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7-2-3) method3: LV flow libraries를 이용하는 방법 (LV library + atpg.lib)

7-2-2) method2: simple 혹은 Regular expression을 만들어서 half-automatically insert

7-3) Write cell lib

write_cell_library library_name.celllib

tessent -shell -lib atpg.lib cell.lib pad.lib scang.lib

cell_attributes (

model ("sff.*") (

nonscan_model = dff;

cell_type = scan_cell;

input (D) (data_in)

input (SI) (scan_in)

input (SE) (scan_enable)

//Can also have regexp pinname,e.g.

// "SE.*" for all pins that start with “SE”

output(Q) (scan_out)

output (QB) (scan_out_inv)

)

)


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8) method4: liberty library를이용하여 2-step 진행 (2016.3 부터가능)

- 모든 attribute가 들어갔는지확인해야함.

- Especially : FF, Scan-FF, Mux

read_cell_library uhts_atpg.lib read_liberty uhts.lib write_cell_library uhts_tessent_cell.lib //optional

8-1) Step1 : simulation model 생성 및 검증

- (6-1)과 동일함.

8-2) Step2 : liberty를 이용하여 attribute를 adding (Tessent shell command mode)

9) Example ( “2018.3_adk.tar.gz” )

- 00_run_step0_generate 04_run_WithAttribute

- 00_run_step0_generate 01_run_step0-1_lcVerify 02_run_step1_fastscan 03_run_step2_vsim

04_run_WithAttribute

- *optional : 05_create_padcells_certification_patterns, 06_generate_lv_library


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■ Tessent Library model

1) Library model and attribute

Chapter 2(in the PDF) illustrates the process of creating a simulation model with the necessary

attributes and required model and pin attributes. The source of each step is illustrated for the “How to

Create a Positive-Edge (Nonscan) DFF Cell” on page 26(tessent_lib_user.pdf). All subsequent cell types

illustrate the final result but do not show the source for each step.

Nonscan DFF cell 에대표예제로기술.

2) Example

2-1) Verilog model에 있는 module/endmodule과 primitive/endprimitive 모두 conversion 된다.

source의 module/endmodule은 “model model_name (port_list) (description)”으로 기술되며,

“model_source = verilog_module;” .

source의 primitive/endprimitive는 역시 “model primitive_name (port_list) (description)”으로

기술되며, “model_source = verilog_udp” .

Chapter 2. Tessent Library Model Information


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2-2) Example Attribute : “cell_type”이 없는 cell도 있다.


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3) Attribute

3-1) ‘cell_type = ‘

cell_type = dff, latch, buffer, inverter, and, or, nand, nor, xor, mux

clock_and, clock_or, clock_mux,

scan_cell, prohibited,

clock_gating_or, clock_gating_and,

synchronizer_cell,

pad

3-2) buffer, inverter


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3-3) PAD

3-3-1) input PAD


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3-3-2) output PAD


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3-4) function cells


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cell_type = clock_mux

?


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Chapter 3. Cell Library

■ Cell Library Overview

1) “library” level information

which applies to all subsequent process.

2) ”model” level information

which applies only to a particular model.

3) ”pin” level information

which applies only to a particular pin.


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4) dft_cell_selection

- A ‘dft_cell_selection’ is optional. If not provided, a default dft_cell_selection is created.

If an explicit parsed, no default will be created. You can create an empty,

explicit dft_cell_selection to prevent creation of a default.

- CAVEAT: If multiple posedge_dff are specified for the same dft_cell_selection_name,

the last parsed will be kept as the one to use.

dft_cell_selection(dft_cell_selection_name)

{

posedge_dff = pos_dff_cell;

}

Model

name


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5) Cell attribute


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6) Special attribute

- pad_from_sje_mux : Select JTAG Enable

- pad_from_sji_mux : Select JTAG Input

- pad_from_sjo_mux : Select JTAG Output

- pad_init_clock_dot6 : related IEEE 1149.6 Boundary Scan

7) Special attribute

7-1) Macro

- How to Define Macros - How to Read Multiple Libraries

- “How to Reuse a Model Definition


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7-2) Primitive

- “Verilog Primitives” field 참조(tessent_lib_user.pdf)

- The primitive used to model an AND gate is _and.

- The primitive used to model a NAND gate is _nand.

- The primitive used to model an OR gate is _or.

- The primitive used to model a NOR gate is _nor.

- The primitive used to model an inverter is _inv.

- The primitive used to model a buffer is _buf.

- The primitive used to model a XOR is _xor.

- The primitive used to model a XNOR is _xnor.

- The primitive used to model a tri-state buffer with an active low control is _tsl.

- The primitive used to model an inverted tri-state buffer with an active low control is _tsli.

- The primitive used to model a tri-state buffer with a active high control is _tsh.

- The primitive used to model an inverted tri-state buffer with an active high control is _tshi.

- The primitive used to model a two-to-one multiplexer is _mux.

- The keyword used to define a single or multiple port D flip-flop is _dff.

- The keyword used to define a single or multiple port D latch is _dlat.

- …


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7-3) RAM and ROM

- “RAM and ROM” field 참조(tessent_lib_user.pdf)

T.B.D.


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Chapter 4. Insertion Attributes Using Liberty

1) General Limitations

2) Liberty Pad Information

- Pad Limitations

- Pad Capabilities

3) Liberty Combinational Cell Information

- Combinational Cell Limitations

- Combinational Cell Capabilities

4) Liberty Sequential Cell Information

- Sequential Cell Limitations

- Sequential Cell Capabilities

- For a Liberty integrated clock gating cell


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Chapter 5. Tessent Simulation Models Using LibComp

1) Simulation Model Creation

- Tessent_Tree_Path/bin/libcomp Verilog_source –dofile dofile –logfile log_file

- libcomp -help

2) How to Find Unsupported Constructs in Partial Models

- search the logfile : grep “not translated/supported.” my.log

3) UDP Limitations and Examples

- Seq, Comb, Memory, etc.

4) You can also use LibComp to convert TetraMax Primitives to Verilog Primitives.


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Chapter 6. Verification of Tessent Simulation Models


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Chapter 7. Shell Command Descriptions

1) lcverify

Please see ‘Chapter 7. Shell Command Dictionary’ for see more details.


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2) libcomp

- Generate ATPG library from Verilog.


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Listed below are some of the unsupported features of LIBCOMP:

Unsupported constructs of UDP:

1. SR Latches constructed with complex logic ( i.e. anthing but the trivial case)

2. Mixed level and edge sequential UDP's

A) Characterized by multiple clocks/data pairs where the clocks are edge and level senstive.

B) Cascaded dff followed by a multi-ported latch.

3. Toggle flip-flop, anthing but the trivial case

4. Some complex JK flops.

For all these cases, the tool will insert the Black Boxed for it.

Chapter 8. List of unsupported features of LIBCOMP


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Unsupported Structural code:

1. Following verilog constructs: always, initial, task

2. Actual parameters that are expressions are not supported

( Expressions ( e.g. a & b ) in the actual parameter of a port )

3. Bidirectional verilog primitive

4. Complex constant is not supported in port map statment.

5. Module <module name> refered by instance name

6. Complex read operations of signals are not supported

Error issue, when the operation is NOT one of : LogicalOperation, BitwiseOperation, Assign,

TernaryOperation, ParanOperation

7. Complex write operations to signals are not supported.

Error issue, when the operation is NOT one of : Assign, Signal, Variable and LogicalOperation,

BitwiseOperation, ParanOperation, TernaryOperation

8. Non-logical/bitwise operation is not supported in continous assignment statement.

Array, vector, $<functions> and negative Integers

9. Non-Assign operations is not supported in Continous assign statement.

10. Real types are not supported.


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Appendix(1). Multi-Bit SCAN Cell

1) Multi-bit scan cell : refer “TessentLibraryCreation_Multibit_FF.pdf”

2) 알아야 할 사항(2017.10)

- Single SCAN-IN / SCAN-OUT은 ‘read_liberty’에서 automatically 생성 함.

- Multi SCAN-IN / SCAN-OUT은 manual 생성과 추가 작업이 필요 함.

- ‘tcd_scan’ file을 이용하거나, sub_chains를 이용(add_sub_chains, add_subchain_clocks)

- TSMC는 Single 만 있으므로, testcase는 삼성에서만 검증 가능 함.

3) 추가검토사항 ???

-

www.mentor.com

© Mentor Graphics Corp. Company Confidential

LIBRARY UPDATE

Scan Mapping in Library


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Appendix(2). STD-CELL Library Generation

1) Limitation & Caution

1)

2)


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Appendix(3). PAD Library Generation


1) Limitation

- ‘specify~endspecify’ block은 connection 부분을 제외하고 무시된다.

2) always 문장에서 Warning이 발생하면 partial conversion이 된다. 가능한한 always 문장을 많이

comment 했을 때, scan/atpg등에 문제가 없으면 될 것으로 판단한다.


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1) Memory for SCAN

1) With SCAN Bypass

2) With internal test

Appendix(4). Memory Library Generation


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Appendix(5). Macro Library Generation


1)

2)


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Appendix(6). Debugging – open_visualizer

1) Check

- fault_coverage_0_to_10_percent_models, 20_to_30, 40_to_50 파일 확인.

- sim.log 혹은 verify.results 확인.

- ‘tcd_scan’ file을 이용하거나, sub_chains를 이용(add_sub_chains, add_subchain_clocks)

- TSMC는 Single 만 있으므로, testcase는 삼성에서만 검증 가능 함.

- fault_coverage_0_to_10_percent_models, 20_to_30, 40_to_50 파일 확인 이후,

test coverage 가 낮은 cell 의 경우 아래와같이 따로 하기의 절차로 특정 Cell 만 ATPG를 실행하고,

ATPG 실행후 Open_visualizer 로 DRC check 가 가능하다.

1. fastscan <cell-name> -model –lib <atpg_library-name>

2. analyze_control_signal –auto

3. set_system_mode atpg

4. set_fault_type [stuck|trans]

5. create_pattern

위 1번 항목의 ‘<cell-name>’ 은 verify 를 원하는 library 내의 cell name,

즉 conversion 된 atpglib 내의 특정 model name 을 의미하며,

’<atpg_library-name>’ 은 conversion된 atpglib 를 의미한다.

Open_visualizer

실행 불가

Open_visualizer

를 이용


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Appendix(7).

1) 1st

- 전체 자료 공유 및 기본 문서 리뷰. (숙제:1~3장까지 읽기 이해되지 않는부분 차후 공유)

2) 2nd

- STD-CELL 실행(adk, cl013,cl018). (숙제:4장읽기)

3) 3rd

- IO 실행. (문제점파악, 확인사항정리) (숙제:5장~마지막)

4) 4th

- Memory, Macro 생성방법논의

5) 5th

- 중간정리 (SCAN/TK에서 주의점, MBIST/LBIST에서 주의점)

6) 6th

- 최종정리


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Appendix(8). Example

1) “00_run_step0_generate libcomp 실행 (fastscan + Questa license 필요)

- 입력 : library.v, dofile 출력 : library.atpg, log_file

2) “01_run_step0-1_lcverify fastscan & vsim 실행 (fastscan + Questa license 필요)

- 입력 : library.atpg, library.v, 출력 : sim.log

3) “02_run_step1_fastscan fastscan crosscheck 실행(additional step)

- 입력 : fastscan.do.cat, library.atpg, 출력 : log.fastscan

- comment : write_patterns에서 error가 발생하면, 해당 write_patterns -replace를 추가후 재 실행.

4) “03_run_step2_vsim” vsim single step 실행 (additional step)

- 입력 : pat.v, library.v, 출력 : sim.log

5) “04_step3_run_WithAttribute” Liberty model을 이용하여 scan_insertion attribute 추가

- 입력: dofile, library.atpg, library_worst.lib , 출력 : 최종 tessent shell library

6)최종

- “04_step3_run_WithAttribute“에서 생성된 library.tessent_lib를 이용하여 scan insertion & ATPG 진행


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Appendix(9). Example-II

1) “00_run_step0_generate libcomp 실행 (fastscan 필요)

- 입력 : library.v, dofile 출력 : library.atpg, log_file

‘fastscan’ license 가 없으면 다음과 같은license error 가 발생

Sample dofile example


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Appendix(9). License

1) “00_run_step0_generate libcomp 실행

- comment : 2-step으로 실행 됨.

- 1’st step : translation / run output으로 *.atpg 파일을 생성

- 기본 tessent –shell mode 진입을 위한 tessent feature 하나만 있으면 됨.

- fastscan license 가 없으면, “set verification off”로 하고 실행.

- 2’nd step : lcVerify 각 cell별 atpg를 진행 ‘write library’ 명령이 자동으로 invoke

- fastscan license가 필요, fastscan license가 없으면 *.atpg 파일은 생성되지만 atpg 검증을 할 수

없어서 command error가 발생. 검증없이 tessent atpg library는 만들 수 있다.

Tessent cell library Generation Flow

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