TELEVIDEO® 955 VIDEO DISPLAY TERMINAL MAINTENANCE … · 2018. 3. 18. · This troubleshooting...

TELEVIDEO® 955 VIDEO DISPLAY TERMINAL MAINTENANCE MANUAL

Document l3l968-00-C September 1987

Copyright

Copyright (c) 1987 by TeleVideo Systems, Inc. All rights reserved~ No part of this publication may be reproduced: transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of TeleVideo Systems, Inc., 1170 Morse Avenue, P.O. Box 3568, Sunnyvale, California 94088-3568.

Disclaimer

TeleVideo Systems, Inc. makes no representations or warranties with respect to this manual. Further, TeleVideo Systems, Inc. reserves the right to make changes in the specifications of the product described within this manual at any time without notice and without obligation of TeleVideo Systems, Inc. to notify any person of such revision or changes.

TeleVideo is a registered trademark of TeleVideo Systems, Inc.

TeleVideo Systems,· Inc., Sunnyvale, CA 94088-3568

1170 Morse Avenue, P.O. Box 3568, 408/745-7760

TABLE OF CONTENTS

l.

2.

3.

4.

Troubleshooting Guide Overvi~w

Description of the Modules Logic Board Power Supply Video Module (Video Monitor Board) Kp.yboard

Removinq the Modules Ooening the Case Removing the Power Supply Replacing the Power Supply Removing the Video Module Replacing the Video Module Removing the Logic Board and Shroud Replacing the Logic Board and Shroud Closing the Case Opening the Keyboard Case Removing the Keyboard Circuit

Visual Inspection Terminal and Keyboard Exterior Terminal and Keyboard Interior

Fault Isolation at the Module Level Troubleshooting the Logic Board and Keyboard Troubleshooting the Video Module

Visual Inspection Adjustments

Schematics

Ordering Spare Parts 955 Terminal Spare Parts List 955 Parts Reference List

Theory of Operation Overview Gate Array Logic Board Theory of Operation

Clock Circui.t Clock Switching Clock Stretch Timing CPU System and Control Character Generation Display Generation Screen Data Storage Communications

Enhanced Gate A.rray I.Jogic Board Theory of Operation Clock Circuit CPU System and Control Character Generation Display Generation Screen Data Storage Communications

iii

1-1 1-1 1-2 1-2 1-3 1-3 1-3 1-4 1-4 1-6 1-6 1-8 1-9 1-10 1-10 1-11 1-12 1-12 1-12 1-12 1-13 1-13 1-17 1-22 1-22 1-22

2-1

3-1 3-2 3-5

4-1 4-1 4-1 4-1 4-3 4-4 4-6 4-9 4-10 4-11 4-12 4-13 4-13 4-15 4-19 4-20 4-21 4-22

5 • Service Information Regional S~les Offices

6. Operator's Mnnual

7.A.ddenda Specifications Bulletins

LIST OF TABLES

1-1 1-2

1-3

2-1 2-2 3-1 3-2 4-1 4-2

Fault Isolation Guide Gate Array Logic Board and

Keyboard Troubleshooting Guide Enhanced Gate A.rray Logic Board and

Keyboard Troubleshooting Guide IC Reference (Gate Array Logic Board) IC Reference (Enhanced Gate Array Logic Board) 955 Terminal Spare Parts List 955 Parts Reference List Memory Map Memory Map

LIST OF FIGURES

1-1 1-2 1-3 1-4 1-5 1-6 1-7 4-1 4-2 4-3 4-4

955 Terminal, Front View 955 Terminal, Rear View Discharging Voltages Opening the Case Removing the Power Supply Removing the Video Module Removing the Logic Board and Shroud 955 Block Diagram (Gate Array Logic Board) Clock Switchinq CPU Clock Stretch Timing 955 B10ck Diagram (Enhanced Gate A.rray Logic Board)

iv

5-1 5-1

1-13

1-17

1-20 2-1 2-4 3-2 3-5 4-7 4-16

1-1 1-2 1-4 1-5 1-7 1-9 1-11 4-2 4-4 4-5 4-14

TROUBLESHOOTING GUIDE

This troubleshooting guide was designed for qualified repair personnel. Using this guide, the schematics in Section 2, and an Operator's Manual, you can repair most failures quickly. If difficulty arises, contact your dealer.

STOP! Do not open the case as described in this manual unless you are a qualified service technician. The components exposed during this procedure retain hazardous voltages that are present even after the power cord has been disconnected.

OVERVIEW

TeleVideo's 955, a general-purpose ASCII terminal, is fully codecompatible with our 925/950 family of terminals. The main element in the system is a 65C02 CMOS custom microprocessor. For CRT control, the 955 uses an advanced alphanumeric VLSI CRT controller chip.

Figures 1-1 and 1-2 show front and rear views of the terminal. Ports, switches and connectors are marked.

Figure 1-1 955 Terminal, Front View

CONTRAST ADJUSTOR

ON/OFF SWITCH

KEYBOARD CONNECTOR

1-1

Figure 1-2 955 Terminal, Rear View

POWER CABLE---=:=:::::-_~l""'" SOCKET --__ ~===-~_

Terminal hardware is divided into four main modules:

Main logic board

Power supply

Video module (video monitor board)

Keyboard

This design permits fast fault isolation and keeps repair time to a minimum. To isolate a faulty module, swap a suspected module with a known-good one.

DESCRIPTION OF THE MODULES

Logic Board

The logic board fits inside a tray that slides into the base of the terminal. It is easily reached by removing two screws from the base.

The 65C02 microprocessor-based control circuitry on the logic board, acting on its own internal system program, stores and processes data received and data to be transmitted. The circuitry also generates the video and sync signals needed to display data on the screen.

1-2

The logic board has four distinct interconnected divisions that are discussed in this manualls Theory of Operation section. They are:

Main processor

Display circuitry-processor

Random Access Memory (RAM)

Interface for external input/output

Power Supply

A switching power supply is located in the pedestal below the CRT. It provides the following voltages for the terminalls electronic circuitry:

+ 5V for TTL logic

+12V for the video signals and RS-232C communications

-12V for RS-232C communications

- 5V for the optional modem

Two user-replaceable fuses--Fl on the power supply and a line fuse in back of the terminal--protect the circuitry.

Video Module (Video Monitor Board)

The video module is located behind the CRT. It contains horizontal and vertical sweep and video amplification circuitry. This circuitry produces a television-type noninterlaced raster display. The video signals generated by the display circuitry cause pixels to appear at designated positions across scan lines. These pixels form a character when selectively combined in a 7 x 9 dot rna tr ix.

Keyboard

The 955 has a detachable keyboard connected to the terminal by a coiled keyboard cable.

The keyboard consists of an array of keyswitches mounted on a printed circui~ board with an 8049 microcomputer and other leis.

The 8049 microprocessor on the keyboard scans the keyboard matrix, encodes the data and transmits two bytes per character requested. Data is sent through a 6-wire coiled cable over an asynchronous serial channel at 9600 baud to the main logic board.

The keyboard microprocessor also activates an audio transducer for the bell and the simulated keyclick.

1-3

On the main logic board, the serial data is converted to parallel data and decoded by the main microprocessor and its firmware.

REMOVING THE MODULES

Opening the Case

STOPl The CRT and capacitors retain high voltages even after power has been turned off. As soon as you open the case, discharge the CRT by connecting one end of a grounding l~ad to the metal chassis and the other end to a screwdriver with an insulated handle. Slip the metal end of the screwdriver under the plastic cap of the anode, as shown in Figure 1-3. Be careful not to touch the metal portion of the screwdriver or the ground lead.

Figure 1-3 Discharging Voltages

CRT ANODE

1 INSULATED HANDlE

SCREWDRIVER

METAL FRAME

Use Figure 1-4 as reference for opening the case.

1. Turn off the terminal.

2. Disconnect the power cord and data cable(s) from the back of the termina17 disconnect the keyboard cable from the front of the terminal.

3. Turn the terminal so the screen faces away from you.

1-4

4. Remove the three screws securing the monitor rear housing to the case (remove the screw under tne power cora r1rst, then remove the two screws near the top of the housing).

NOTE: Remove the screws completely. If necessary, tip the unit backwards slightly.

5. To release the clamp holding the bezel and monitor rear housing together (See Figure 1-4):

a. Grasp the housing with your left hand.

b. Sharply tap the right side of the housing with the heel of your right hand.

6. Lift off the monitor rear housing.

Figure 1-4 Opening the Case

PRINTER PORT

1-5

Removing the Power Supply

STOPl The CRT retains high voltages, even after the power has been turned off, and poses a potential shock hazard. Follow the CRT discharge procedure on page 1-4 of this section before removing and replacing the power supply.

Use Figure 1-5 as reference for removing and replacing the power supply.

1. Turn off the terminal and open the case (See page 1-4).


3. Remove the two Phillips screws securing the bezel to the case (the screws are located inside the case, one on each side of the power supply).

4. Disconnect the Ground connector, the power connector (P4) and the DC connectors (P1, P2 and/or P3) from the power supply.

NOTE: Only two connectors are attached at PI, P2 and P3. Pay close attention to the polarity for reference during reassembly.

5. Turn the unit so the screen faces you. Remove the two Phillips screws securing the power supply to the case.

6. Slide the power supply toward you to remove it from the case.

Replacing the Power Supply

1. Turn the unit so the screen faces you. Slide the power supply into the terminal until it locks into the plastic support bracket.

2. Reconnect the Ground connector, the power connector (P4) and the DC connectors (PI, P2 and P3).

NOTE: Any of the three connectors may be used. For example, you may take the connectors off Pl and P2 and replace them on P2 and P3.

3. Insert and tighten the two Phillips screws securing the power supply to the case.

4. Replace the bezel and monitor rear housing and close the case (See page 1-11).

1-6

Figure 1-5 Removing the Power Supply

•

FRONT VIEW

Pi

P2

POWER SUPPLY

POWER CONNECTOR (P4) __ :::::::::---tii"~"",,!!!!!,;;::."~!!!!!!!!!!!!!~~-:;

BACK VIEW

1-7

Removing the Video Module

STOP I The CRT retains high voltages, even after the power has been turned off, and poses a potential shock hazard. Follow the CRT discharge procedure on page 1-4 of this section before removing and replacing the video module.

Use Figure 1-6 as reference for removing and replacing the video module.

1. Turn off the terminal and open the case (See page 1-4).

2. Turn the unit so the screen faces away from you.

3. Disconnect the voltage lead at the anode by gently lifting the rubber cap and unhinging the metal lead.

4. Carefully remove the CRT connector (small PC board at the back of the CRT).

5. Remove the power connector (red), the video connector (white) and the yoke connector (blue) from the video board.

6. NOTE: In some 955 terminals the video module is on a base that slides up and down~ in others, the video module is on a hinged base.

To determine which model you are working on, check below the video module. If there are three screws below the module, go on to the next step. If not, go to step 9.

7. Remove the two Phillips screws (one on each upper support bracket) holding the video module in place.

8. Remove the middle screw below the module and loosen the screw on each side of it. This allows the video module to slide down.

9. If the model you are working on is hinged, you must remove four screws.

a. Remove the screw on each side of the plate holding the video module in place.

b. Remove the two screws (one below the other) on the right side plate.

10. Remove the four Phillips screws holding the video board to its base~ slide the board out of the terminal.

1-8

Figure 1-6 Removing the Video Module

t+----VIDEO MODULE

Replacing the Video Module


2. Slide the video module onto its base (See Figure 1-6) until the four screw holes in the board line up with the four screw holes in the base.

3. Insert and tighten the four Phillips screws holding the video module to its base.

4. Reconnect the power connector (red), the video connector (white) and the yoke connector (blue) on the video module.

5. Carefully replace the CRT connector (small PCB at the back of the CRT).

6. Replace the anode cap:

a. Pull back the rubber portion of the anode cap, exposing the metal leads.

1-9

b. Pinch the two leads together and insert them into the opening for the anode cap in the CRT. Release the leads.

c. Secure the rubber portion of the anode cap.

7. Insert and tighten the Phillips screws securing the module to the case. See step 6 (Removing the Video Module) if you are replacing the sliding module. See step 9 if you are replacing the hinged module.

8. Replace the bezel (if removed) and monitor rear housing: close the case (See page 1-11).

Removing the Logic Board and Shroud

Use Figure 1-7 as reference for removing and replacing the logic board and shroud.

1. Turn off the terminal. Disconnect the power cord and data cable(s) from the back of the terminal: disconnect the keyboard cable from the front of the terminal.

2. Rotate the complete unit so the back faces you. Remove the two Phillips screws (in the base) holding the logic board tray in place.

3. Grasp the logic board tray by its center tab~ pull the tray toward you. Disconnect the red (P5) and white (P2) logic board connectors to slide the tray completely out of the terminal.

4. Remove the four brass screws securing the shroud to the logic board; remove the six Phillips screws securing the logic board to the tray.

5. Lift the logic board out of the tray.

Replacing the Logic Board and Shroud

1. Align the six screw holes in the logic board with the screw holes in the tray.

2. Loosely mount the six Phillips screws holding the logic board in place: insert and tighten the four brass screws holding the shroud to the logic board, then tighten the six Phillips screws securing the logic board.

3. Replace the logic board tray in the base:

a. Fit the metal flanges on the logic board tray into the guides at the back of the terminal. Hold the connector cables up so t.hey do not interfere as you replace the tray.

1-10

b. Reattach the red connector (P5) and the white connector I _ "'" \ _ _ _ I' _ _ , _ __..! _ '- _ _ __ ~

\~~J on ~ne LOgl~ UUdLU.

c. Align the keyboard connector with the opening in the front of the terminal.

4. Insert and tighten the two Phillips screws holding the logic board tray in the base.

Figure 1-7 Removing the Logic Board and Shroud

• 9

LOGIC BOARD ~J~iiiiii~'ii~~~~~~:::~ '~~ LOGICBOARDTRAY/ " /

'------PHILLIPS SCREW

Closing the Case

1. Replace the bezel:

a. Place the bezel face down in front of the terminal. Raise the bezel slightly and hook its two bottom tabs into the openings (one under the contrast adjustor; one under the ON/OFF switch) in the lower case.

b. Swing the bezel up to frame the screen, matching the ON/OFF switch and contrast adjustor with the openings in the bezel.

1-11

c. Carefully turn the screen away from you while holding the bezel in place. Insert and tighten the two Phillips screws securing the bezel to the case (these screws are located inside the case, on on each side of the power supply).

2. Replace the monitor rear housing:

a. Position the monitor rear housing on the case, as shown in Figure 1-4.

b. Al ign the screw hole under the power cord wi th the lower screw hole in the housing.

c. Fi t the four tabs in the hous ing over the edge of the lower case.

d. Fi t the tab in the top of the beze 1 into the s lot in the top of the monitor rear housing. Squeeze the bezel and housing together.

e. Insert and tighten the Phillips screw under the power cord and the two Phi 11 ips screws near the top of the housing.

Opening the Keyboard Case

1. Disconnect the coiled keyboard cable from the front of the terminal.

2. Turn the keyboard upside down and remove the six Phillips screws.

3. Turn the keyboard rightside up and remove the top cover.

Removing the Keyboard Circuit

1. Remove the four Phillips screws securing the keyboard circuit.

2. Lift the entire assembly out of the keyboard case.

VISUAL INSPECTION

A thorough visual inspection often makes the difference between success and failure in a repair attempt. Often a problem can be located just by close visual examination.

Terminal and Keyboard Exterior

Look for signs of accidental damage, abuse, or neglect. Keyboard failures are often caused by spilled liquids, sprayed cleaning solvents, staples, or paperclips.

1-12

Are there any dents or deep scratches on the exterior of the terminal or keyboard? If so, ask the user how and when the damage occurred. It may contribute to the problem with the unit.

Terminal and Keyboard Interior

Open the cases and inspect the keyboard and terminal interiors.

Keyboard: Check for signs of spilled liquids, foreign objects, unplugged devices, defective traces, and signs of overheating and burning. Check the telephone-style connectors (located on the back of the keyboard case and on the front of the terminal).

Wiring Harness: Check the condition of the wires and look for crushed insulation, exposed wires, and loose or broken connectors. Unplug the connectors and check that the pins are intact.

Logic Board: Check for loose chips, bent pins on chips, defective chip sockets, signs of overheating and burning, defective traces, and poor solder joints. Check that devices are properly installed.

Power Supply: Check for open fuses, defective components, and signs of overheating and burning.

Video Module: Check for defective components, signs of overheating, and defective traces.

Remove all defective modules for closer inspection and repair. When you finish the repairs, replace the module(s) and test them.

FAULT ISOLATION AT THE MODULE LEVEL

TeleVideo's modular terminal design makes isolating a problem to a particular module easy. You can either follow Table 1-1, Fault Isolation Guide, or replace each module in turn until the fault is corrected.

To use Table 1-1, find the description that resembles the problem in the terminal. Then, if applicable, refer to the troubleshooting guide for the suspected module.

Table 1-1 Fault Isolation Guide

Symptom

No beep on power up

1-13

Suspected Module

Logic board Line fuse Power supply Keyboard

Table 1-1 (Continued) Fault Isolation Guide

Sywaptom.

No video, no cursor

No external communication

Incorrect characters

Incorrect attributes

No keyboard communication

Fails to reset properly when CTRL RESET is pressed

No baud-rate selection

Power supply fuse blowing

Line fuse blowing

High-pitched whine

Distorted video

Characters missing dots

Display too dim/can't adjust

Video fades

Suspected Module

Logic board Power supply Video module CRT

Cable to host Logic board Power supply (-12V)

Logic board Keyboard

Logic board

Logic board Keyboard cable

Keyboard (See Service Bulletin number 65*

Logic board

Video module Power supply

See Service Bulletin Number 63*

Video module

Video module Power supply Logic board

Logic board Defective CRT

Video module Power supply

Check that video module has been modified as described in Service Bulletin Number 67*

*Section 7 (Addenda) contains Service Bulletins applicable to the 955 terminal.

1-14


Symptom

Online communication problem

Garbled date, missing data, "p3ER" error message (revision C and D logic board only)

False "p3ER" error when using main RS232 port (in block mode and half-duplex with pins 4 and 5 jumpered)

Jittery screen

Wavy screen

Incorrect voltages

No light at cathode filament

Display not equal to key entry

Visible retrace scanlines

Keyboard locked up

Fails

Some keys inoperative

Suspected Module

Logic board Cable to host Host

Logic Board (See Service Bulletin Number 64*)

Logic board (See Service Bulletin Number 58*)

Video module Hertz setting

Video module Power supply External interference

Power supply

Video module Power supply Defective CRT

Logic board Keyboard cable Cable to host Host

Brightness adjustment Video module Logic board

Keyboard cable Keyboard Logic board Software command

Logic board Power supply (+5V) Keyboard

Keyboard Logic board


1-15


Symptom

Horizontal bar across screen

Poor linearity

Cursor moves, no characters

Vertical line across screen

Crackling sound with distorted video

1-16

Suspected Module

Logic board Video module

Video module

Logic board

Logic board Video module Yoke

Video module

TROUBLESHOOTING THE LOGIC BOARD AND KEYBOARD

This section is a guide to component-level repair of the logic board and keyboard modules.

Determine the type of logic board in your terminal, then refer to Table 1-2 or Table 1-3 to locate the suspected defective component:

For Gate Array models (part number 132160-00 - Gate Array location U34), use Table 1-2.

For Enhanced Gate Array models (part number 132880-00 - Gate ~rray location U37); use Table 1-3.

NOTE: You can also determine the type of logic board by comparing the board to the illustrations in Section 2 of this manual.

If you are not sure that a component is satisfactory, replace it before proceeding to the next test point. Befor~ replacing a chip or component, check its inputs and outputs for proper levels and signal quality.

Table 1-2 Gate Array Logic Board and Keyboard Troubleshooting Guide

Symptom

Display/Video

No display, no beep, fails self test

Distorted video

Incorrect characters

1-17

Component

65C02 Gate Array 2674 Sys. Eprom

2674 2732 6116 74LS374 Gate Array

2732 65511\ Gate Array 74LS374 6116 74AS194 Sys. Eprom 8049 (Kybd)

Location Page

Ul 2 of U34 4 of U14 3 of U4, US 2 of

U14 3 of U45 4 of U6 2 of U33 4 of U34 4 of

U45 4 of U9 6 of U34 4 of U32 4 of U6 2 of U37, U42 4 of U4, US 2 of U2 KYBD

6 6 6 6

6 6 6 6 6

6 6 6 6 6 6 6

Table 1-2 (Continued) Gate Array Logic Board and Keyboard Troubleshooting Guide

Symptom

Display/Video

Horizontal bar across screen

No vertical sync

No cursor

Loss of attributes

Co .. unications

No full-duplex communication (FOX) at P3

No full-duplex communication (FOX) at P4

No status signal transmitted (OSR, OCD, CTS, DTR)

No status signal received (OCD, CTS)

Garbled data, missing data, up3ER" error message (revision C and D logic board only)

False up3ER" error when using main RS232 port (in block mode and half-duplex with pins 4 and 5 jumpered)

Component

2674 Gate A.rray 74LS32 74LS08

2674 7406 Gate Array

2674 65C02

2674 Gate Array Sys. Eprom 65C02

6551A 1488 1489

655lA 1488 1489

1488 6551A

1489 6551.A.

Location

U14 U34 U43 U44

U14 U28 U34

U14 Ul

U14 U34 U4, U5 Ul

Ull U3 U7

UIO U3 U8

U3, U12 Ull

U7, U8 Ull

Schematic Page

3 of 6 4 of 6 3 of 6 4 of 6

3 of 6 3 of 6 4 of 6

3 of 6 2 of 6

3 of 6 4 of 6 2 of 6 2 of 6

6 of 6 6 of 6 6 of 6

6 of 6 6 of 6 6 of 6

6 of 6 6 of 6

6 of 6 6 of 6



*Section 7 (Addenda) contains Service Bulletins applicable to the 955 termin::tl.

1-18

Table 1-2 (Continued) Gate Array Logic Board and Keyboard Troubleshooting Guide

Symptom

Keyboard

All keys inoperative

One or more row of keys inoperative

One key inoperative

SHIFT, CTRL, ALPHA LOCK, and function keys inoperative

No keyclick/no beep


Component Location

6551A U9 74LS32 U23, U47 Gate Arrrty U34 8049 (Kybd) U2

65517.\ 74LS32

6551A Keyswitch

U9 U23, U47

U9

8049 (Kybd) U2 74LS145

(Kybd) 74LS32

U3 U23, U47

6551.A U9 Sys Eprom U4, U5 74LS145

(Kybd) U3

Transducer (Kybd)

2N4401 (Kybd) Ql

74LS32 U23 6551A U9 8049 (Kybd) U2

Schematic Page

6 of 6 6 of 6 4 of 6 4 of 6

6 of 6 6 of 6

6 of 6

KYBD

KYBD 6 of 6

6 of 6 2 of 6

KYBD

KYBD

KYBD 6 of 6 6 of 6 KYBD



1-19

Table 1-3 Enhanced Gate ~rray Logic Board and Keyboard Troubleshooting

Symptom Component Location Page

Display/Video

No display, no beep, 65C02 U4 2 of 5 fails self test Gate Array U37 4 of 5

2674 U28 3 of 5 Sys. Eprom U14, U15 2 of 5

Distorted vi<ieo 2674 U28 3 of 5 2732 U46 4 of 5 6116 U16 2 of 5 74LS374 U33 4 of 5 Gate Arrav U37 4 of 5

Incorrect characters 2732 U46 4 of 5 6551~ U20 5 of 5 Gr:ite Array U37 4 of 5 74LS374 U47 4 of 5 6116 U16 2 of 5 74F166 U38 4 of 5 Sys. EproM U14, UlS 2 of 5 8049 (Kybd) U2 KYBD

Horizontr:il bar across 2674 U28 3 of 5 screen Gate Array U37 4 of 5

74LS32 U18 3 of 5

Nn vertical sync 2674 U28 3 of 5 7406 U40 3 of 5 Gate Array U37 4 of 5

No cursor 2674 U28 3 of 5 65C02 U4 2 of 5

Loss of attributes 2674 U28 3 of 5 Gate Array U37 4 of 5 Sys. Eprom U14, U15 2 of 5 65C02 U4 2 of 5

Communications

No full-duplex 6551A U22 5 of 5 COMMunication (FOX) at P3 1488 U17 5 of 5

1489 U9 5 of 5

No fu11-auplex 6551A U21 5 of 5 communication (FDX) at P4 1488 U17 5 of 5

1489 U5 5 of 5

1-20

Table 1-3 (Continued) Enhanced Gate Array Logic Board and Keyboard Troubleshooting

Symptom Component Location

Communications

No status signal transmitted 1488 U13, U17 U22 (DSR, DCD, CTS, DTR) 655lA

No status signal received 1489 U5, U9 U22 (DCD, CTS) 6551A

Keyboard

All keys inoperative

One or more row of keys inoperative

One key inoperative

SHIFT, CTRL, ALPHA. LOCK, and function keys inoperative

No keyclick/no beep

6551A U20 74LS32 Ull GateA.rray U37 8049 (Kybd) U2

6551A. 74LS32

U20 Ull

6551A U20 Keyswitch 8049 (Kybd) U2 74LS145

(Kybd) U3 74LS32 Ull

655LA. Sys Eprom 74LS145

(Kybd)

Transducer (Kybd)

2N4401 (Kybd)

74LS32 6551A 8049 (Kybd)

U20 U14, U15

U3

Ql Ull U20 U2

Schematic Page

5 of 5 5 of 5

5 of 5 5 of 5

5 of 5 5 of 5 4 of 5 KYBD

5 of 5 5 of 5

5 of 5

KYBD

KYBD 5 of 5

5 of 5 2 of 5

KYBD

KYBD

KYBD 5 of 5 5 of 5 KYBD




1-21

TROUBLESHOOTING THE VIDEO MODULE

STOPl HIGH VOLTAGES ARE PRESENT ON THE VIDEO MODULE. USE EXTREME CARE DURING TROUBLESHOOTING.

Visual Inspection

Turn the terminal off and remove the monitor rear housing, as described in Section I of this manual (Removing the Modules). Check the following possible problem areas before removing the video module from the terminal.

a. Connectors: check for loose or damaged connectors, dirty contacts or bad crimps.

b. Wires: check for any broken, loose or frayed wires.

c. Components: check for any deformed, leaking or discolored components.

Correct any defects, then retest the terminal before continuing.

Remove the video module from the terminal, as described on page 1-8. Inspect the video module for:

a. Deformed, leaking, or discolored components.

b. Damaged- components.

c. Cracked or lifted traces.

d. Poor solder joints (loose solder lumps, solder bridges, or cold solder joints).

Adjustments

Four adjustments can be made to the video module: height, linearity, brightness and focus (VR2). These controls are labeled on the video module. Use the following chart to determine the proper control to adjust.

Syaptoa

Character intensity too bright or too dim

Whole screen is too taIlor too short

Characters are not even in height from the top to the bottom of the screen

Characters are not in focus

1-22

Control

Brightness

Height

Linearity

Focus

This section is a guide to component-level repair of the video modUle. Wnen in doubt regarding the proper operation of a component, replace it before proceeding to the next test point. Before replacing a chip or component, check its inputs and outputs for proper levels and signal quality.

Symptom: No vertical deflection

1. Check IC-l for vertical sync.

2. If the signal is improper or missing, trace back to PIO for vertical sync at pin 5.

3. If the signal is good, trace forward to IC-l, and related components up to the vertical yoke.

Symptom: No horizontal deflection

1. Check the base of Q301 for horizontal sync.

2. If the signal is improper or missing, trace back to PIO for horizontal sync at pin 1.

3. If the signal is good, check the output of the horizontal drive transformer T301 and the base of Q302. Trace for the presence of horizontal deflection through Q302, C306, L30l, and L302 up to the horizontal yoke.

Sympto.: Audible high-pitched whine

1. Check coils L301, L302, and flyback transformer.

Symptom: Video fades after a few minutes or after several hours.

Check that the video module has been modified as described in Service Bulletin Number 67*.


1-23

SCHEMATICS

This section contains schematics and silkscreens of the 955 1 s major modules. For a brief description of the chip at each location on the logic board, determine the type of board in your terminal, then refer to Table 2-1 or Table 2-2.

For Gate Array models (part number 132160-00 - Gate Array location U34), use Table 2-1.

For Enhanced Gate Array models (part number 132880-00 - Gate Array location U37). use Table 2-2.

NOTE: You can also determine the type of logic board by comparing the board to the illustrations in Section 2 of this manual.

Refer to Section 3 of this manual for component part numbers.

Table 2-1 IC Reference (Gate Array Logic Board)

Location Page

Ul 2

U2 2

U3 6

U4 2

U5 2

U6 2

U7 6

U8 6

U9 6

UlO 6

Ull 6

U12 6

U13 1,2,4

U14 3

U15 2

Type/Description

MICROPROCESSOR 65C02 3MHZ

74LS139 2X 1 OF 4 DECODER

75188 4X LINE DRIVER

SYSTEM EPROM 955

SYSTEM EPROM 955

2K x 8 CMOS STATIC RAM

75l89A 4X LINE RECEIVER

75l89A 4X LINE RECEIVER

SY655lA/1 2MHZ SYN/AMI (KEYBOARD UART)

SY655lA/1 2MHZ SYN/AMI (PRINTER UART)

SY655lA/1 2MHZ SYN/AMI (HOST UART)


74LSOO 4X 2-IN NAND GATE

2674 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)

74LS273 8X D-TYPE FLIP-FLOP

2-1

Table 2-1 (Continued) IC Reference (Gate Array Logic Board)

Location Page Type/Description

U16 3 74LS157 4X 2-IN DATA SELECT MULTIPLEXER


UlS 3 74LS245, N8T245N

U19 2,4 74HC04 HEX INVERTER

U20 3 74LS245, N8T245N

U2l 3 74LS157 4X 2-IN DATA SELECT MULTIPLEXER


U23 2,5,6 74LS32 4X 2-IN OR GATE

U24 1,2,4,5 74LS02 4X 2-IN NOR GATE

U25 3 STATIC RAM 2K x S lOOns.

U26 3 STATIC RAM 2K x 8 lOOns.

U27 2 74LS32 4X 2-IN OR GATE

U28 1,2,3,4 7406 6X INVERTER BUFFER/DRIVER

U29 1 8211 PROG VOLTAGE REGULATOR

U30 3 STATIC RAM 2K x 8 lOOns.

U3l 3 STATIC RAM 2K x 8 lOOns.

U32 4 .74LS374 8X D-TYPE FLIP-FLOP

U33 4 74LS374 8X D-TYPE FLIP-FLOP

U34 4 GATE ARR11.Y TVI 16

U35 1,4 74LS374 ax D-TYPE FLIP-FLOP

U36 4 74AS194 4-BIT SHIFT REGISTER


U38 5 74LS74 2X D-TYPE E-TRIGGERED FLIP-FLOP

U39 5 74LSOO 4X 2-IN NAND GATE

2-2

Table 2-1 (Continued) IC Reference (Gate Array Logic Board)


U40 5 74AS163 SYNC 4-BIT COUNTER

U41 5 74851 AND-OR INVERTER GATE


U43 3 74S32 4X 2-IN POS OR GATE

U44 3,4,6 74LS08 4X 2-IN AND GATE

U45 4 ROM 955 CHARACTER GENERATOR


U47 1,6 74LS32 4X 2-IN OR GATE

U48 3,4,5 74S04 6X INVERTER

2-3

Table 2-2 Ie Reference (Enhanced Gate Array Logic Board)

Location

U2

U3

U4

U5

U7

U8

U9

U11

U13

U14

U1S

U16

U17

U18

UI9

U20

U21

U22

U23

U24

U25

U26

U27

Page

1

1,2

2

5

1

1,5

5

2,5

5

2

2

2

5

3

2

5

5

5

1

1,2,5

3

3

3

Type/Description

8211 PROG VOLTAGE REGULATOR

74LS132 4X 2-IN NAND SCHMITT

65C02 MICROPROCESSOR 3 MHZ

75189A 4X LINE RECEIVER

7406 6X INVERTER BUFFER/DRIVER

74LS08 4X 2-IN AND GATE

75189A 4X LINE RECEIVER

74LS32 4X 2-IN OR GATE


SYSTEM EPROM CO-FF

CALCULA.TOR EPROM

STATIC RAM 2K X 8 CMOS 150ns


74S32 4X 2-IN POS OR GA.TE

74LS139 2X 1 OF 4 DECODER

SY6551A/I 2 MHZ SYN/AMI (KYBD UART)

SY6551A/1 2 MHZ SYN/AMI (PRINTER UART)

SY655IA/1 2 MHZ SYN/AMI (HOST UART)

74LS163 SYN 4-BIT COUNTER

74LS32 4X 2-IN OR GATE

74LS245, N8T24SN 8X BUS TRANSCEIVER

74LS157 4X 2-IN DATA SELECT MULTIPLEXER

74LS157 4X 2-IN DATA SELECT MULTIPLEXER

2-4

Ie Reference (Enhanced Gate Array Logic Board)


U28 3 2674 ADV~NCED VIDEO DISPLAY CONTROLLER (AVDC) 4 MHZ

U29 1,2,5 74HC04 HEX INVERTER

U30 3 74LS245, N8T245N 8X BUS TRANSCEIVER





U36 3 STATIC RAM 8K X 8 lOOns CMOS

U37 4 G~TE ARRAY TSI-19

U38 4 74F166 8X SHIFT REGISTER


U40 3,4 7406 6X INVERTER BUFFER/DRIVER

U42 ' 3,4 74LS08 4X 2-IN AND GATE

U43 3,5 74LS32 4X 2-IN OR GATE

U44 2,3,4 74LS04 6X INVERTER

U45 3 STATIC RAM 8K X 8 lOOns CMOS

U46 4 CHARACTER GENERATOR


U48 3,4 74LS74 2X D-TYPE E-TRIGGERED FLIP-FLOP

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~OE 10 GND

+ 5 V._~VV"V-----<II -bL....-------I • R I >82

-= U48 LS(J4

6 7 A I 9 8 Ael 12 18 OE

20 CE fGND ~ R4 <' 82

U44

+5V

~VCC D 1 ~ 3 OA D2~1~1---+_r__T-~4~DB D3 13 5 DC 04 14 6 DO

'--_--::2--1 S I ~-----,--g-:150

10 51 II C K

CLR I

U37

QO~

ASI94

SI94

05 15

D6~ D7~ r ~G_N_D __ ---I

R PI (8) 4.7K

J\!'y. -t5V

RPI(9)

4.7K .. +5V

'5 16 CUR::. BLK vee ~---"BLANK HALF 8

r------I------------t---r-------:;2)11' DOT srn I N TE.NSITY r-=-~--~--------~-j-~~RA0

~ RA2 U34 ~ RA3

.-------+------------t---r-------.10~ BUNK eLK '---+-----:;, 3;;-1 DCC

6 ..------I------t DIS PE N VIDE.o 2-

.-~------------------~-j--1~9ICURSOR ~l-l-~+-~-+------------------4-~4_+-t--1~-----------------Ii--II--~'~~5yNC 5

.-I-------------------t----r-----:;4~tv S''f Nt:: COM P VI D r---+5V

~vcc "------t-t-----t-+--------:;3110 A

4 L--~r1-+-~5~DB

-I ClR-

U42

+5V

~VCC 1--=°---------;3;-;00

I 4 '-'-----::7=--1 U 3 5

'---_3""""17 5YS RESET

Q~ 2 38 CHAD 0 ,~ 5 39 G\ AD \ 02. VI ~2:::....=..3-----3-8-.4-K ~6~1--____ ~3~CHAD2 9 2 36 XTAl 1/2

SH.3 HSYNC 5 ~ 5 ~---~-TII---' 6

"------~-+_r+-~~DC ~OO

12 QOD OC~-~ 2 8 LS374

1\'---~---1----=3----t ~-t-------:-1 C\.lAD 3 DlSP RAM ~3::":4=---------... 1-"'.2+--____ 1 4::1 C 'rip., \:, -, 011--:'-:'-

4 lS08~-----' L-------==2'--i5 I ~ __ 9-;50 ASI94

~0~c~c------~-~-----------~_t~--------------------+-j_----1111051 ~ SH.5 DOT ClK liCK SH.5 ~~~--------~~----------~-r+-+-----------------~-----~~8 GND

5

SH.3 CURSOR

SH.3 VSyr-JC

I 7 I I I I

14 D5 17 06 18 D7 II CK

~I---=5+_------'1-"2_; ATT R/W ~ 27 16

r-----=--

~OE 10 GNO

~ R2 82

Q7~

'--------_~A\.~

31 All BNK INi---II 40 .--------:-102 925/920 ~ ~_9--{30\N/WOB ffi 2 I~~ I

~ LI NLI PG An GNO 13"3 R Sl~/92= SDR ~

4C-7F ~

UICj --= ~C04 11"'--'0 ~ /~~r8'---__.___; :X~}----------'

I v Y3 UI~ 3.6864 HC04

~ 0 I------< C 5 R2.r

~ 47K 10.001

P2 - 3

P2-4

PII- 20

SH. 5

SH. I

SH.I

SH 1,6

o

c

B -

8 1 7 I 6 I 5 1 4 I 3 I 2 J 1 I I ECO NO. I DATE I APPROVED APPLICAnON REVISION DESCRIPTION

HEn AUT! ~~~N S,E:E S,H ;

I I I 1 I

-SH.2 80/132

D D RPI (10) 4.7K

.A +5V lillY

U38 ~~ LS74

2D 5 I- 4 U39 L! U41 3 CK 9 6 ~3 6 13

+ 5V - 7GND Q~ 5 L500L.-. U48 jl4

I--

U39 504 I 8 P-£>o4 2 VCC

- 5 10

8 9 U 41 - 9 L500 5

4 LS32,.... 6

~ LS51 4 551 6 DOT CLK U39 SH. 4 U23

~

C C GND

+ 5V J! 114 + 5V -

il4 YI Wl3 I Ic:r33g0 8 I 2

Y2 MHz

I L RI0 U40 DCC

31.084 + 5V A5163 SH. 4 -

MHz :>82

6. VCC

I--+5V U48

<:>R9 ! U 38 RP2 (3) S04

~ L574 IK ->82 - l! 10 . .A" "- 7 TC

15 2 DCC SH. 4 14 r--_o.......;;.... +5V 'tIVV 10 CEP ""

1 s 9 CET -'--

::!! - ,Ep ~rs ~ P3

9· - PE -

9 UZ4 II .r-K_ Q 5 P2 -

COMM R 4 PI 13 II .I~ Ql 5H. 2

~C3' 1..---13 SH. 3

B 3 P0 U48 --1 MR Q2

12 S04 CCLK SH. 3 B 147Pf

2 J"'K - ~;ND

I---

5H. I SYSTEM RESET -:..= I---

U48 504

9 ~8 (ClK SH.4 .~

1 - U39

~

I 13_ ~II 00 5H. 2

A A .'/ TOl..EMNCtS cJ'-ILE5.S lIIO-EO / CONT~"CT

NUltol8ER O,leleVideo Systems, Inc.

7 DES lOATE "" 0 LY I, . 2~:8""

OoliTE PC B SCHEMATIC DIAGR.A.M """Fl_ .. CH. 10ATE F·"' ......

~~=Te;T~! ~ ~:,iU~ xx. ~ ___

E"". lOAn 9:='S CONTROL BOARD

I"'''OPM .. ~ Ht-i1C~ !! CONJ"'jEN"'AL Of'iilGIOf ACT y'~ "ppqo""'l SIZE: CODEIDENT ~ 3 6 - 00 ~ REV ANO lIIA()&'AIe-.ur.., ·0 -e ... E~·DEO "ICl ~ •• 1_

PAfI'T '7 ' .. ··"5 'XlC1,/WF.!'t ~ \1160 T M ':OP'ED D i 1 21 )-~PAOOVCfO ')PI :;!"iG..::>')C) Tl'J ....... ,P() _ .... S·()l.oER .. pOq() ... Al ~ P"R'T'E!NI'·IoiOt.. ... • .. E~,...,....'f~

~lE5 --COHSfoer ":JF ·Elf_ ~.:t:'".; 'Y"~EW:S ,...c ~."E .. lLfllrR~

[SHEET 5 "NO S~.Af' EDGe, SCALE .... ONE OF "

8 I 7 I 6 f 5 I 4 T ~ '} I 1

I 6 ! 5 4 I 3 1 2 1 1

JIUt"""l':.. A PROD RElEA5E 2661 'r~~ - ~ e. ..... ~ ""' ... ~ F ..... P£. .... 1l.<:'O ~<'''IT I tiifaor . .-.J

C BEL~V C FAB SMALL BD lB20T ,.Ik~! Y

E RI..L REV Q F .... t:, PE.1't.. E.C.o '2.'300T WI c...cl ~

F ADD C:41 PER EC.O ?1035T 'Io/I{ "" ~< Go R&.V Rlq 4 ,JU .... PER:!!> ~I~:.,. 9~'~CY

o H OIEL R2S P"~ Ii ~c !So22:Z. "1"'1'-1 -~ D

-

G

--

B

-

-

PI-6

t5V

+5V

RI9 'I.SK >

RIB ~ 1M

Is 3 U29

La211

2

R20 471< .... v

CR9 IN914

,~

C28 I,L r'+

UI3

CR!! ~

11'1914

+5V

r---

> R37

~

C37 + If'! I

-=-

U28 7406

4.7K

~ 5V

1 "~~-4 R35 "Aft Q4 'VV

10K 21'12222

CRa ,,~p 5_ KBO RST 1~5811 v4'.7K 4ILSW-o-6 __ 1-1 -( ~_O __ 10_-'-"""'_--+---<P---4S~Y..:..S_T.::..E_M ...... R ...... E=-S:....:E=-T_

R21 < 4.7 K <

<

~---------I~--~-------------~----~-~--------~Ilc3 > 1 C6 I ~-----~~ PlI-1

I 0.01 4.7K

~.I R36

XTAL 1/2 - U24 - -= SH.4 SH.2 SH.4

__________________ =-I�___\: 13 13 ~7

_H_I_G_H_S_P_E_E_D _________________________ 1-;2 L902r.~~----------------12~1·.L-S3~2~11-------------------------H-O-S-T--B-R-CK_ 38.4 K 3 ~~4 ___ -IJI

SH.6

U35 HC04

)P8-2, 15 P5-5 )~~~~~J~~~~~~~~~-'~~I~~~l~~~~+~V PI-2 > + 1 +

,,, C9 'r- C II .------4; P8-1 22 22

t----~~ P8-16 PI 1-27,29,31,33 >>--------.1 P5-4 ~r---~~~~------.------~--4---~----·+5V

+ I DECOUPlING 1 22 CAPS 0.1

'I" CI2 T------ rC100-C136

P5- 3 '>-----4I----4------t----+--...----4>---....-----,-1_1 LOGIC GND

P~-I ~ P.4 -I >-----.... P 1_ 1 )>-___ -4

P5-1 )~------------.------------------~---------------. -12V P4 -7 >>-------.....

NOTES: ( UNLESS OTHERWISE SPECIFIED)

I. ALJ- RESISTORS ARE VALUED IN OHMS ±5~. A~D ARE 1/4,*.

2. ALL CAPACITORS ARE VALUED IN MICROFARADS •

~

c

B --'

-

A P3-7 ,>--------... ....----..------t~--- - 5 V P8- 8.9,>-------... A

i P6-6 ,}-------. P6 - 7 f\iii ............ 1iiUL-~flIiRiii5liMllr.om,"'7I/Oi'iii~mw:r~---,---~-------1 I PII_ 9.14.26.34 :>--_____ ... / _._ ~ /::-" ... TO •• 1ekMdeo Systems, Inc.

I· PI! - 28.3"'.32 ,>------6 -'----,,...'l_I-... -+-~D....;L:.Y_PlI.J=uI,!.l ..... 111/--1.... PCB SCHEMATIC DIAGRAW PI_ 3 '}-----4 -._ x • '/..... ... .. f ~~~,~=..: 00.- I-_-+---~ ... -..-t' QSS CONTROL BOARD

IfiIIIIOMUI,'n()MWItICH"COHf'IOIIfFW.. I ~~~ -. -{----- - SID I CODEIDENT ~ 132163-00 i R:

L------------II---------------------~------------------------r_---------------------lr-------_______ -.~~==~~~~==-=:=.==~~-~~~~--~~~~~_~~~~. __ _L ________ ~~~LE~N~1t!~)N~~ ____ _ilM~arr~I~O~F~6LJ 8 I I 5 I 4 I 3 2 \ 1

o

B

A I

i

1 5 4

A0'-AI3'

+5V +5V t- 5V

t28 VCC A 01-'-1 0"'-----___ 00.;1

~ VCC/CE t-=9----:::.21,-;'.� 128 vee A0 .... 1=-0_· . .....:;;0~JJ IT:§: VCc/CE ... 9"------,1"',,

r0 __ ~I~1 Dd rS~~2~1

t28 VCC A0~1.;:..0_-""""",,:" 0,'. ~ veC/CE t-9"---__ --;~!,. ••

~0---'I~I~D0 t-8~ __ ~"

J DlICIII",101l

r

" VSYNC

1-5V

t 28 vee AIbl-::"rt.10,------,0=>;. + 5V lli vee/ e E • ... 1-'9'--__ 1.,,'.

o II D0 8 2' RP2(5)

PII- 23

5H. 4

I 12 IV 7 31

''''2~--13-1 U30 .... 6~~4~,1

i ~3 _--.L.:I 5'4 6 I I 6 Po? .... .5~---..;;5'-';'1

/,....1 _.....;1~2'-1 U 2 5 l-7:,..--_.....;~:-;:. r2~~1:34 r6~_~ 3 15 6116 ft2 5 5

.;=-0 __ 1 1-100 t-'8-----3"",.

I 12 ~7--~1 1.12------1--3-1 U 31 6 4'

~--5"'" ,~3 __ !_5-1 6; 16 P-2 t-5---

6"",.

~1~~12.:....1 7 3' • I K

1,,=.2 __ 13-1 U26 6 4 ~_ VSVNC ... P2-5

r3,-------,-,15=-1 61/6 ~2 5 5' V U28

SH. 2 00 - D7

SH.2 An RAM

r=4'----~1 6--1 T C - 5564 i-'4=------':6?>"·i

5 17 Pl:10 :3 7 ~--~ ~------'~I

~6 __ ~18~~ ~2~5_~8~1 ~7 __ ~19~D7 ~2~4 __ ~9~'.

V 20 es AI0t=2:..;.1-~10",'. 23 :;-;p. 27 ~/AII 2 ,..;

.---? WE A I 2 ~ ~ GND or p£.2 . ~AII ~ we 3 -= I 2 1

1

~C=HA~R~R~A~M ____ r-+-__________________ ~ __ -' SH. 2 en 5H. 5 ~R~/=w~-----r~--------------------~-. SH. 2

+ 5V~I406 vce D0t-B-----0, I

4 16 TC-5564 4 6 1r-5-~1 7=-1 Pl-10 t---=-3 ----'7::-..

~6~~1~8 F2~5 __ 8~' 7 19 D 7 F:2~A __ -:-9='1

2(2l CS Aln 21 ~ r---2=-~~'QIWE/AII - I

• +-+--__ 2:...7'(1 WE AI --:: l2. I~

_r-'14 GND oi~2~

-:!:- 2 13 W2 ~

U43 ; .--

~ SH.5 ""'='C~CL;:;;;K~---........... _+_-__'__7_ICeLK t-9 __ --::1,. 5 ..... C~R;;BTC,R~D _____ +-_-:I,-tRD pI0~_-=2'1 12 U43 U46

SH. 2QIT~ 2 IT I I 3 '--+---+---1"--\)532 }-I_I --t---t-. 9 -:t 2 8 4 U 43

4 1 6 t-4 _____ ~1 1r.::-5 --:1-=7-t 3 7'

~-----'-11

1~6--_1-8-1 t-=2~5~~8~'. 1/7 __ -~19-tD7 ~2~4 __ ~11'l9~(:1 r-~2~0~C5 Aln~2~1--__ ~~1 r---,2~3:-1WE fA II '''' • ..;

r--.-+-r-.-_2~7~WE A I 2 t-=2"'--___ ~ .....

fGND OE~

0+ 5 v4 vec RlW,..,I:----~-4

I a 80 A f'lv.-2 __ .._0 ..... I 17 '''t-3 __ -:::1::,", 2 16 U 2 0 t-4 _____ 2 .....

3 15 l S24 5 1-=5"--__ ....;;;3,,1

4 14 ~6~----:::4fl 5 13 .... 7 ___ ~5::'".

1.r-4-~16=-1 4 6' 7406 1~5 __ ~17~ t-3~ __ ~7~'. 1~6--~18~ F2=5 __ ~8~/1 ..,.:..7_-...1.0 119'-10 7 t=2:..:.4 __ ~19 I'''':'

.-----=2::..:0~ C 5 A I a~21 ___ ---,-"l'f~ ....

r--___ 2;;;..;3::..tWE IA II ,..

~ WE AI2 ... 2=---~livl too OE~ -:- 3 WI

2 I

t5V~ vee o 18 I 17 80 2 16 UI8 3 15 LS245 4 14 5 13 6 12

R3

o ' .. 3

4 2 5 3 6 4 7 5 8 6

All'

7 AD0-AD7 SH. 4 6 12 ~8~ __ ~6~. 1 II B 7 A 7l-9 __ ~7

~ ... G_N_D __ CEoo4lL

H.2 CRTe WR 3 WR t:"12-=----::45

"1 oJ _ 1L--+-_---'-1.;;.0-L v ~ SH. 2 2 39 A2 t-:1~3_---:::,. ~ 7 II 87 A7 I~

~ ... G-N-D--e ... E ---

SH.4 SH.4

SH. 2

SH. 2

/r::.I_-t----::3::-::B:-tA I t-:-1.,..4 __ ---::6:'1 L... ______ -++---.-..,1__---=12-\ II VQI 37 Ao. D7 15 7 1"- 'L532>---------,

CURSOR V~--1-~7~·rv ~3~4~---::0~"~--------------~I--~----~v~~U46 ~B~LA~N~K~~~-+----::1--::7~n~~~~DADDu~3 I '--D0----D-7---------~~~------~~----------~~ .. ----------------~--~~~

18 BLANK 32 2 A0-A12 '------'-" ..... VSYNC t-::3~1------=3"

~6~2674 ~3~0~---=4'1 + ~v . +5V t . _ ; +5 V t_ . AVDC t-:2:-::9~~~...... L!§. VCC UI6 Q 1-4 __ ~0t 4 ~ VCC UI7 Q ~~-~:1:1 8 ~rV-C-C-U-2-1 -Cl~i---:r,:.

2287 7 0 6310L5157bt-7---:I,,1 5 6 IOLSI57 b 9 6' 9 ~laLSI57bt-9---:-::10"'" ~~---="lr=-I '"""""""----:-:~ I b C 1-=9~_....;:23:.r.t' I b c 7' I nib C II' 26 8 2 10 Ie d J-.:.1..;::.2_---.;;(" 6 10 Ie d t2 10 .... Ie d 1....;1;..;;;;;2~ ____ 25 9 3 13 Jd 7 13'd II 13 1d 24 10 0 2 SEL~I--~... 4 2 SEL ~ B 2 OQ SEl rl.:-

R P1(5) 23 . II I 5 00 15 5 5 0" . 15 9 5 l t5 4.7K I? V Ob EN ~~ 6 1.1 Ob EN t>= Ob EN F

NMI 3:-------+------__ -t IN TR

-t',v ~

4 Ii ~ vee Q t-------:I'2"',.

;..;12~_3:;.t 10 U22 b t-'1'---_..;.;;~.,.1 .;..;;13~_6-1lb lSI5 7

12 2 '13 5 Oq

.----Ob

I SELI5 EN~

+ 5 V_-+--'v .... V' .... .,-----' l1'-2 12 L.!l OC 0 10 J.!. Oc ~ DAOOl3 21 13 3 14 Od .( R5 7 14 O~ I I 14 f-Od f:r.IJ"\ U43

CD0-CD7

HSYNC CNTRI I 4 GND ~ 8! GND ,~ GND I v .... '~" -..... -.~ , 18 I, r Is f ::fa :!:-s 10 S32 HSYNCB

GNDACLl~ -:::: H5YNC J?0 • RPl(6 - .4.7K~'~ __ --____ --______ ------'~~D~A~D~D~O~~-A-D-DI-3----~---.'~----------____________ ~~ ____ ~ __ --______ _+-----D-A-D-D0 .. -D-A-D-D-I~3 - . .

+5V-. ..

SH.4

P 2-1

5H.4

SH. 4

L...------------------~~----------------------~4r--~A07--A~I~3--------------~~------------~~-=~--~~-----------------+------~------~, PII-22

1 leo ItO. DAn ..... 'ROVID

I .L--------------~----------------._----------------~r_------------------_.---------------_r~-----~~~~--~-----~-----~~~~=------=~------

8 7 6 5 4 3 2

o

c

B

G

B

A

7 6 5 4 s 2 1 lCONO. DATI _D

I ~---2-4-1-+-5-V--~,L~~(jJ II +5 bV RPI (7)

16 I 4.7K ~-----t-__:4:__1F1IA4 vee UI:3 !VCC ruJ.:--'VV\.,.--'" +5V

31A5 ~9 8 U36 1-7-----t-~2~146 I0 lS00 5 II?

U2e 74~6

5 6

RII 4.7

+5V ~ .,.

C13.6 R8 180 .

C 2 4.7 .~(

4 + 5 V Q3

~

~ )

R7 IK l-=-:---t----:::;-i:I;-1I"I7 6 DC QD f-U'"-

~ __ ~_~2~3~A8 D0~9~-____ ---....00 A A -i2V .. lt~~2 A RP2(6) : ~~0 ~~J,£2_~_.4_2_6-411--___ ~ ____ ..., ~-----t __ 2~2::-t"9 ASI94 J-!-=----t-~1 97'""1"10 S 94

21 II 10 Sl 1 ~----.---=-.....,.,. I I II' K

+5V

U45 2732

DADD0- DADDI3 t _ SH. :3 --------,,~ ~ VCC Q0 J..;2:--__ -+ ___ --::5 ..... A3

...... 7--t-_,w 00 5 6 A 2 ",,6--t-~4:-1 U 3:3 6 7 A I 5 7 LS:3 74 9 8 A0

• ~4 -+-----:8.-1 I 2 I 8 r\ do .:::. E

10 13 ~ p2V ~E II 14 ~ GND

U 2 8 ~-+--:-1:17 Q 7 ~ 7406 18 •

R4 > 82

~ ... IG_N_D __ _

+5V

~vec CIA I DI 10 3 DA

02~1~1-----+~~~~~~DB U37 03 1"3 DC 04 14 6 D QO ~

----=2 ...... 51 05 I 5 9 50 AS 194 06~ I_~ 51 SI94 07r11 II CK

~ ... IG_N_O __ _

'6~ :>IK

2 WI2 I

-.;: RPI(9) + 5V 4.7K I

A ... ... . 15

16 CUR: BLk vee ~--IT BLANK HALF f.i

.-----I----------t--r--;2~1 oar SER I NTE.NSITY ~-~------~--------~_,~~RA0

~ RA2 \,J34 ~ RA3

~--~--------------~_,--~103~~KCLK &....--+----1..."... DCC r---+-~I~~DISPEN VIDEO L SH.3 BLANK 9 ~~~8-~~~-r~~lnl,~~,~:~

~OE ~:2 (7)t. G~D

+ 5 V'--"VV\t.---.

.--~--------r_~--~~~CURSOR 1 H 5),NC r--W-+--+-+-~--------1H-t+t--t--------I-I~34i17 v S'fNC COMP VIO ~

+5V +5V --.... 5'{S RESET

~

~ ,

5YSTEM~

RI ~82

U48 LS04

5 6

~ !Vee CIJj ...L- ~3 VCC QIJ 2 38 C\iAD (;3 1--f---f-+---t---:;3;-10 A 0 D" '''1-i5~ __ ---=39;-1 CHAO' 02. VI t-:2::.,;3:...-____ 38 ___ 4_K

L...---+-+-t-t--~~::_tO B U4 2 I 4 6 i CHAO 2

SH.:3 HSYNC ~

U44

5---- 6 4 5Y'S\t--I--

L----+-t-+-1r-1~5:::10C QO~32 2 7 U35 l! 14 CHAD3 m5pRAMt..:3~6~ __ ..... XT ..... A ...... L_I_/2_ ~ DO QC ...

I--.... 3 8 L5374 12 12 C\1ADl . 01~

~----::2~S I 4 13 I 5 Ail RAv ~ ___ 9:;150 A5194 5 14 05 ~ AT,. BNKlNRI27

~O~CC~:':""':":"-----+-4----:...----H-t-+---------~---m'jl 5J Si94 17 06 Q7~ 31 02 925/92(31 4°1 SH. 5 DOT CLK I I C K I a 0 7 r---:-:9~ eDW/WOB 'I=G 2 ~ SH.5 f GND II CK ~ LINE! R> An GND * SH,3 CURSOR SH.:3 ,~

HIGH SPEED

~ OE g. 9IG/S2:, 5DR ~ r- GN D 4Q-'TF r--

-:;. R2 Ul~ ~ 82 ~~:~4 I; ,.10

~ IVY3 UI~ 3.6864 'HC04

~O~ C5 4-7K. 1 0•001

PII-21

P2-3

P2-4

PII-20

SH·5 SH. I

SH.I

5H 1,6

SH;2 UtiE/PAGEATT SH.2 ;0G IG0B

SH.2 MB/NONEMB.

L--_________ 11

1 : -------......, SH.2 .!p I.

SH.2 ~~==========~=-=-----------------------------------------------------IF==~~~~ •• ~ Systems, Inc.

PCB SCHEMATIC DIAGRAM QS'5 CONTROL .BOARD

D

c

B

A

D

G

B

A

i

I i

i

8

SH.2

SH. 2

SH. 1

7

80/132

6 L 5

RPI (10) 4.7K

4

r---------~------~------------------------------~~-~A.N.~.---+T5V

U38 LS74 " 2r--'~ .--40 Q'I-::J~-+--+-....;,I.,---- ............ ~ 3 4 U 39 L.!.

r-If----3~<:K - 6 I 2ILS01~~~--I 6 13 7 GNO Q~ ~ 5 LS00 .....,~ U3'9

1

5 o 8 9

U41

4 LS32 6

U23

9 LS0~

U39 ~~_LS_5_1 __

Y I WI:3

8

( Y2

.-_--+ __ --..,,;1-1 ~ I.OB4 MHz

..-__ ~I IG, ~~q,=> .. 8~_1 oOit-o--2 --+------I'----JI MHz

~

RI0 82

+ 5V U 36 • R9 : 82 I L574

~~ t--_

11

4-1? S crL

9 U24

~ ,......u.D i"i 8

I I,. K \..IP'----t---.

C!>~ 47Pf

~, R ~/13-

U48 504

Pi>~"!:D'4 __ :-t 4

vee U 41

551

GNO

U40 +5V A5163

RP2 (3) t 16 vce IK 1lf

+5V.--~~'~~'~~~--~lt~CEP .--"""!,~CET

Ci: P3 • P2

6

1 I

(40 41PF

U48 504

TC 15

PE 9 I r

~13~_---:..1..:...t1 .10 ---...... ~P, .--+....;.3~P9 ..-....-~Mft Q2 12

U48 S04

1 DIICIIIPflON leQ "D. I iJAii I ., .. ;iU.iW I

D

DOT elK SH. 4

c

Dec SH. 4

SH. 4

SH. 3

SH. :3 B

SYSTEM RESET

"CK ~, GNO

':r' U48 504

L-________ -------+ ______________________________________ -r-+ ______________________________ ~9, ~8

I CCLK SH.4

U39 13

~~II~-----------------------------------------0~O SH. 2

A ~~~~~--~~~r-----r-~.~.~~~-~~-em-~~~~.--,

---;--r--IF4-=-.:;.:......-Fl~-l PCB SCHEMATIC DIAGRAM -T----- ~-4---+"""---I'" 955 CO NT ROL BOA R 0

~------------.---------------------.-----------------_,,_----------------~----------_r~--------~~~~--~------~--------~~~~~~--~~~=---8 7 6 5 4 3 2

o

c

B

A : 1 I

i ! V i

"7 6 5 4 2 ",'UOATION

"·1"" .::. P6-1 RxD MOD P8-12 ~~ ______ ~l ____________________ ~ ________________________________________ --______________________________ ~

P6-4 {r------------------------------+------------------------------------------------. SH.2 SH. I SH.2

AI0 HOST BRCK D0 - D7

+ 5V +5\1

t 14 I vee A 0p3~--+-+---+--,

U7 B0p6~-+~~_+--------~ 1489 C0~- RP4 + 5V

U47 13~111 + t~5 ~)o-3"'--_--12-1~

- +12V' .,,0~1__~18~D0 vce f

1 19 RTS ~8 '4 ~ 9 2 20

+ 5V f 15

~0-+--.-.:.;18;...fD0 vee r-...,,=1-+~'9::,..t RTS ~

2 20 3 21 -) 4 ~ 4 22 _!A 22 6551A

U44 LS08 6

U5'50 . 43 21 UII '---+-Ir---...... - 5-f-f1 6 T RTS , ~+-~ .~~~~

r-...5 23 8 5 23 ~o- 8 C3b..L C24 ~6 24 fRTI~ 6 24 IRQ -}:..6 ~ ~H :330pF (2)

D0 ~ :;~ 4.7 K(2:<if P3 - 5 ,~C~T~S----__._---~I__4 A I R eAt-2""--+r-_·--+-+---t----,-(3--:-~__'\1V\r___41

,~0~S~R----~--~ __ --~4~81 RCB~5-+--;~~~~)~~~J P 3 - 6 " DC D tx 9 v v

P3 - 8 >')......;:R:...;:x:.:;D;.......T----+--~ __ ~IIU~ C I RC C c. ... 10 ~7 25 07 7 25 07 13 I . tf7 DS R

P 3 - 3 '~l---~-+-1 __ +-----j1--___ ,;.;13~ 0 I oR C 0 1-'- ... c."" J..

1

GN 1 N914

TCI4IC'5rC'J3~~PF J? (2 X)

SH.I SH 2 SH.2

SYS R[SE. T

AI

th(4X)

e----------+--+-----1f---I~:-I -RE.-S I~ R-DECO-S Ii ~ \I -CTS : 21f OC.Q ...--_4-_1-_-___ - _-~~_--=-2::8~~ - ~ f---L-I

r--------+-+--t---;:::..----,:~,.-t~~~ T x 0 ~ ___ -4-----~-...::2~~ TlI.O l! f-- 2 ~:3 OTR '"' W6 - 3

r-------4~----oCSI ~------_4--~3~CSI 7 .-----..-..------:-I;-tXTAL I '--------+-~I~~ XTAL 1 ~ 1488

.------+--tI------:-:14:-tRS0 14 RS0 -:: , 1 27 ~ 5

21 .--------+--2;-:1~ RS 1

VI r----+-......:;,~0 2 - 12 V

C3~ J 3~OPI

1

P3-4

P4-6 P4-5

r-__ 1-~-+~~r1-+~.-__ ~1~2 RxO ~ RxO ~----~-----------------.--------_4, PB-3

r-~~~_+4r+-~_+~----~I7.aOSR ~ ____ ~nco 9 - 9 I::!.Si!!:l

-=-~ CTS G~NID ~ CTS

R xC I 1

-

4 U3

+12V

rl<4

~--tw\-O-D__+'- P<D _ ~

-::!:- I i r RxC GND

P8-14/r------------------------+4-+--~_+~~~~~~-----------~_+~~~~----~ ~' Cl8 33e\pF

+ 5V

~~~;4 ~6 6 . TxD

T 5: I bO''''''4--......,,,....,.-----4 P3 - 2 L.:... H.--' 1 C25 '

t 14

vee A0 ~

10 - 330PFHST OTR

. ~I: I );. 8 P3-20 rr-

U 8 1... 6 1489 B0~ +5V e'" 0--1 1---+-' t 15

D0 lr-':-----I

~H-.../ I *g~PF6 ~ P3-11 ~--1-------~----~----------~4---------~·~1-2~~~ f~~'~I~~_.~~~~~A~m~PR~IN~T=E.4~~ P4-3

~ ~C27 P4 -2 DATA FROM PNTR I AI ReA~5 r-..."",0 __ 18--1D0 vee P4-20~ W6 I ~ 4 B '-'.1_--,-,'9=-1 RTSP! P3-18 ' TE.ST T W]I ..... o:~2=4 ..... ~ ___ .:.;:'O~e: RgB'-9-~ 2 20

"I'" 3313 PF U 33 " + 5V .1. ~~~;)--+3..., LS32 7 VIr:" C34

, C20 1 ~9 1 113 01 GN~C.g ~ -...;:3~--=-~2~1 6~;IA

33(3PFJ. 330Pj};. C 7 J:. 7 6 5 r7) ""'~---':-'23~ 1 .- 1488 lIN ::~ 330Pf

~?~ - .c RP4(2) a...-____ +--__ ~D_C_D_4 P4- 8 i .. L I'KY l~ 13 : 4.7K -= ~ ~

r· 6 24 " P BUSY I W~2 _ ~.7KRP~. > ,7 25 07 P4 - II " ;l3

P4 -19 ) P BUSY ALT ..... ~3 + 5V-......... ~ L-1-~f-+-+--+-______ 4;..j1RE.S

26 -12 V IRQ IRQD-~--+-~---+-+--~----~------~~--------~--------------------~~--4 SH.2

TxO MOD '_ 7 P6-2 R/W ~--~~~~4-------~16~DCO

SH.2 ~A~9~----------------------------~--~_+~+_~------~28~R/W SH.2 ~CO~M= .. =-----------------------------~--~~~4-~-----~32~CS~ TxD 10 SH 2 -~~M~~--------------------------~--~~~~------~CSI

10 U47 ~------~r-----------~--.-T--------~; P8-4 8 TxD KBD "

. XTAL 1/2 6 SH.4 -7A0~~~----------------------------~----~~+-~------~13~XTALI 5H.2 ~~------------~~----------------~------~+_~------~RS0

U23 ~ ______ ~~14~RSI

PI _ 4 " R x D K8 D

r'l "'" <In. Co

All SH.2

~ 27~2 I 9 ILS~~)-8--_------+-----~---+----__ ~1~2 RxD

r 1 C43 I'SOP5

1- e21 J 100pF

~'7 OSR 9 -

CTS GND

I ' f '

PII-8r-,------------------~--------------------------------------------------~

T 9 )~3~~~--------+-----~------------~~~~, PI-5 ~ 1C45 R34· IISOPi

II I ~.---~ -~ ...-.--1 ~+5V

P8-13,~D~·T~R--------------------------------------------------------------------------~ SH. 2

P8- 5 ~----------------r-------------------_,--------------------_.--------------------_r--------------------~~ ________ ~====~ __ ¥-__ ~ __ ~ __ --____ ~==r_~w-----~~~~~

8 7 6 5 4 3 2

o

c

B

-I I I 1 I I 8 7 6 5 4 3 2 I 1

I APPLICATION REVISION DESCRIPllON ECONO. DATE APPROVED

NfXT .t.$Sy :::==-:' A PkO~ ~ELE.A::':.. 2b61 '!:i~ ~~ USED""

:!. RC=.L. ~E.\I '0 i'OA.a ~R E.C.D ~<"91T I.~ .• ,. ~ C RELRIOV C FA8 SMALL BD 2820T rq,./,k 10 , ""?J5 D RtV \(ALUE'=> OF "<.Ib~ RI7 2~T <>/>4.1--< ..,----~ E RI:.L R..'ii£.V D FA~ F!C.R.I:.c.O 29'OOT ~/85" !.{-«q F ADD C41 PER EC.O 3035T r~r./(/ .1..-,-...

G R!C.V R '9 4 .JUWlPER5 !!>,~~, q;.ijJ '~(}-' H DEL R2S PE.R. E.c..O ~a'2:2..T "Irq I} U-~ 0 J ON SH.4 ADD R3S 1M I ~bOZT 1;o/Q11i. W,-~

.0

K ON ~. 2. 3 ADD SYS RAM-: :k3"T h/~1{ G~( +5V R/W I

+5V R20 + 5v

47K vv

CAli rl A37 ~ IK IN914 4.7K RP2-4

P,\~ <

"TI.SK < 8 CR9 ~ R35 < IN914 3 U29 LooI Q4 I--. v

roo 10K 2N2222 La211 C37 -I:. RI5 .> · RI8 I}'-~ I 22.'" > · 1M > -· -

=. 2 C28 - 10

+5V ~5 /4 rr;

- U28 R21 > - -4-,7K > UI3 7406 C CRa R23 5

c .1\ A A 6 II _10 SYSTEM RESET

.... KBD RST INS811 vv 41LSOO .. 4.7K .....

r 1c3 1 SH.2,4,5,6

PI-6 /

I C6

- .> > "- PH-I

1°·01 > 4.7K ,

1°·1 R36

U24 - -.L.

- - -XTAL 112 - II U47

SH.4 12 )LS02~

13 13 HIGH SPEED

12 )LS32 II HOST BRCK

SH.2 38.4 K

3 "",,4 SH.6 ~ SH.4 "'"

U35 HC04

B

:P8-2,15

P5-5 ~ r +1 +lcll r NOTES: ( UNLESS OTHERWISE SPECIFIED) + 12V

PI-2 I. ALL RESISTORS ARE VALUED IN OHMS ±5"1o , P8-1 AND ARE 1/4W. -r C9 "

PI 1-27,29,31,33 ~ 22 22

2. ALL CAPACITORS ARE VALUED B

1 , P8-16 IN MICROFARADS.

~

P5-4 "

+ fel2 +5V ~ 1 DECOUPLING 1 T------ TC100-C136 22 CAPS 0.1

P5- 3 ~

I J. LOGIC GND

-I-

p'Z_' " 1 ..J I /

+ 1 CI3

- J P4-1 )

PI-I T 22

P5-1 )

1 • - 12V

I P4-r P3-7 "- 2 I VRI 3

- 5V P8- 8,9) I 79L05 1 A F6-6 ) C29 P6- 7 11 +1 /

"/ :=-i?~ ~e~~~CT PII-9,14,26.34) 10 o lele\1.deo Systems, Inc.

I DES o"rf

:>11-28.30,32' DR D L '( D~,'; 17/8~1- PCB SCHEMATIC DIAGRAM PI- 3 ' - CO''''O[JITW.

. , c"' fl"",SH DArE

rMCS~NTI5THE.F'AOf"EFIT"I'Of'

v~-q=.S CONTROL BOARD TELEVUO S'rSTEws . ..c AHOCONT ...... ENGR DATE

-'- INFOflIIU,"l()N W'4ICM I!§ CQNI'tOEJfTlAl DESIGN ACTIVITY "F'PAQ,,'U.

SIZEI CODE IDENT ~. ~ REV - "'''fO ~~.r.A'Y TO ""El..EV'OEO NO - P"'A"'I'~!"M'S:J()CUNpn"""lJfcoPtI:O D I 132163-00 K Rt:pqr~:1 QP: corsc...OSfO TO n-o.--o

CUS"OWER 4PPAO"""l. ~~,.~.~~~~~ ~~~~~lE~~~ lA~. z SCALE \\1:. I SHEET , OF 6

8 I 7 I 6 I 5 I 4 T 3 2 I 1

A

o

B

A

8 7 6 5 4

A0'-A13' , , +5V +5V +- 5V

128 vee A0....-1=0 __ 0~,J ~ VCC/CE t-'9~_-:-IJ'"

r0 ___ ~I~1 D0 ....-8 ____ 2~, I 12 7 3/ r2---13~ U30 ~6~-4~'

tH8 vec A(/)t-10 __ ~0 26 9 I'

vCC/eE 8 2' o II De} I 12 7 2 13 U31 6 4'

3

128 vce ArtJ 10 0 ~ VCC/CE 9 ~/

~0----I-I-;D 0 8 3' ~1 __ ~1=2-; U25 ~7~_~ 2 13 6 4'

.r~=-----,--,! 5"-i 61 16 p.;:> 5 5' 4 16 Te-5564 4 6 r"5---'-17=--i PL-10 3 7

3 15 6116p.2 5 5' '/4~~1-:-6' r4~-~6'

S 17 3 i

~3-----15-i 6! 16 p.? 5 5'

4 16 TC- 5564 4 6' ~5----1'-7--t PI.:-I 0 3 7

6 18 25 8' .,------=--=-1

1~7 ____ -,-19~D7 24 9 ~_-:=-2::=-10 Cs AIO 21 1\2>, ~-23-QWEfAII /

.++--+ __ --'2=-7<1 WE A I 2 2 ~ 14GND 0E~2~ ~ ~313

W2

=6 ___ !~8~ r2_5 ____ ~8 1/7--1~94D7 r2-:-4 ___ ~9

.-------:2:-:;0:.ctC 5 A v~·2,-1 ____ I-=(J. r-_2-::-3'WE/AII·~ ,

r--++-HI~2:-7:__1WE A I 2 t-;2"",, ___ f~2 14 GND OE~ -r-L-----I

.~6_-----:18~ 25 8 ~7 ____ 1_9-;D7 24 9 r--_2_0--.. C5 AI0 21 10

23 WE/All I

27, WE 2 12 ~ AI2 '

~ GND OE ~2 r;r" -::!:- WB 3 -=- I 2 1

1

SH. 2 ~D~0~-~D~7~ ______ ~ ____________________ ~~,,-__ ~U~U~~-~(C~[D~7 ____ ~ ______ ~~'~~ ________ +-__ ~ ____ ~~ ________ ~~~~~~~ __ ~~ SH. 2 An RAM , -.-8J...lJ:2 .BlLL ....

~~ ~ U43 U46

~461

S c ~=HA~R~R~A~M~ __ ~-+ __________________ ~ __ --. I H. 2 -~ 3 ~

\.i I 2 LS32 13 12 . 5~. 5 ~~-------r-;----------------------~-' ~ __ ~ U44 5H. 2 ...:.,R:!./.:,::W ________ +---+-___________________ --t,...., U46 ~I 3 U48

40 0 4 I, 6 2 LS08 504 - + 5V~1 6 vec D0,r8~----J I 5 }LS32 ).:'------.--; ~C~C~LK~~--~~~--~CeLK ~9----~lrl ~~--~ SH.5

SH.2 SH.2 SH.2

..,;C=RT=C;....R--=D:.....-__ --+ __ ::-tl RD r'10~ __ --=2:, I 12 ~C""'RTi~C;=;::;;~ __ -t-_ __=_21cr\_t: t-:-I ::-I _----:3 .. 1 13 )S32 }-I_I -t---+-, 9 32 8 ~U 43 .::::Cc..:RT.c..C::....:.:W-'-'R ____ ~--=-+-___=_:3~WR .... 1_2 ___ 4-, .--+-1----/ 1'----+-__ .:.=10~ 5 532 6

r2~-+ __ ~3~9~A2 ~1-:-3 ____ ~5'1 ,-1 __ -+ __ -::3:-::8:__1 A 1 r,1r:4 ____ --:::6:1 L... ____________ +-+ __ -+ ____ ....;1c:::.2-\ II

+5V~ vee o 18 80 I 17 ,..., 3 I

2 16 3 15

U20 4 2 L 524 5 t-5----3

4 14 6 4 5 13 7 5 6 12 B 6

~7-----1~1 87 A7t-9~ __ ~7 :f .... G_N_D __ C .... ErLL

/

3

+5V

t 28 vee AC/J.-10=----=0"',1 ill: v eCI C E 1-'9'---_-'1:..-;/1

r0=------'-"~D0 1-'8'---_-=2J,/. I 12 7 3

r"2----~13~ U26 ~6:----=4~/1

i, . .=.3_--,-,15"'-l 6! ! 6 P,2 r5:--_--=5.n' .~4-~16~ ~4---=6~/1 .~5-~17~ r3~_~7~'1 1~6_~18~ F2~5_~8~'1 I r-7 _---'-"19"-1 D 7 p2:..:..4_--=,9 r.(0:.1

r----.:.2=-:0=ct C 5 A I "'\OF2,-,-1 _--:21 JU'l.l1

.----'2:::....3~wt: fA II ~ WE AI2r2"'-----..;..12='

PGND OE~ -=- 3 WI

2 v ,

R3

, +5V~ vee (;3 IS B0 I 17

RfW I A 0F2=-----=0:/1

3 I 2 16 3 15 4 14 5 13 6 12

UI8 L5245

4 2 5 3 6 4 7 5 B 6

3

All'

4 """ ~

DESCRIPTION

51-\ \

VSYNC

+ 5V

> RP2(5) >IK

P 11- 23 SH. 4

V5YNC~ P2-5 . U28 7406

SYS RAiVI R/W SH, 2.

7 I I 9 7 A00-AD7 B 7 A 71-------../ ,,---..... --------- SH. 4

~ .... G-N-D--C ...... E~


SH.4 SH.4

~r0--_r---3-7~A0 D7r-1~5~~7~1 ~ ________________ _r+_--+_----1-3~JLS~/rU-4-6-----------. CURSOR V 7 CURSOR 34 0,- '--" ~ -, C 00 -C07 ~B.::::L~A~NK~--T----+--~1--:::7:--1 DADD0r-3~3~--~1 '--D0----D-7------------++---+--------------------------~~----------------~--~,,~~----------________ ~--------~---------

SH.2

Sri. 2

B

I 8 BLANK 32 2 AaJ-A , 2 I '------'-'''--I V5YNC 3 I 3

U 14 +5V SCN2674 30 4 , ._ I

AVDC 29 5 ~ vce UI6 Q ~74---,---...:.0:...; 28 6 0 3 I

10 LSI 57 b I------~ r 2,-7::--_=7 I 6 I b C 1-'9=---_----::2 .... 2_6 ____ 7'.8 2 1 al 1 c d ~1-=2---~3 25 9 3 13 Id NMI 35-

-------i-------.--t IN TR

R Pl(5) 4.7K

+ 5 V _-+_-'\.AI\.A~A __ ...J

1-::2:-::4~_1_0'-1 'I> 2 Oa SELt----:-I---... 23 II I 20b EN~1 22 12 2 II OC

~ DADDI3t-2--:-!----!3---.., /3 14 Od p,,\

HSYNC CNTRLI ~ ~_ND8 1_ 81 GNDACLL~

2° .>RP1(6 -=- ,,>4. 7K ,

+5V t . _r----.., ~ 4 4'

4 3 vec UI7 a ~7-----5j/l

5 6 I a LSI 57 b t-9=------6~/' ~--~~Ib cr-----~I 6 '(;3 Ie d t-~_"2=____7../1 7 13 1d

4 2 SEL~ EN pl2

"

5 5 00 6 II Ob 7 14 OC

Vd GND

~8

D.~DDO DADDI3

+5V t .r----........, L!g 4 8":-

8 3 vec U21 0 t-:7~--~·

9 6:~ LSI5 7 ~ 1_9~ __ 1~0' 10 I (]J Ie d (_I 2 __ 1..-J1 II 13 'd 8 2

9 5 00 IT Ob

10 Dc

SEL~ EN~

I I 14 ...... ),. _0 GND

~8

"

SH.4

t-5V

~ vee 0 t-4 __ -::12",. 12 3 10 U22 b ~7,-----13~' 13 6 Ib L515 7

,

12 2 0", 13 5 Ob

I SEL~ EN~

GNO I "bs

U43 9

~P2-1 ~ HSYNC SH. 4

DADD0-0AOO 13 SH. 4

) -I-5V~ j j

L-___________________ +-________________________ ~--~~~-----------------=+-------------------------~~------------------~.~---------------7) PII-22 ~A~0~-~A~I~3~L_ __________________________ _' _________________________ ~_~ __ ~A~0_A~13~ _____________ ~L ________________________ ~I

7 5 4 3

~=_------n=======~~~--------r_----------------------_1

2

O. TeltM.deo Systems, Inc.

PCB SCHE.MATIC DIAGRAM gSS CONTROL BOARD

o

c

B

A

8

o

-

G

-

B

-

-

A

8

I 7 I 6 I 5 1 4 I 3 I I 1 I ECO NO. I DATE I APPAOYED

2 I APPLICAnON I REVISION I DESCRIPTION

S\4 \ I~-I ~-~ I I S~E IL _________ ----------------_~-" PII-21

I I I RII C 2 4.7 4. 7 24 t + 5V

Q0 2 4 IA4 vee

- + 5V RPI (7)

f l6 _ I .4.}K UI3 ~VCC CLR +5V

U28 7406

+5V.~-AV~y~----~-+~I~(--I.---------~) R8

5 3 5 6 2 A6

5H.5 CClK

=2 __ 7-1 U 32 = ~3_---,-:8::-; L S 3 74

4 13 5 14 6 17

7 18 D7 I I CK

9 I A7 12 23 A8 15 22 :1\9 16 19 11\10 19 21 I~ II 07

~9 U36 10 lS00 8

5 DC QOriZ-~~~~~----~6~DD D0 9

A5194 --

10 51 5194

II eK

5 6

4 U24 LS02

~5

+5V f ? RP2(6) ~IK I

R6 470

j~,,0 vV'

R7 :: Q3 IK ('

Lte)2N4264~ -12V

,

.----l OE f GND

U45 2732

~GND 2 WI2 I j

SYSTEM RESET

+5V R PI (8)

+5V 1 4.7K

RPI(9) +5V

4.7K A

VVY

DADD0- DADDI3 ,

SHe 3 ---------~,,, ~ vee

~vec 3 DA 01 10

D2~1~1-----4-+--+_---1 4

CLR vv +5V 15

.,,-7-+_3~ 00 Q0 \.!:2=---__ -4 __ ---==5'--1A 3

5 6 A2 1 '-=.,6--+-_4,,-t U 3 3 1'-.:::.5-----+-__ 7:-1 l5 374

4 8 10 13 II 14

U28 17

6 7 AI 9 8 A(/; 12 18 OE

2(/; CE

FGND

03 13 D4 14

05 15

D6~ D7~

5 6 2 9

10 II

DB U37 De DO QD 51 SO A5194

Sl 5194 CK

~ ~ CUR: Blk vee 24 ---II BLANK HALF 8

......-----I-----------+----t---::z);,;·OOT 5ER lNTE.NSITY -=·~----~---------------~--T_~~RA0

~ RA2 U34 l££ RA3

~---I---------___:r___t-_:_10:::-i BLINK. eLK . '.

7406 18 II D7 SH.3 BLANK 9 ~~~8-~~~~~+IVCK

~OE

~:2(7) f GNO

~ R4 > 82

~GND L-_+--_~13:; DCC r----If---

6-tDISPEN VIDE.O ~

......-~-----------------r--+_~1~9 CURSOR

+ 5 V... 'VV

SH.3 HSYN C

I Iu SYt-K ......-UU~-+-+-+--------------+-+-H-+-t------------1-1441VH SYNC COMP VID ~ + 5 V + 5 V L-__

3-t7 SYS RESET

~\lCC m -'--- ~ vee > R I L-4---1~-+-----:3:-tD A 0 3 > 82 4 42 ----=-----t00

-< U 4 8 L--~~_+__+_---i D B U I 4 S r1 4 L---+-+----'r-t~~5::-t 0 e Q r!-f- 2 7 U 3 5 --"- L w U44 T f=. D

~ D D QC ~1-=-3-----' 1'-=3=----8--1 L S 3 74 5 'X):6 ____ -f--+-f-__ 5~ 6 2

Q~~2~------~38~CBAD0 llU 5 39 mAD \ 02. VI a-:2=-.:3=---____ 3_8 __ 4_K

J-:6:O-+ ___ --:~;::-1 CHAD 2 36 XTAl 1/2 .... 9-+------irrnAD 3 DISPPAM t...:::.::==-----.:....:...:.:...:.:::.--'--".-~1~2+-----1~4 c~Au7 011~

~LS08J------' L~~~=~9:~~ ASI94

JD~CfC------------_+--~----~--------~~_+---~----------------~t_----_r10~Sl ~ SH.5 DOT elK II CK

SH.5 f GND

.'--'4=--__ 1:....::3=-1 ~1-=5+_----1 2-"-f ATT R/W ~ 5 14 D5 ~ All 'BNKINl-I ~

17 06 Q7 ~ _---"-3-11 02 925/920 140 , '8 D 7 ~~9'-1 BOW/Woe PG 2 ~ II CK ~ LINE! PG An GND I~

,---L OE r- 910/92:' SDR ~ r GN 0 I 4Q-7F J-----,

-=- R2 I UI~ ~

III ~ I n>vr it" ~i~

L---------------------------------------------~:~.-t.--------------~I 3.6864 HC04

L-L_=__=__=__=__=__=__=__=__=__=__=__=_-=-+~_=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=__=_~---' r ~ g.~ 01

P2-3

P2-4

PII-20

5H. 5

SH. I

SH.I

SH 1,6

o

I---

c

H

B I---

~----~~-----~~~------~~~-~ , 1 I I >K~( R3B ~

~~~c==-~--~~----~~------------------------------------------------------------~II ~ --=============>=4~7KDM~IM~~~--_.--~--~~~~~--~A I .AT'~/AL roLEA.<NCES",USSNOTEO / ~~":,T O. TeleVi.deo Systems, Inc.

~~~~~~------------------------------------------------------~~~~~~~ ~~~. ~ ~ DLY :~I~ PCB SCHEMATIC DIAG~M .:f. , • 7 J,.:.C"-':"·I--_~O='T''---;- g55 CONTROL BOARD

~ §~ ... ~ :/.~.'--- ~1=~ .. ac=Tly=ITY= • .-:N~~~·T<L--+..-.SDlz:;;:E:r IC"'O"'O-rlE liniOE~NiTT 1=''--1-3-2-1-6-3-' 0-0-.IR ~~:EiEvT1 =~~~~c::~~o~~ II CU!TOUE.A~Al I ~ ~~':.'~~,";7;':;;;"',;;~'::,~" ~"~":7." ~.. SCALE "ONE ISHEET" OF b

I 7 T 6 I 5 1 4 I 3 2 \ 1

8

o SH.2

c

SH. 2

B

SH. 1

A

8

7

80/132

6 5 "" I

RPI(0) 4.7K

4

r----------.--------+---------------------------------~--~yAvAvr----+5V

U38 L574 4

.----2=i0 ..,:5=----+--+..;.1,--~ 4 U 3 9 lJ. r--f __ 3~.r K 9 5 t 21 LL5500d::>V1lJ~~3--__I 6

7 GNO Q ~ 5 L500' 13 U39

5

4 lS32 6

10 8 9 9 LS0'~D--4-"'-10-1

U39 r

U41

8

LS51 U23 I~

~----------------~

Y2

...... ----1---1' 31.084-MHz

YI

...... ----t' Iq~33910 MHz

8 Wl3

I 2

U48 504

~JIoI""'o-4 _____ 2_f

5

4

vee U41

S51

GND

U40 + 5V AS163

RP2 (3) t '16-~vec

3

6

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ORDERING SPARE PARTS

You can order spare parts by telephone*, telex or by written purchase order. To place an order, contact the TeleVideo Regional Sales Office in your area, or contact our Corporate Spare Parts Order Entry Department at the following address:

TeleVideo Systems, Inc. 1170 Morse Avenue

P.O. Box 3568 Sunnyvale, CA 94088-3568

Sunnyvale: Telex: Fax: TWX

or call

408-745-7760 474-5041 TVISYS 408-734-1927 910-338-7633

All orders are shipped F.O.B. our designated site.

*All telephone orders must be followed by a confirming purchase order clearly marked "Confirming Purchase Order".

3-1

Order parts by contactinq the TeleVideo Regional Sales Office in Y0ur area, or contacting our Spare Parts Order Entry Department.

Table 3-1 955 Terminal Spare Parts List

MAJOR MODULES List Rec.

Part Number Description Price Oty.

*132160-00 LOGIC BO~RD 417.40 1 *132880-00 ENH.~NCED GATE ARRAY LOGIC BD. 250.00 1 *132325-00 VIDEO MONITOR BOARD 50.00 1 *132324-00 POWER SUPPLY 80.00 1 *130945-00 KEYBOARD ASSEMBLY 92.00 1 *122187-00 TUBE CRT 14" GREEN 85.00 1 *131747 .... 00 TUBE CRT 14" AMBER 85.00 1

PCB ASSEMBLY LOGIC BOARD

NOTE: Determine whether you have a gate array logic board or an enhanced gate array board before ordering the shift register. gate array chip or static RAM chips. See page 3-3 for enhanced gate array part numbers.

List Rec. Part Number Description Price Oty.

*130236-00 IC MICROPROCESSOR 65C02 3-MHZ 26.00 4 *121387-00 IC 2K x 8 CMOS STATIC RAM 14.00 4 *131405-00 IC GATE ARRAY TVI 16 42.31 5

131612-00 IC 74AS194 4-BIT SHIFT REG 5.00 *180002-78** IC SYSTEM EPROM 2764 35.00 4 sets *180002-79** IC SYSTEM EPROM 2764 32.00 4 sets *180002 .... 88** IC SYSTEM EPROM 27128 32.00 4 sets *180002-91** IC SYSTEM EPROM 32.00 4 sets

*TeleVideo recommends dealers stoc~ th~ qu~ntity indicated per 100 units.

**Before ordering, check the part number on the EPROM(s}. You must replace the EPROM(s} with the same type and combination you reMoved. The thr~e possible combin~tions are:

1. Two 2764 EPROMs (PiN 180002-78: PiN 180002-79) 2. One 27128 EPROM - PiN 180002-88 3. PiN 180002-91~ PiN 180002-88

3-2

Table 3-1 (Continued) - 955 Terminal Spare Parts List

PCB ~SSEMBLY LOGIC BOARD

Part Number

*120530-00 *130234-00 *180002-26 *131154-00 *131155-00 *131386-00

Description

IC SY6551A/l 2-MHZ SYN/AMI IC 2674 AVDC 4-MHZ IC ROM 955 CH~R GEN CRY 19.3396-MHZ OSC CRY OSC 31.684-MHZ BATTERY LITHIUM CYLINDER

ENHANCED GATE ARRAY LOGIC BOARD

*270947-00 IC GATE ARR.?\Y TSI-19

PCB ASSEMBLY VIDEO MONITOR BOARD

*242816-00 TRANS FLYBACK KFS-20867

List Price

6.00 28.00 35.00 8.00

17.00 6 .. 00

30.00

14.00

Rec. Oty.

2 4 2 2 sets 2 sets 2

1

1

*Te1eVideo recommends dealers stock the quantity indicated per 1"n .. _':J.._ .LVV UllL .... ~.

3-3

Table 3-1 (Continued) - 955 Terminal Spare Parts List

ADDITIONAL PARTS

Part Number

*131219-00 131158-00 131159-00 131157-00 122911-00 122161-00 132165-00 132166-00 132155-00 132143-00 132144-00 132145-00 131969-00 131968-00

Description

KEYCAP KIT KEYSWITCH NONLOCKING KEYS\'lITCH NONLOCKING MAR KEYSWITCH LOCKING PWR CORD 3-COND SHLD lOA 125V CEL ASY 6 CONDUCTOR RJ12 BEZEL REAR HSG BASE PEDESTAL OUTER SHIPPING CARTON SHIPPING C~RTON STYROFOAM RT SHIPPING CARTON STYROFOAM LEFT OPERATOR'S MANUAL 955 MAINTENANCE M~NU~L 955

PRICES ARE SUBJECT TO CHANGE WITHOUT NOTICE

List Price

20.00 3.00 3.00 4.00

10.00 10.00

9.00 19.60 6.40

15.00 15.00 15.00 20.00 50.00

Rec. Oty.

1

*Tp.leVideo recoMmends d~~lers stoc~ the qu~ntity indicated per 100 units.

3-4

Table 3-2 955 Parts Reference List

NOTE: NOT ALL PARTS LISTED IN TABLE 3-2 WILL BE STOCKED BY TELEVIDEO

MAJOR MODULES

Part Number

132160-00 132880-00 132325-00 132324-00 130945-00 122187-00 131747-00

Description

LOGIC BOARD ENHANCED GATE ARRAY LOGIC BOARD VIDEO MONITOR BOARD POWER SUPPLY KEYBOARD ASSEMBLY TUBE CRT 14" GREEN TUBE CRT 14" AMBER

PCB ASSEMBLY LOGIC BOARD

Determine whether you have a gate array logic board or an enhanced gate array logic board, then refer to the appropriate parts list (page 3-5 for tbe gate array: page 3-7 for the enhanced gate array.

PCB ASSEMBLY GATE ARRAY LOGIC BOARD - PART NUMBER 132160-00

Part Number Description Location

130236-00 IC MICROPROCESSOR 6sC02 3-MHZ U1 120272-00 IC 74LS139 2X 1 OF 4 DECODER U2 120292-00 IC 7s188N 4X LINE DRIVER U3, 12 180002-78* IC SYSTEM EPROM 2764 U4 180002-79* IC SYSTEM EPROM 2764 US 180002-88* IC SYSTEM EPROM 27128 U4 180002-91* IC SYSTEM EPROM US 121387-00 IC 2K x 8 CMOS STATIC RAM U6 120294-00 IC 7s189A 4X LINE RECEIVER U7, 8 120530-00 IC SY6ss1A/1 2-MHZ SYNIAMI U9, 10, 11 120242-00 Ie 74LSOO 4X 2-IN NAND GATE U13, 39 130234-00 IC 2674 AVDC 4-MHZ U14

*Before ordering, check the part number on the EPROM(s). You must replace the EPROM(s) with the same type and combination you removed. The three possible combinations are:

1. Two 2764 EPROMs (piN 180002-78~ PiN 180002-79) 2. One 27128 EPROM - PiN 180002-88 3. PiN 180002-91; PiN 180002-88

3-5

Table 3-2 (Continued) - 955 Parts Reference List


Part NUDlber

120376-00 120274-00 120362-00 131609-00 120258-00 120416-00 131634-00 131615-00 120348-00 131614-00 120290-00 131405-00 131612-00 120266-00 131611-00 120456-00 120388-00 120252-00 180002-26 120246-00 131551-00 120469-00 131154-00 131155-00 122168-00 131386-00 121440-00

120517-00 120521-00

120533-00 120381-00 126182-00 120531-00

120341-00 126184-00 131829-00 120337-00 120371-00 120413-00 120427-00 120429-00 130177-00

Description

IC 74LS273 ax D-TYPE FF IC 74L8157 4X2-IN DATA SEL/MLT IC 74LS245, N8T245N IC 74HC04 HEX INVERTER IC 74LS32 4X 2-IN OR GATE IC 74LS02 4X 2-IN NOR GATE IC STATIC RAM 8K x 8 lOOns. IC ST.ATIC RAM 2K x 8 lOOns. IC 7406 6X INVTR BFR/DRVR IC 8211 PROG VOLT REG IC 74LS374 8X D-TYPE FF IC GATE ARRAY TVI 16 IC 74AS194 4-BIT SHIFT REG IC 74LS74 2X D-TYPE E-TRIG FF IC 74AS163 SYNC 4-BIT COUNTER IC 74S51 AND-OR INVTR GATE IC 74832 4X 2-IN POS OR GATE IC 74LS08 4X 2-IN AND GATE IC ROM 955 CHAR GEN IC 74S04 6X INVTR TRAN 2N4264 NPN TRAN 2N2222A NPN/SILICON CRY 19.3396-MHZ OSC CRY OSC 31.684-MHZ CRY 3. 6864-MHZ BATTERY LITHIUM CYLINDER RES CF 82 OHM 1/4W 5%

RES CF 470 OHM 1/4W 5% RES CF 1000 OHM 1/4W 5%

RES CF 180 OHM 1/4W 5% RES CF '4.7 OHM +/-5% RES MF 22K OHM 1/4W +/-1% RES CF 4700 OHM 1/4W 5%

RES CF 10K OHM 1/4W 5% RES MF 1M OHM 1/4W -t-/-l% RES MF 71.5K OHM 1/4W 1% RES CF 47K OHM 1/4W 5% RES CF 680 OHM 1/4W 5% RES PK 4.7K OHM lOP SIP RES PK 1K OHM 8P SIP RES PK 4.7K OHM 8P SIP CAP TANT 4.7uF 16V +/-20%

3-6

Location

U15 U16, 17, 21, 22 U18, 20 U19 U23, 27, 46, 47 U24 U25, 31 U25, 26, 30, 31 U28 U29 U32, 33, 35 U34 U36, 37, 42 U38 U40 U41 U43 U44 U45 U48 01-3 04 Yl Y2 Y3 B1 Rl-5, 9, 10, 13, 24 R6 R7, 12, 14, 28, 34 R8 R11 R15 R16, 21, 23, 25, 26, 36, 37 R17, 35 RIB R19 R20, 27 R29 RP1 RP2 RP4 C2, 114



Part Number Description

130172-00 CAP GL PK .1uF 25V +80%

130190-00 CAP GL PK .001uF 25V +80 -20 130175-00 C1\P ELEC 22uF 16V +80% 130173-00 CAP GL PK 330pF 25V +/-20%

130183-00 CAP GL PK 100pF 50V +/-10% 130176-00 CAP ELEC 10uF 16V +80% 130179-00 CAP GL PK 47pF 50V 120279-00 CAP ELEC 1uF 16V 10% 120251-00 CAP MICA 150pF 500V 1% 120301-00 CAP CER .1uF 50V 10%

Location

C3, 6, 7, 100-105, 108-110, 112, 116, 118, 124, 126-129, 131, 132 C5 C9, 11-13 C14-20, 24-27, 34-36 C21, 38 C28-30 C31, 33, 40, 47 C37 C43, 45 C106, 107, Ill, 113, 115, 117, 119-123, 125, 130, 134, 135, 136, 137, 138

120475-00 131746-00

DIODE 1N914 CR3, 5-7, 9-11 DIODE IN5817 SCHOT BAR RECT lA CR8

ENHANCED GATE ARRAY LOGIC BOARD - PART NUMBER 132880-00


131614-00 IC 8211 PROG VOLT REG U2 123620-00 IC 74LS132 4X 2-IN NAND SCHMITT U3 130236-00 IC 65C02 MICROPROCESSOR 3 MHZ U4 120294-00 IC 75189A 4X LINE RECEIVER U5, 9 120348-00 IC 7406 INVERTER BFR/DRVR U7, 40 120252-00 IC 74LS08 4X 2-IN AND GATE U8, 42 120258-00 IC 74LS32 4X 2-IN OR GATE U11, 24,

34, 43 120292-00 IC 75188 4X LINE DRIVER U13, 17 180002-88 IC SYSTEM EPROM CO-FF U14 180002-91 IC CALCULATOR EPROM U15 270992-00 IC STATIC RAM 2K X 8 CMOS 150ns U16 120388-00 IC 74S32 4X 2-IN POS OR GATE U18 120272-00 Ie 74LS139 2X 1 OF 4 DECODER DI9 120530-00 Ie SY6551A/l 2 MHZ SYN/AMI U20-22 120276-00 IC 74LS163 SYN 4-BIT COUNTER U23 120362-00 IC 74LS245, N8T245N U25, 30 120274-00 Ie 74LS157 4X 2-IN DATA SEL/MLT U26, 27,

31, 32 130234-00 IC 2674 AVDC 4 MHZ U28 131609-00 IC 74HC04 HEX INVERTER U29 120290-00 IC 74LS374 8X D-TYPE FLIP-FLOP U33, 47

3-7




270958-00 IC STATIC RAM 8K X 8 lOOns CMOS U36, 45 270947-00 IC GATE ARRAY TSI-19 U37 270737-00 IC 74F166 8X SHIFT REGISTER U38 120376-00 IC 74LS273 8X D-TYPE FF U39 120248-00 IC 74LS04 6X INVERTER U44 180002 ... 26 IC CHARACTER GENERATOR U46 120266-00 IC 74LS74 2X D-TYPE

E-TRIGGERED FLIP-FLOP U48 131386-00 BATTERY LITHIUM CYLINDER Bl 131746-00 DIODE IN5817 SCHOT BAR RECT L~ CRl, 4,

5, 9 120475-00 DIODE IN914 CR2, 3,

6-8 120469-00 TRAN 2N2222A NPN/SILICON Ql 131551-00 TRAN 2N4264 NPN Q2, 4 122168-00 CRYSTAL 3.6864 MHZ Yl 131154-00 CRYSTAL 19.3396 MHZ OSC Y2 131155-00 CRYSTAL OSC 31.684 MHZ Y3 120531-00 RES CF 4700 OHM 1/4W 5% R1, 7, 8, 10

17, 18, 22, 23, 28, 44, 45, 50, 51, 55, 56, 59, 61, 62

126184-00 RES MF 1M OHM 1/4W +/- 1% R2 131829-00 RES MF 71.5K OHM 1/4W 1% R3 126182-00 RES MF 22K OHM 1/4W +/- 1% R4 120337-00 RES CF 47K OHM 1/4W 5% R5 120521-00 RES CF 1000 OHM 1/4W 5% R6, 11-13,

15, 25, 26, 30, 32-37, 39, 41, 42, 52-54, 57

120341-00 RES CF 10K OHM 1/4W 5% R9 120371-00 RES CF 680 OHM 1/4W 5% R14 121440-00 RES CF 82 OHM 1/4W 5% R19, 21, 43,

47, 48, 49, 29 270414-00 RES CF 2.2M OHB 1/4W R24 121770-00 RES CF 820 OHM 1/2W 5% R27 120517-00 RES CF 470 OHM 1/4W 5% R31 120533-00 RES CF 180 OHM 1/4W 5% R38 120381-00 RES CF 4.7 OHM +/- 5% R40 120365-00 RES CF 240 OHM 1/4W 5% R46 120373-00 RES CF 27K OHM 1/4W 5% R60 120429-00 RES PK 4.7K OHM 8-PIN SIP RPI 130175-00 CAP ELECT 22uF 16V +80% C1, 82, 87, 88 130172-00 CAP GL PK .1uF 25V +80% C3 120251-00 CAP MICA 150 pF 500V C4, 20 130179-00 CAP GL PK 47pF 50V C5, 7, 27 I 53

3-8



Part Number Description

130176-00 CAP ELECT 10uF 16V +80% 120301-00 CAP CER .1uF 50V 10%

130174-00 CAP GL PK .01uF 25V +80% -20% 130183-00 CAP GL PK 100 pF 50V +/- 10% 130173-00 CAP GL PK 330pF 25V +/- 20%

120279-00 CAP ELEC 1uF 16V 10% 130177-00 CAP T.ANT 4. 7uF 16V +/- 20%

Location

C6, 38 C8, 9, 12, 22, 25, 28, 29, 35, 37, 39, 40, 42, 47-52, 55-62, 64-66, 68-72, 74-77, 79, 83, 85, 86, 89, 90, 92 CI0 C11, 19 C13-18, 30-34, 43-46, 73 C26 C67; 78

PCB ASSEMBLY VIDEO MONITOR BOARD - PART NUMBER 132325-00

270884-00 270883-00 120485-00 241301-00 241300-00 270882-00 122022-00 242817-00 242816-00 241020-00 241021-00 242000-00 120441-00 121801-00 120377-00 131800-00 121770-00 120403-00 120531-00 240102-00 240104-00 ')Anln'l_nn ~-.r""'...LV"" "Vv

120337-00 240108-00 131502-00 249700-01 240105-00 240106-00 240107-00 121967-00

TRAN KTC 2235(0) TRAN BU406 DIODE 1N4148 SWITCH DIODE MR856 DIODE BA159 DIODE 1N4755 DIODE 1N4004 MOT TRANS H DRIVE HDT~955 TRANS FLYBACK KFS-20867 COIL LINEARITY FIXED YEL DOT COIL WIDTH W-955 IC VERT AMP TDA-1170N POT TRIM lOOK OHM TOP-ADJ PCMT POT FOCUS 2M OHM RES CF 47 OHM 1/4W +/-5% RES CF 22K OHM 1/4W 5% RES CF 820 OHM 1/2W 5% RES CF 220 OHM 1/4W 5% RES CF 4700 OHM 1/4W 5% RES CF 180K OHM 1/4W RES CF 220K OHM 1/4W RES CF 390K OHM 1/4W RES CF 47K OHM 1/4W 5% RES MF 1.0 OHM 1W RES CF 68K OHM 1/4W +/- 5% RES CF 33K OHM 1/4W RES CF 56K OHM li4W RES CF 3.3 OHM 1/4W RES CF 3.3 OHM 1/2W CAP ELEC 4.7uF 16V

3-9

Q301 Q302 0301 0302, 303 0502-504, 506 0505 0601 T301 T302 L301 L302 IC1 SFRl, 2, 4 VR2 R301, 501 R302 R504 R512 R601, 611 R603 R602, 606 R604 R605 R607 R608 R609 R610 R613 R614 C301


PCB ASSEMBLY VIDEO MONITOR BOARD - PART NUMBER 132325-00

Part Number

249017-00 240910-00 241124-00 130127-00 249032-00 240909-00 130827-00 130186-00 270880-00 130126-00 240907-00 240908-00 24901S-00 249003-00 1219S9-00 121962-00 249027-00 240700-00

ADDITIONAL

131219-00 131158-00 131159-00 131157-00 121700-00 120455-00 121390-00 122151-00 130948-00 130949-00 132189-00 123361-00 122161-00 132165-00 132166-00 132155-00 132143-00 132144-00 132145-00 132195-00 122985-03 122985-01 132172-00 132167-00 132158-00 132441-00 131969-00 131968-00

Description Location

CAP PF O.OluF SOV CAP PF O.OOluF 400V CAP PP .01uF 630V CAP ELEC 220uF 2SV CAP ELECT 6.8uF 2SV NON-POL CAP PF 0.22uF SOV CAP ELEC 100uF 100V RADIAL CAP CER .02uF SOV CAP MF .01uF 800V 10% RA.D CAP PF .033uF 400V CAP PF O.luF SOV CAP PF O.lSuF SOV CAP ELEC 2200uF 16V CAP ELECT 100uF 2SV CAP CER 220pF SOV CAP ELEC 2200uF 10V CAP ELECT 47uF 25V CAP CER 470pF 50V

PARTS

KEYCAP KIT KEYSWITCH NONLOCKING KEYSWITCH NONLOCKING MAR KEYSWITCH LOCKING IC 74LS145 (KYBD) (U3)

C302 C303 C304 C30S C306 C307

LOS CS02 CS03 CS04 CS07 C601, C602 C60S C606 C607 C608 C609 C612

TRANSISTOR 2N4401/2SC1166 (KYBD - Ql) KYBD CPU (8049) (U2) TRANSDUCER AUDIO (KYBD) HSG KEYBOARD TOP HSG KEYBOARD BOTTOM OVERLAY FUNCTION KEY 955 BLANK PWR CORD 3-COND SHLD lOA 125V CBL ASY 6 CONDUCTOR RJ12 BEZEL HSG REAR BA.SE PEDESTAL, OUTER SHIPPING CARTON SHIPPING CARTON STYROFOAM RT SHIPPING CARTON STYROFOAM LEFT FUSE HOLDER

603,

FUSE 1.5 AMP 250V SLOW BLOW (115V ONLY) FUSE .75 AMP 250V SLOW BLOW (230V ONLY) CONTRAST POT BRIGHTNESS KNOB PANEL RE.AR PEDESTAL CURRENT LOOP KIT OPERATOR'S MANUAL 955 M~INTENANCE MANUAL 955

3-10

604, 611

OVERVIEW

Determine the type of logic board in your terminal, then refer to the theory of operation that applies to your board.

For Gate Array models (part number 132160-00 - Gate Array location U34), read the information starting on page 4-1 .

For Enhanced Gate Array models (part number 132880-00 - Gate Array location U37), read the information starting on page 4-13 .

NOTE: You can determine the type of logic board by comparing the board to the illustrations in Section 2 of this manual.

GATE ARRAY LOGIC BOARD THEORY OF OPERATION

The terminal logic is based on a 65C02 B-bit microprocessor rated at 3 MHz, capable of addressing 65K bytes of memory.

Figure 4-1 shows a block diagram of the gate array logic board.

Refer to the schematic diagram in Section 2 while reading the Theory of Operation that follows.

Clock Circuit (See sheet 5 of the schematic)

The 955 has two display modes: BO-column and 132-column. Two clock oscillators (Yl and Y2) accommodate the two modes. Yl oscillates at 19.3396 MHz and serves as the basic clock in BOcolumn mode. Y2 oscillates at 31.0B4 MHz and serves as the basic clock in 132-column mode.

One half of U41 (a 74S51 AND/OR INVERT) selects Yl or Y2. The level on the BO/132 line determines which oscillator's output appears at pin 6 of U41. This output, DOT CLOCK, serves two purposes: as a c lock to shi ft v ideo da ta through a shi ft register (see CHARACTER GENERATION, page 4-9) and as a clock for a divide-by-nine counter (U40). The 955's character cell is nine pixels wide: thus, the divide-by-nine counter.

U40 (74AS163) provides the basis for the CPU system clock and for the character clock used by the CRT controller (AVDC SCN2674 -U14).

The CRT controller uses the CCLK BAR* signal as the character clock. ~n inversion of this clock, CCLK, generates the CPU system clock or Phi zero (00).

*Signals referred to as "SIGN~L BA.R" appear on the schematic as SIGNAL.

4-1

31. \/84 MHz

POWER DOWN/ RESET

CIRCUIT

CPU 65CIi!2

IlO

CLOCK

~ RESET

,...-._- --------'

11~US

I SYS EPROM I NONVOLII.TILE I 2764 (2) CS S~~i~\~

'"'r------------"r ~ _IBII.TTERY I

SYS RESET

CS R/W'--__ -I

NONVOLII.TILE I RII.M CONTROL

-

r----~ BUS '------1 t t CSR/W

~~ I :::;~~~' -----".. ,."

j"il"SELECTS

--CS

~ ~SYNC

_I\.

NMI_- ----v' ~SYNC

CCLK

CS __ CONT lATCH

-

MUX LS157

(4)

AVDC CIRCUIT ... A

2674 DII.TII. BUS

""

~CCLK DISPLII.Y 1'.DDRESS BUS

~BLII.NK '--___ ..J

~ rV

r-"--

-

-CHII.R A RII.M 6116 "'r (2 )

-

LII.TCH LS374

CCLK-----'

.J\. LATCH

roI LS374

BI,INK CLK __

LA.ST LINE~

BLA.NK

=) ~

-y

CHA.R GEN 2332

GII.TE II.RRA.Y

ITR1'.NSCEIVERI

~

LII.TCH LS374

BI.A.NK------' t

I-----i~ BLINK CLK

.------1~ LAST LI NE

!----VIDEOVTO VIDEO FROM (~H SYNC MONITOR A.VDC __ V SYNC

SHIFT REG 11.5194 (3 )

The CPU system clock and character clock are synchronized and interleaved (see SCREEN DATA STORAGE, page 4-11). This allows the same clock to be used for system timing and for display generation.

Two considerations require CCLK to be modified for use as the system clock. They are: 1) the CPU's 3 MHz frequency limitation; and, 2) the requirement that any speed Universal Asynchronous Receiver Transmitter (UART) be used.

To overcome the CPU's speed limitation, CCLK is divided by 2 when in 132-column mode (see discussion in the next paragraph). To allow the use of any speed UART, the system clock is stretched out whenever the UARTs are accessed by the CPU (see discussion under Clock Stretch Timing).

In l32-column operation, the character clock is 31.084 MHz divided by 9, or 3.454 MHz. Dividing by 2 overcomes the CPU's 3 MHz frequency limitation while allowing the character and system clocks to be synchronized and interleaved. This is accomplished by half of U38 (a D-type flip-flop connected in toggle mode, thus dividing by 2). The Q BAR* output of U38 (pin 6) is connected to one input of the second section of U4l (74S51). The other input to U41 is CCLK.

In 132-column mode, the output of U38 is used for Phi zero; in 80-column mode, CCLK is used for Phi zero.

Clock Switching

Clock switching occurs in the following way. When the system clock is switched from 132-column mode (divide-by-2) to 80-column mode, or vice versa, the transition must occur during the inactive or low portion of the clock being switched to. Two gates of U39 are cross-connected to form a simple set/reset flipflop. The outputs of the flip-flop control which clock is gated to the output of U4l (pin 8).

When the 80/132 line switches from low to high under system control (going to l32-column mode) the U39 flip-flop will not change state unless the Q output of U38 is high (0 BAR* is low). Conversely, when the 80/132 line switches from high to low, the U39 flip-flop will not change unless CCLK is low. This timing is illustrated in Figure 4-2.

*Signals referred to as "SIGNAL BAR" appear on the schematic as SIGNAL.

4-3

Figure 4-2 Clock Switching

80/132 80

CCLK

U38-6 (0)

U39-6

~O

Clock Stretch Timing

132

Clock Stretch Timing occurs in the following sequence:

Using SYSTEM RESET BAR*, U38** is initialized with Q BAR* output high (pin 8). This gates the output of U4l directly through NAND gate U39 to be used for Phi zero. If the output of U4l is low and COMM BAR* (a CPU address bus decode that signifies a UART access) is low, a positive edge is provided to the clock input of U38. This causes the Q BAR* output to toggle low, which in turn holds Phi zero high.

COMM BAR* remains low as long as Phi zero is high, allowing the next negative transition of U41 ' s output to toggle U38 again, which returns it to the initialized state. This timing is illustrated in Figure 4-3.


**The remaining half of U38 is connected in toggle mode.

4-4

Figure 4-3 CPU Clock Stretch Timing

U4l-8

The three other clocks provided by the clock circuitry are: DeC, Dec BAR* and Ql BAR*.

Dec is used to load parallel character data into the video shift register (see Display Generation, page 4-10).

Dec BAR* is used to latch attribute data and display control signals into the gate array (see Display Generation, page 4-10).

Ql BAR* is used to produce the signals necessary to properly write data into the character and attribute RAMs (see Screen Data Storage, page 4-11).

*Signals referred to as IISIGNAL BARil appear on the schematic as SIGNAL.

4-5

CPU System And Control (See sheets I and 2 of the schematic)

The CPU system consists of the CPU (6SC02 - Ul), the address bus decoder (74LS139 - U2, plus some gates), the system EPROMs (2764 1 s - U4 and US), system RAM (6116 LP4 - U6), the system reset circuit, and the control latch (74LS273 - UI5).

The CPU is the controller for the entire board, initializing and controlling all of the UARTs, the CRT controller, the clock circuits and the video gate array. It also processes all of the data received from the keyboard, computer or printer, and updates the screen RAM accordingly.

Many of the display features, such as smooth scrolling and line lock, are controlled by the CPU in conjunction with the CRT controller.

Each device on the board has a specific address or range of addresses, as shown on the memory map (see Table 4-1).

The decoder chip (U2) provides the chip selects for all the devices on the memory map. Section one of this chip divides the 65K address range of the 6SC02 into four 16K blocks.

The highest range block is used to select the system EPROMs, which contain the system firmware (a specialized operating system). The next lower 16K block is used for character RAM, which with attribute RAM (the next lower 16K block), is expandable to 16K bytes. The lowest 16K block is divided into four, 4K blocks by the second section of U2 and is allocated as follows.

The highest 4K block selects the optional system ROM, if it is installed. The next lower 4K block selects the CRT controller. The next lower 4K block selects the UARTs, graphics option board, and control latch. The lowest 4K block selects system RAM.

System RAM serves two purposes in the 955. Part of the RAM is used by the firmware as the stack and other temporary data stores, such as input and output buffers. In addition, the RAM is backed up by a battery, thus retaining the data even with power switched off. This allows portions of the RAM to be used for function key programming and to retain initialization parameters.

To retain data two things must occur: 1) the voltage to the RAM must not fall below 2 vol tSi and, 2) the RAM must be deselected as power from the power supply discharges.

Voltage is maintained by the battery (Bl). Deselecting the RAM is accomplished by using a transistor (Ql) in series with the chip select signal from the decoder (see discussion in the next paraqraph) .

4-6

Table 4-1 Memory Map

FFFF

FOOO DFFF

COOO BFFF

8000 7FFF

4000 3FFF

3000 2FFF

2000 18FF

1800 14FF

1400 12FF

1200 11FF

1100 10FF

1000 OFFF

0000

SYSTEM ROM

SYSTEM ROM

CHARACTER RAM

ATTRIBUTE RAM

OPTION ROM

CRTC

HOST UART

PRINTER UART

KEYBOA.RD UART

CONTROL LATCH

GRAPHICS OPTION

SYSTEM RAM

4-7

with power on, SYSTEM RESET BAR* is high, turning 01 on and allowing the chip select signal to go to the RAM. When power goes away, the SYSTEM RESET BAR* signal goes low when +5 volts falls below 4.4 volts. This turns 01 off, causing pin 18 of the RAM to follow the voltage at the junction of CR3 and R29. This voltage drops at the same rate as +5 volts until the battery voltage is reached (typically 2.8 to 3 volts), at which time the battery voltage takes over. As an added precaution, pin 21 of the RAM (WE BAR*) is also deselected during power down (02).

The CPU system uses the control latch to give the firmware control over some hardware devices that do not interface to the data bus. Starting with the 00 output of U15, the control latch1s output signals are:

DTR Data Terminal Ready. A signal sent to the host computer telling it to stop transmitting data to the 955 (DTR high).

HIGH SPEED Used to control the transmit and receive clock to the computer port UART. When this signal is high, the clock frequency is 3.6864 MHz; when it is low, the frequency is 1.8432 MHz. This allows for a maximum baud rate of 38.4 Kbaud in high-speed mode.

MODEM Used only if an internal modem is installed in the 955. When this signal is low, the internal modem interfaces with the computer port UART; when it is high, the RS232 interface is used.

BOG/GOB Connects to the video gate array and is used to control the normal background of the display. A low on this line provides a light background; a high produces a dark background.

LINE/PAGE ATT Connects to the video gate array. Causes the selected attribute to carry to the end of the present character row (low) or to the end of the display (high).

EMB/NONEMB Connects to the video gate array and controls the appearance of the attribute character. In embedded mode (space), the attribute character appears as a half-intensity space and prevents displaying data in the attribute character position. In nonembedded mode (no space) the attribute character does not appear and it is possible to display data at any location on the screen.


4-8

The reset circuit is shown on sheet 1 of the schematic. For the CPU to initialize properly, the RESET BAR* input (pin 40) must be held low for a minimum of six system clock cycles after voltage is at the operating level (4.75 volts minimum).

The node labeled SYSTEM RESET BAR* is controlled by the outputs of three devices: U29, U28 and Q4. Until the +5 volts reaches the operating level for these devices, their outputs are in a high-impedance state (not being driven to either a high or low state). During this period the node is held low by pull-down resistor R36.

When the voltage reaches the 1.6-volt level, U29 begins to drive the node low and continues to do so until the voltage gets above 4.6 volts. At the 2.2-volt level the output of U28 also begins to drive the node low and continues to do so until the level on pin 4 0 f U 1 3 rea ch est he 2.2 - v 0 I tIe vel. Th i sis del aye d by the RC network consisting of R20 and C28. The result is that SYSTEM RESET BAR* is held low for 60 to 80 milliseconds after +5 volts reaches the 4.75-volt level.

When all the devices stop driving the node low, a high level is applied to the node through Q4, which serves as an active pull-up with a delayed response relative to +5 volts. This prevents the node from following +5 volts during the early stages of a powerup sequence (when +5 volts is lower than 1.6 volts).

At power-down the controlling device is U29. Its output is driven low when the supply goes below 4.4 volts. This is not necessary for proper operation of the CPU, but is critical for the integrity of the battery backed-up RAM.

Character Generation (See sheet 4 of the schematic)

The 955 uses character cells, rather than a full bit-mapped display, to produce characters on the screen. Each character cell is 9 pixels wide by 14 pixels high. The screen consists of either 3432 (132 x 26) character cells in l32-column mode, or 2080 (80 x 26) character cells in 80-column mode. Each of the 256 possible characters is pre-defined and resides in the character generator ROM (U45). The CPU changes the display by changing the code stored in the screen RAMs at the desired location{s).

The codes written into the screen RAMs are read out as the CRT controller refreshes the display (see Display Generation, page 4-10). As each code is read out, one per character clock cycle, it is latched into the character address latch (U32).

*Signals referred to as "SIGNAL BARil appear on the schematic as SIGNAL.

4-9

The outputs of the character address latch are used as the highorder address lines of the character generator ROM. The loworder addresses are provided by the scan line address latch (U33), which latches the line address outputs of the CRT controller. At the end of the character clock cycle, DCC (left side of sheet 4) goes high for one DOT CLK cycle.

Wi th DCC high, the next rising edge of DOT CLK wi 11 load the DO through D7 outputs of the character generator into a nine-bit shift register consisting of U36, U37 and U42 (74AS194 or 748194). When DCC goes low again, the data is shifted out of the QC output of U42 (pin 13) until the complete byte has been shifted out. The output of the shift register (U42, pin 13) connects to the video gate array (U34), where it is combined with other signals to create the video signal to the video monitor board.

Under certain conditions, two of the shift register's inputs are connected to provide a character cell nine pixels wide without using a special 9-bit wide ROM. In normal text mode, D7 from the character generator is always a low (zero), creating a single dot space on the left side of each character cell. The DC input of U36 (pin 5), which becomes the dot on the right in the character cell, is loaded into the shi ft regi ster as a low unless the D7 output of the character address latch (U32) is high.

If D7 is high, the DC input of U36 will be the same as the DD input of U36. This allows characters that need to use the entire width of the character cell, such as line drawing graphics, to do so.

Character address codes 00 through 7F cannot extend the entire width of the character cell~ character codes 80 through FF can.

Display Generation (See sbeets 3 and 4 of tbe scbeaatic)

The video monitor board requires three signals from the logic board to produce a display on the CRT: vertical sync (VSYNC BAR*), hurizontal sync (H8YNC), and video.

VSYNC BAR* and HSYNC originate from the CRT controller (U14). They are buffered and connect to the video board through pin 5 (VSYNC BA.R*) and pin 1 (HSYNC) of P2. Video comes from the video gate array (U34). It goes through a NOR gate (U24) and a highcurrent open collector inverter (U28).

*Signa1s referred to as IlSIGNA.L BARil appear on the schematic as SIGNAL.

4-10

HSYNC and VSYNC BAR* are timed pulses derived by the CRT controller from internal programmable counters that count CCLK cycles. For example, HSYNC might be a positive-going pulse starting 80 CCLK cycles after the beginning of each scan line and lasting 16 CCLK cycles. The CRT controller·s internal counter would reset at the beginning of each scan line, count to 80, set HSYNC high, count 16 more CCLKs and set HSYNC low.

VSYNC is a much slower signal based on scan lines. Another counter inside the CRT controller counts scan lines and toggles VSYNC according to the way the firmware has programmed the internal registers.

As the CRT controller (AVDC SCN2674 - U14) counts CCLKs, it is also putting out addresses on its display address lines (pins 21-34, DADDO-DADD13). These lines connect to four 74LS157 4-bit 2-way multiplexers (U16, U17, U2l and U22). The select inputs of the multiplexers are normally high, allowing the CRT controller·s address line to access the data in the screen RAMs.

As data in the screen RAMs is read out, it is latched into the character address latch (U32) for the character data bus and into the video gate array for the attribute data bus.

The serialized character data (see Character Generation, page 4-9), is fed into the video gate array where it is combined with attribute data, the BLANK output of the CRT controller, the cursor output of the CRT controller, the screen background control (BOG/GOB) and other signals to produce a series of pulses that come out on the VIDEO output of the gate array.

If the VIDEO output is high, the electron beam in the CRT is turned on, producing a light dot or series of dots on the screen. If VIDEO is low, the screen is dark.

Screen Data Storage (See sheets 2 and 3 of the schematic)

If the CPU needs to access either the character or attribute RAMs, the corresponding signal, CHAR RAM BAR* or ATT RAM BAR* goes low for a full CPU cycle. Since the CPU clock can be running at half the speed of the character CCLK (see Clock Circuit, page 4-1), both of these signals are gated with CCL~ BAR*.

When CCLK BAR* is low, the CRT controller is at the beginning of a character clock cycle and its address lines are not stable. However, during this period the CPU·s address lines are stable and the CPU is either putting data on the data bus or is looking for data from the selected device.

Gating CHAR RAM BAR* and ATT RAM BAR* with CCLK BAR* and then ANDing the resulting signals produces a low on the select inputs


4-11

(pin 1) to the multiplexers during this period of the CPU cycle. This allows the CPUls address lines to drive the screen RAMs.

The outputs of the two gates used to gate CHAR RAM BAR* and ATT RAM BAR* with CCLK BAR* (74LS32, U46 pins 1-6) are connected to the CE BAR* inputs to U20 and U18. U20 and U18 are B-bit transceivers used to isolate the CPU data bus from the character data bus and the attribute data bus (CDO-7 and ADO-7).

The direction control input to the transceivers (pin 1) is created by gating CCLK BAR* with R/W from the CPU (U46, pins 11-13). In this manner, the CPU can write data to or read data from the screen RAMs (either character or attribute) without interrupting or interfering with the CRT contro11er ' s process of refreshing the screen.

Communications (See sheet 6 of the schematic)

There are three serial communications channels. Each has its own dedicated UART and can send and receive data at speeds ranging from 50 to 19,200 bits per second (3B,400 for the computer port).

U11 (6551A) is the UART used for communication to the host computer. It interfaces to a 25-pin D-subminiature connector (P3) via TTL to RS-232 level converters (U7 and UB, 14B91s~ U3 and U12, 148B ' s).

The baud rate is selectable under firmware control and is derived from the clock going in on pin 6 (XTAL 1). For the normal baud rate range of 50 to 19.2K, a 1.B432-MHz clock is used. When the 38.4K baud rate is selected, the firmware must also increase the clock input to 3.6864-MHz. It does this by using the HIGH-SPEED control line of the control latch (see CPU System and Control, page 4-6).

UIO is the UART dedicated to printer communications. It interfaces to a 25-pin D-subminiature connector (P4) via the same chips as Ul1. Its clock input is fixed at 1.8432 MHz, allowing the 50 to 19.2K baud range.

U9 is the UART llsed to communicate with the keyboard. Its clock input is also fixed at 1.B432 MHz and is capable of communicating at 50 to 19.2K baud. Since the keyboard's baud rate is 9600 baud, the firmware programs U9 to always communicate at this speed.

The IRQ BA~ outputs for all three UARTs are tied together in a wired OR configuration. When any of the UARTs generate an Interrupt Request (IRQ), the IRQ BAR* line goes low, signaling to the CPU that an interrupt has occurred. The CPU then polls the UARTs to determine which one generated the interrupt, and processes the interrupt as required.

*Signals referred to as "SIGNAL 8.l-\R" appear on the schematic as SIGNA.L.

4-12

ENHANCED GATE ARRAY LOGIC BOARD THEORY OF OPERATION

The terminal logic is based on a 65C02 8-bit microprocessor rated at 3 MHz, capable of addressing 65K bytes of memory.

Figure 4-4 shows a block diagram of the enhanced gate array logic board.

Refer to the schematic diagram in Section 2 while reading the Theory of Operation that follows.

Clock Circuit (see sheets 1, 2, 3, and 4 of the SChematic)

The 955 has two display modes: 80-column and 132-column. Two clock oscillators (Y2 and Y3) accommodate the two modes. Y2 oscillates at 19.3396 MHz and serves as the basic clock in 80-column mode. Y3 oscillates at 31.084 MHz and serves as the basic clock in 132-column mode.

The gate array (U37) selects Y2 or Y3. The SDOTCK output from the gate array serves two purposes: as a clock to shift video data through a shift register (see Character Generation, page 4-19) and as a clock for a divide-by-nine counter within the gate array. The 955's character cell is nine pixels wide~ thus, the divide-by-nine counter.

All system clocks are created inside the gate array. It provides the basis for the CPU system clock and for the character clock (CCLK BAR*) used by the CRT controller (2674 AVDC - U28). An inversion of this clock (CCLK) generates the CPU system clock or Phi zero (00).

The CPU system clock and character clock are synchronized and interleaved (see Screen Data Storage, page 4-21). This allows the same clock to be used for system timing and for display generation.

Two considerations require CCLK to be modified for use as the sxstem clock. They are: 1) the CPU's 3 MHz frequency Ilmitation~ and, 2) the requirement that any speed Universal Asynchronous Receiver Transmitter (UART) be used.

To overcome the CPU's speed limitation, CCLK is divided by 2 when in 132-column mode (see discussion in the next paragraph). To allow the use of any speed UART, the system clock is stretched out whenever the UARTs are accessed by the CPU.

*Si.gnals referred to as "SIGNAL BAR" appear on the schematic as SIGNA.L.

4-13

POWER DOWN/ RESET

CIRCUIT

CPU 6'iC02

IRQ~---Il

..--_ct HL--_____ ---.. DII.TA BUS I II I----+-

SYS RESET

.-------, }r-----.----.~}

I SYS EPROM 2764 (2)

-CS I NONVOLATILE J SYSTEM RAM 6116 LP

CS

~ _I BATTERY 1

R/W ..... __ ......

SYS RESET NONVOLII.TILE I RAM CONTROL

ADDRESS BUS r-----,

DECODE LOGIC

-------

t t_ cs R/W

) v

MUX r~S157

(4)

NMI..----i H SYNC

AVDC 2674

-------V SYNC

A DATI\. BUS

DISPLAY ADDRESS BUS

-----.. BLANK

r---",

rY

~ r--v

--

7

ITRANSCEIVERI

~

ATT Vt- ~ RAM N LATCH

6116 Y LS374 (2 )

"---

CCLK-

r---

CHAR ~ RAM LATCH

6116 N- rV LS374 (2 )

'--

I TRII.NSCE IVERI

;...

" LATCH

Y 2

L-...

1'-.

.. BLINK CLK .... LAST LINE ....

BLANK

I ~ ~

y

CHAR GEN 2332

Y3

t

GATE ARRAY

LS374 t----.... BLINK CLK

t----.... LAST LINE

BLANK---------~t

----- V I DEO

v TO VIDEO

FROM ( .... H SYNC MONITOR AVDC .... V SYNC

00

t-----.... CcLi< CCLK

SHIFT REG AS194 (3 ) §

.... n

2' .... ell -

In 132-column operation, the character clock is 31.084 MHz divided by 9, or 3.454 MHz. Dividing by 2 overcomes the CPU's 3 MHz frequency limitation while allowing the character and system clocks to be synchronized and interleaved. This is accomplished by the gate array.

The other clocks provided by the clock circuitry are: LDSRB and Ql BAR*.

LDSRB is used to load parallel character data into the video shift register (see Display Generation, page 4-20).

Ql BAR* is used to produce the signals necessary to properly write data into the character and attribute RAMs (see Screen Data Storage, page 4-21).

CPU System And Control (see sheets land 2 of the schematic)

The CPU system consists of the CPU (65C02 - U4), . the address bus decoder (74LS139 - U19, plus some gates), the system EPROMs (U14 and U15), system RAM (6ll6 LP4 - U16), the system reset circuit, and the control latch (74LS273 - U39).

The CPU is the controller for the entire board, initializing and controlling all of the UARTs, the CRT controller, the clock circuits and the video gate array. It also processes all of the data received from the keyboard, computer or printer, and updates the screen RAM accordingly.

Many of the display features, such as smooth scrolling and line lock, are controlled by the CPU in conjunction with the CRT controller.

Each device on the board has a specific address or range of addresses, as shown on the memory map (see Table 4-2).

The decoder chip (U19) provides the chip selects for all the devices on the memory map. Section one of this chip divides the 65K address range of the 65C02 into four 16K blocks.


4-15

The highest range block is used to select the system EPROMs, which contain the system firmware (a specialized operating system). The next lower 16K block is used for character RAM, which with attribute RAM (the next lower 16K block), is expandable to 16K bytes. The lowest 16K block is divided into four, 4K blocks by the second section of U19 and is allocated as follows.

The highest 4K block selects the optional system ROM, if it is installed. The next lower 4K block selects the CRT controller. The next lower 4K block selects the UARTs, graphics option board, and control latch. The lowest 4K block selects system RAM.

Table 4-2 Memory Map

FFFF

FOOO DFFF

COOO BFFF

8000 7FFF

4000 3FFF

3000 2FFF

2000 18FF

1800 14FF

1400 12FF

1200 11FF

1100 10FF

1000 OFFF

0000

SYSTEM ROM

SYSTEM ROM

CHARACTER RAM

ATTRIBUTE RAM

I OPTION ROM

CRTC

HOST UART

PRINTER UART

KEYBOARD UART

CONTROL LATCH

GRAPHICS OPTION

SYSTEM RAM

4-16

System RAM serves two purposes in the 955. Part of the RA.M is used by the firmware as the stack and other temporary data stores, such as input and output buffers. In addition, the RAM is backed up by a battery, thus retaining the data even with power switched off. This allows portions of the RAM to be used for function key programming and to retain initialization parameters.

To retain data two things must occur: 1) the voltage to the RAM must not fa 11 be low 2 vol ts ~ and, 2) the RAM mus t be dese lected as power from the power supply discharges.

Voltage is maintained by the battery (BI). Deselecting the RAM is accomplished by using a transistor (Q2) in series with the chip select signal from the decoder (see next paragraph).

With power on, SYSTEM RESET BAR* is high, turning Q2 on and allowing the chip select signal to go to the RAM. When power goes away, the SYSTEM RESET BAR* signal goes low when +5 volts falls below 4.4 volts. This turns Q2 off, causing pin 18 of the RAM to follow the voltage at the junction of CR6 and R14. This voltage drops at the same rate as +5 volts until the battery voltage is reached (typically 2.8 to 3 volts), at which time the battery voltage takes over.

The CPU system uses the control latch (U39) to give the firmware control over some hardware devices that do not interface to the data bus. The control latch's output signals are:

DTR Data Terminal Ready. A signal sent to the host computer telling it to stop transmitting data to the 955 (DTR high).

HIGH SPEED Used to control the transmit and receive clock to the computer port UART. A maximum baud rate of 38.4 Kbaud is provided when the signal is high. When it is low, the frequency is 1.8432 MHz.

MODEM Used only if an internal modem is installed in the 955. When this signal is low, the internal modem interfaces with the computer port UART~ when it is high, the RS232 interface is used.

PROT MODE Protect Mode. A customer option determined by jumper W13. Identifies protect characters as half-intensity or reverse.

LITE/DARK Selects whether the screen background is light or dark. When the signal is low, the screen background is light~ when it is high, the screen background is dark.


4-17

LINE/PAGE ATT Connects to the video gate array. Causes the selected attribute to carry to the end of the present character row (low) or to the end of the display (high).

EMB/NONEMB Connects to the video gate array and controls the appearance of the attribute character. In embedded mode (space), the attribute character appears as a half-intensity space and prevents displaying data in the attribute character posi tion. .In nonembedded mode (no space) the attribute character does not appear and it is possible to display data at any location on the screen.

80/132 Selects between the 80-column mode and the l32-column mode. Clock frequencies are changed to correspond to the mode that is chosen.

The reset circuit is shown on sheets I and 2 of the schematic. For the CPU to initialize properly, the RESET BAR* input (pin 40) must be held low for a minimum of six system clock cycles after voltage is at the operating level (4.75 volts minimum).

The node labeled SYSTEM RESET BAR* is controlled by three devices: U2, the keyboard, and 01. Until the +5 volts reaches the operating level for these devices, their outputs are in a high-impedance state (not being driven to either a high or low state). During this period the node is held low by pull-down resistor R8.

When the voltage reaches the 1.6-volt level, U2 begins to drive the node low and continues to do so until the voltage gets above 4.6 volts. At the 2.2-volt level the output of U7 also begins to drive the node low and continues to do so until the level on pin 4 0 f U 3 rea ch est he 2. 2 - v 0 I tIe vel. Th i sis del aye d by the RC network consisting of R5 and C6. The result is that SYSTEM RESET BAR* is held low for 60 to 80 milliseconds after +5 volts reaches the 4.75~volt level.

When all the devices stop driving the node low, a high level is applied to the node through 01, which serves as an active pull-up with a delayed response relative to +5 volts. This prevents the node from following +5 volts during the early stages of a powerup sequence (when +5 volts is lower than 1.6 volts).

At power-down the controlling device is U2. Its output is driven low when the supply goes below 4.4 volts. This is not necessary for proper operation of the CPU, but is critical for the integrity of the battery backed-up RAM.


4-18

Character Generation (see sheet 4 of the schematic)

The 955 uses character cells, rather than a full bit-mapped display, to produce characters on the screen. Each character c ell i s 9 pix e 1 s wid e by 14 pix e 1 s high. Th esc r e e n con sis t s 0 f either 3432 (132 x 26) character cells in l32-column mode, or 2080 (80 x 26) character cells in 80-column mode. Each of the 256 possible characters is pre-defined and resides in the character generator ROM (U46). The CPU changes the display by changi ng the code stored in the screen RAMs a t the des ired location(s).

The codes written into the screen RAMs are read out as the CRT controller refreshes the display (see Display Generation, page 4-20). As each code is read out, one per character clock cycle, it is latched into the character address latch (U47).

The outputs of the character address latch are used as the highorder address lines of the character generator ROM (U46). The low-order addresses are provided by the scan line address latch (U33), which latches the line address outputs of the CRT controller. ~t the end of the character clock cycle, LDSRB goes low for one SDOTCK cycle.

With LDSRB low, the next rising edge of SDOTCK will load the DO through D7 outputs of the character generator into an eight-bit wide shift register (U38 - 74F166). When LDSRB goes high, the data is shifted out of the Q7 output of U38 (pin 13) until the complete byte has been shifted out. The output of the shift register (U38, pin 13) connects to the video gate array (U37), where it is combined with other signals to create the video signal to the video monitor board.

The ninth bit is decoded when the logic (U42 and U48) detects a graphic character, which then is shifted in serial as the last dot.

In normal text mode, D7 and DO from the character generator are always low (zero), creating a single dot space on the left (D7) and right (DO) of each character cell. The OS input of U38 (pin 1), which becomes the last dot on the right in the character cell, is loaded into the shift register as a low unless the Q7 output of the character address latch (U47) and DO are high.

If Q7 is high, the OS input of U38 will be the same as the DO input of U38. This allows nine-bit wide graphics characters that use the entire width of the character cell, such as line drawing graphics.

Character aaQ~ess codes 00 through 7F cannot extend the entire width of the character celli graphics character codes 80 through FF can.

4-19

Display Generation (see she~ts 3 and 4 of the schematic)

The video monitor board requires three signals from the logic board to produce a display on the CRT: vertical sync (VSYNC BAR*), horizontal sync (HSYNC), and video.

VSYNC BAR* and HSYNC originate from the CRT controller (2674 AVDC - U28). They are buffered and connect to the video board through pin 5 (VSYNC BAR*) and pin 1 (HSYNC) of P2. Video comes from the video gate array (U37). It goes through an AND gate (U42) and a high-current open collector inverter (U40).

HSYNC and VSYNC BAR* are timed pulses derived by the CRT controller from internal programmable counters that count CCLK cycles. For example, HSYNC might be a positive-going pulse starting 80 CCLK cycles after the beginning of each scan line and lasting 16 CCLK cycles. The CRT controller's internal counter would reset at the beginning of each scan line, count to 80, set HSYNC high, count 16 more CCLKs and set HSYNC low.

VSYNC is a much slower signal based on scan lines. Another counter inside the CRT controller counts scan lines and toggles VSYNC according to the way the firmware has programmed the internal registers.

As the CRT controller (2674 AVDC - U28) counts CCLKs, it is also putting out addresses on its display address lines (pins 21-34, D~DDO-DADD13). These lines connect to four 74LS157 4-bit 2-way multiplexers (U26, U27, U3l and U32). The select inputs of the multiplexers are normally high, allowing the CRT controller's address line to access the data in the screen RAMs.

As data in the screen RAMs is read out, it is latched into the character address latch (U47) for the character data bus and into the video gate array for the attribute data bus.

The serialized character data (see Character Generation, page 4-19), is fed into the video gate array where it is combined with attribute data, the BLANK output of the CRT controller, the cursor output of the CRT controller, LITE/DARK and other signals to produce a series of pulses that come out on the VIDEO output of the gate array.

If the VIDEO output of P2-4 is high, the electron beam in the CRT is turned on, producing a light dot or series of dots on the screen. If the VIDEO is low, the screen is dark.

*Signa1s referred to as "SIGN~L BAR" appear on the schematic as SIGNAL.

4-20

Screen Data Storage (see sheets 2 and 3 of the schematic)

If the CPU needs to access either the character or attribute RAMs, the corresponding signal, CHAR RAM BAR* or ATT RAM BAR* goes low for a full CPU cycle. Since the CPU clock can be running at half the speed of the character CCLK (see Clock Circuit, page 4-13), both of these signals are gated with CCLK BAR* •

When CCLK BAR* is low, the CRT controller is at the beginning of a character clock cycle and its address lines are not stable. However, during this period the CPU's address lines are stable and the CPU is either putting data on the data bus or is looking for data from the selected device.

Gating CHAR RAM BAR* and ATT RAM BAR* with CCLK BAR* and then ANDing the resulting signals produces a low on the select inputs (pin 1) to the multiplexers during this period of the CPU cycle. This allows the CPU's address lines to drive the screen RAMs.

The outputs of the two gates used to gate CHAR RAM BAR* and ATT RAM BAR* with CCLK B~R* (74LS32, U43 pins 8-13) are connected to the CE BAR* inputs to U25 and U30. U25 and U30 are 8-bit transceivers used to isolate the CPU data bus from the character data bus and the attribute data bus (CDO-7 and ADO-7).

The direction control input to the transceivers (pin 1) is created by gating CCLK BAR* with R/W from the CPU (U43, pins 1-3). In this manner, the CPU can write data to or read data from the screen RAMs (either character or attribute) without interrupting or interfering with the CRT controller's process of refreshing the $creen.


4-21

Communications (see sheet 5 of the schematic)

There are three serial communications channels. Each has its own dedicated UART and can send and receive data at speeds ranging from 50 to 19,200 bits per second (38,400 for the computer port).

U22 (6551A) is the UART used for communication to the host computer. It interfaces to a 25-pin D-subminiature connector (P3) via TTL to RS-232 level converters (U9 and US, l489's~ U13 and U17, 1488's).

The baud rate is selectable under firmware control and is derived from the clock going in on pin 6 (XTAL 1). For the normal baud rate range of 50 to 19.2K, a 1.8432-MHz clock is used. When the 38.4K baud rate is selected, the firmware selects a slower frequency of 460.8-KHz. It does this by using the HIGH-SPEED control line of the control latch (see CPU System and Control, page 4-15).

U21 is the UART dedicated to printer communications. It interfaces to a 25-pin D-subminiature connector (P4) via the same chips as U22. Its clock input is fixed at 1.8432 MHz, providing a 50 to 19.2K baud range.

U20 is the UART used to communicate with the keyboard. Its clock input is also fixed at 1.8432 MHz and is capable of communicating at 50 to 19.2K baud. Since the keyboard's baud rate is 9600 baud, the firmware programs U20 to always communicate at this speed.

The IRQ BA.:Rt outputs for all three UARTs are tied together in a wired OR configuration. When any of the UARTs generate an Interrupt Request (IRQ), the IRQ BA.R* line goes low, signaling to the CPU that an interrupt has occurred. The CPU then polls the UARTs to determine which one generated the interrupt, and processes the interrupt as required.

*Siqnals referred to as "SIGNAL BARil appear on the schematic as SIGNAL.

4-22

SERVICE INFORMATION

If your ter~inal has technical problems, contact your dealer. International customers may telex 474-5041 TVISYS or call the nearest regional sales office. TeleVideo sales offices are listed below.

REGIONAL SALES OFFICES

Eastern 6900 Jericho Turnpi~e Suite 100LL Syosset, NY 11791 (516) 496-4777

Northwest 1170 Morse Avenue P.O. Box 3568 Sunnyvale, CA 94088-3568 (408) 745-7760

Southcentral 1431 Greenway Drive Suite 110 Irving, TX 75038 (214) 550-1060

Central Europe Saturnusstraat 25 2132 HB Hoofdorp The Netherlands Phone: 011-31-2503-35444 Telex: 74615 (TLVDO NL)

Northern Europe Dorna House, 50 Guildford Rd., West End Surrey GU24 9PW England Phone: 011-44-09905-6464 Telex: 858922

5-1

Northeast 1601 Trapelo Road Reservoir Place Waltham, MA 02154 (617) 890-3282/3284

Southeast 6075 The Corners Parkway Suite 208 Norcross, GA 30092 (404) 447-1231

Midwest 1002 E. Algonquin Road Suite 11~ Schaumburg, IL 60173 (312) 397-5400

Southern Europe 3 rue Le Corbusier Silic 244 94568 Rungis Cedex (Paris) France Phone: 011-33-1-4687-3440 Telex: 205191F

I. Physical

VDT Dimension:

Height: Width Depth :

VDT Net Weight:

Case Foot Print

Case Features:

Tilt:

Swivel:

Cooling:

Connectors:

SPECIFICATIONS

36.195 cm (14.25 in. ) 32.385 cm (12.75 in. ) 31.75 cm (12.5 in. )

22 lbs.

12.5 in. by 11.5 in. max.

-5 to +15 degrees

270 degrees left to right

Convection system

One RS232 communication port One RS422 communication port (option) One RS232 printer port One RJ:L2 mouse port (option) . One RJ12 keyboard port

One AC receptacle-type quick disconnect

CRT:

Diagonal Measure: 35.56 cm (14 in.)

Phosphor: Green

Fluorescence: Green

Face-plate: Filterglass

Screen: Aluminized

Persistence: Medium Short (300us decay time)

7-1

I I • Electrical

AC Supply:

Frequency:

Source Current:

l15V Li.ne:

230V Line:

Phase:

Wattage:

DC Supply:

5V:

12V:

-12V:

Ripple and Spike Noise:

50/60 Hertz +/- 3Hz

1 .0 Amp. (Max.)

.s Amp. (Max.)

Single phase, 3-wire

40 VA Max.

+/- • 1 Volt at 3 Amo.

+/- .2 Volt at 2.0 .1\JTlp.

+/- • S Volt at 200 rn.1\

100rnV peak to peak all DC outouts max. (Resistive Load)

7-2

III. Display 80 132

Horizontal Scanning Frequency: 22.86 Khz 22.86 Khz

Vertical Scanning Frequency: 60 Hertz 60 Hertz

Character Lines: 26 26

Columns Per Line: 80 132

Cell Size (Character Block): Dot Matrix Dot Matrix

width: 9 9

Height: 14 14

High Voltage (At Dark Screen): 13.5 KV +/-500V 13.5 KV +/-500V

High Voltage Regulation (From Dark Screen to Full Bright): 500V +/-250V 500V +/-250V

Picture Brightness at Maximum Contrast: 40 Ft. Lambert 40 Ft. Lambert

Picture Size (Active Display)

Format:

Width:

Height:

Levels of Gray:

7-3

26 lines of 80 26 lines of 80

235 mm 235 mm

185 mm 185 mm

Dark, Half Bright, Full Bright

IV. Keyboard:

Style:

Height:

Home Row DIN std.

Width:

Depth:

Net Weight:

Microcontroller:

Layout:

Operating Life:

V. Environmental:

Operating:

Temperature:

Humidity:

Altitude:

Non-operating:

Temperature:

Humidity:

Altitude:

MTBF:

MTTR:

Vibration:

Shock:

Shipping:

Girth:

Weight:

7-4

Low Profile (DIN std.)

4.699 cm (1.85 in.) Untilted

30 mm Until ted

45.2 cm (17.8 in.)

18.415 cm (7.25 in.)

1.81 kg (3 lbs.)

8049

Included in this section, following specifications

10 Million Keystro~es Min.

o to 45 Degrees C (32 to 113 Degrees F)

10% to 85% non-condensing

3,000 m I (10,000 ft.)

-40 to 60 Degrees C

10% to 85%

5,000 m I (15,000 ft.)

10,000 Hours Min.

30 Minutes

0.3G, 5 to 100 Hz, operational

20G, 11 ms, 18 shocKs

108 inches max.

50 Ibs. max.

VI. CRT Controller Format:

80 x 26 132 x 26

1 . Dot Frequency 19.3396 MHz 31.6840 MHz

2 .. Character Cell

Number of Dots per Character: 9 9

Number of Scan Lines per Character 14 14

3. Character Frequency 2.14884 MHz 3.52044 MHz

4. Screen Format

Number of Characters per Screen 80 132

Number of Rows per Screen 26 26

5. Total Characters per Line 94 154

7-5

VII. Control Board

Type:

Microprocessor:

CRT Controller:

Battery:

Current Loop:

Graphics Board Connector:

Current Load (std.)

Current Load with Options

Printer Port

Main Port

Baud Rate (Main): (Printer):

Parity:

Data Bits:

Handshaking:

System ROM:

System RAM:

Display RAM:

7-6

2-sided, includes power and ground

65C02-P3 (3 MHz)

2674

3V min. Lithium

Option Board (P6)

26-pin

1.3A (5V)~ 220ma (12V)

2.5A (5V) max.

RS232 (P4)

RS232 (P3)

50-38.4K bit/sec. 50-19.2K bit/sec.

No, Odd, Even, Mark, Space

7 or 8

No, X-on/X-off, DTR, Both

16K

2K

4K to 16K max.

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B

A

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D -DAR.K C.OLOR KE'fCJ:a...PS.

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TELEVIDEO® 955 VIDEO DISPLAY TERMINAL MAINTENANCE … · 2018. 3. 18. · This troubleshooting...

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