Technology Roadmap of INTEL’s Processors

Technology Roadmapof

INTEL’s Processors

July 2014

Technology Roadmap Intel Processors 2014 Content for re-use only with TechInsights permission 2

Table of Contents Intel’s product line from Pentium to Ivy BridgeAbove 100 nm node (Gate-First)Sub-100 nm nodes: 90 nm and 65 nm (Gate-First)45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)

Parameters related to “Technology Node”

Contacted Gate Pitch6T SRAM Cell SizeMetal 1 Pitch

FutureWhat to expect NEXT?

Technology Roadmap Intel Processors 2014 Content for re-use only with TechInsights permission

Above 100 nm, Gate-First: Package (top & bottom) 0.35 µm

Intel Pentium Microprocessor (200 MHz)

0.18 µmIntel III Microprocessor

“Coppermine” (450 MHz)

0.13 µmIntel III Microprocessor“Tualatin” (1.26 GHz)

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10.8 mm x 12.6 mm = 136.1 mm2

0.35 µmIntel Pentium

Microprocessor (200 MHz)

10.3 mm x 12.3 mm = 126.7 mm2




7.1 mm x 11.1 mm = 79 mm2

Above 100 nm, Gate-First: Die and Die markings

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0.35 µmIntel Pentium

Microprocessor (200 MHz)




Above 100 nm, Gate-First: SRAM at gate level

All the SRAMS: P+ diffusions of the pull-down transistors have an “H” shape and each one is shared by two SRAM cells

Wordline and pull-down are 90˚ at each other and this consumes lot of space

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The devices before 0.35 µm are not taken because previous two generations (0.6 µm and 0.8 µm) used BiCMOS process

The 0.25 µm node has been omitted to avoid clutter

Above 100 nm: Critical Parameters

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Parameters 0.35 µm Node 0.18 µm Node 0.13 µm Node

Die size 136 mm2 126.7 mm2 79 mm2

NMOS gate length 335 nm 120 nm 70 nmPMOS gate length 330 nm 130 nm 70 nm

Minimum metal 1 pitch 950 nm 750 nm 360 nmGate oxide thickness 5 nm 2.5 nm 1.9 nmContacted gate pitch 1480 nm 760 nm 510 nm

Silicide TiSi CoSi CoSiMetallization levels 4 (A1) 6 (A1) 6 (Cu)

SRAM cell size 18.1 µm2 6 µm2 3.25 µm2


In four generations (0.35 µm, 0.25 µm, 0.18 µm, 0.13 µm):

The die area shrunk from 136 to 79 mm2

The gate length reduced from 335 nm to 70 nm

The metal 1 pitch scaled down from 950 nm to 360 nm

The SRAM cell size decreased from 18.1 µm2 to 3.25 µm2

Not all parameters scaled in the same proportion

Intel moved towards sub 100 nm nodes with process-integration experience in Cu-interconnects and low-k materials

By 130 nm node all the processors had a clock frequency in the range of 3 GHz

Above 100 nm: Summary

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90 nmIntel Pentium IV, “Prescott”

(3 GHz)

Sub 100 nm, Gate-First: Package (Top & Bottom)

65 nmIntel Dual Core, “Xeon”

(3 GHz)

90 nm and 65 nm are two generations below 100 nm nodes, which used conventional gate structure with poly for gate electrode and oxide for gate dielectric

65 nm node was essentially a shrink of 90 nm

The most innovative part in 65 nm node was the introduction of dual core architecture

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10.8 mm x 10.34 mm = 112 mm2

Sub 100 nm, Gate-First: Die and Die markings

13.4 mm x 10.4 mm = 142 mm2


(3 GHz)


(3 GHz)

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Sub 100 nm, Gate-First: SRAM at gate level

The SRAM cell at diffusion changed from H_O structure to continuous regions of P-well for NMOS transistors and I shaped regions of N-well for PMOS transistors

Intel 65 nm node is 2nd generation of strain silicon technology

65 nm node adopted the same uniaxial strained approach as 90 nm node

Epitaxial SiGe film was employed for PMOS source-drains in 65 nm and 90 nm node

Up to 65 nm node, single patterning was only used


(3 GHz)


(3 GHz)

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45 nmIntel Core 2TM Extreme, “Penryn”

(3 GHz)

Sub 100 nm, Gate-Last: Package (Top & Bottom)

32 nm Intel Dual Core, “Clarkdale/Westmere”

(3 GHz)

22 nmIntel Quadcore, “Ivy Bridge”

(3.3 GHz)

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19.6 mm x 8.0 mm = 112 mm29.2 mm x 8.2 mm =

75.4 mm2

Sub 100 nm, Gate-Last: Die and Die Markings

12.2 mm x 8.5 mm = 104 mm2


(3 GHz)


(3 GHz)


(3.3 GHz)

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Sub 100 nm, Gate-Last: SRAM at gate level

The 6T SRAM cell has been the vehicle to define technology nodes

Cross couple PMOS and NMOS metal gates are connected at the side of the metal gate.

45 nm node uses double patterning with 193 nm dry lithography

32 nm node uses double patterning with 193 nm immersion lithography

22 nm node introduces fins and uses double patterning with 193 nm immersion lithography


(3 GHz)


(3 GHz)


(3.3 GHz)

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Sub 100 nm, Gate-Last: Summary

Intel’s 45 nm process is the first to incorporate high-k metal gate (HKMG) technology. Their innovative process protects the high-k gate dielectric from polysilicon etch by depositing a TiN top interface layer (TIL) before polysilicon deposition and patterning.

PMOS channel stress is enhanced by removing the polysilicon dummy gates which is an enabling factor of the replacement metal gate process Intel used for the first time double patterning based on 193 nm dry lithography for critical layers and at the transistor gate level. Intel’s 32 nm was essentially a shrink of 45 nm node with the exception that immersion lithography was used.

As of today, 2014, Intel is the only manufacturer to use a FinFET for its transistors. Intel 22 nm replaced the traditional 2-D planar MOS transistor with a gate that is wrapped around a thin three-dimensional silicon fin that rises up vertically from the silicon substrate . A thin high-k dielectric separates the silicon fin from the metal gate on each of the three sides of the fin

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Sub 100 nm, Gate-Last: Graphical Summary

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Sub 100 nm: Critical Dimensions (Logic)

90 nm and 45 nm have the same gate-length65 nm and 32 nm have the same gate-length

Gate length is not an accurate parameter for defining technology node for devices below 100 nm node

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Node 90 nm 65 nm 45 nm 32 nm 22 nm

Lithography 248 nm dry 193 nm dry 193 nm dry 193 nm immersion + double patterning

193 nm immersion + double patterning

Process

SiGe is used to strain a silicon channel;

tensile nitride layer for NMOS channel; Ni-Si replaces Co-Si

SiGe for PMOS; Poly gates; W contact, M1

in Cu

SiGe for PMOS; Metal gates with

High-K; W contact; M1 in Cu

SiGe_PMOS; eSi_NMOS; Metal gates with high-K, M0 level in Cu; W contact; M1 in Cu

Tri-gate transistor; SiG3_PMOS;

eSi_NMOS; Metal gates, M0 level in W; W contact; M1 in Cu

Minimum Contacted Gate Pitch (nm) 310 220 160 113 90

Minimum Gate Length (nm) 45 36 45 34 25

Minimum Metal 1 Pitch (nm) 220 210 150 113 90


Sub 100 nm: Critical Dimensions (SRAM)

The 32 nm node introduced the metal 0 level and changed the wiring position of bitlines (BL), Wordlines (WL), Vss and Vdd lines and improved slightly the width/length (W/L) ratio of transistors

The SRAM in 22 nm node kept the same wiring configuration for BL, WL, Vdd and Vss, as in 32 nm node but by introducing Tri-Gate (FinFET) structure improved W/L ratio

Generally, the widths of pull down transistors are greater than the widths of access transistors. The current ratio of I PD /I AC reflecting geometric device dimension is known as beta ratio. A higher beta ratio reflects higher cell stability

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For advanced nodes “Gate-Length” is not a reliable parameter for defining technology node

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The “Contacted Gate Pitch” takes in account the gate length and the minimum litho-features, thus reflects the actual technology node

“Contacted Gate Pitch” decreases by 0.7 every two years, following Intel’s “Tick Tock” scheme

Every alternate year Intel develops a new process technology and the following year a new micro-architecture, (Tick / Tock scheme)

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The “square root of 6T-SRAM cell area” is linear with technology node and is an accurate method to determine the technology node

Intel 22 nm has 0.092 µm2 SRAM cell for high density applications but our analysis did not locate these cells, only 0.108 µm2 SRAM cell for low voltage applications was found in reverse engineering.


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The “Metal 1 Pitch” is also indicative of the technology node but not very accurate

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What is coming NEXT?

Intel has developed both CPU and SoC processes for its 45 nm, 32 nm and 22 nm technology nodes

SoC products usually incorporate a variety of devices that are often not seen in regular CPU products

Intel will use the 22 nm technology node platform and diversify for different products

Intel is not pursuing only high performance, but developing process and architectures for wider range of products varying from server-market to mobile market

This wide variety of products requires different design at one particular technology node

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What is coming NEXT?

Different chips with different designs are available at 22 nm technology, for example:

Ivy Bridge ( CPU); Haswell (SoC); Bay Trail (for tablets, Atom Z300 series)

Intel 22 nmIvy Bridge

Bay Trail 22 nm ATOM Z300

Intel 22 nmHaswell

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What is coming NEXT?Generation of High-K and Metal Gates with “Gate-Last” process

Most likely bulk FinFET will be used for 14 nm node

EUV will probably be used for sub 10 nm nodes

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Technology Roadmap of INTEL’s Processors

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