Technology Mapping

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Technology MappingTechnology Mapping

Example:Example:tt1 = a + bc;

t2 = d + e;

t3 = ab + d;

t4 = t1t2 + fg;

t5 = t4h + t2t3;

F = t5’;

This shows an unoptimized set of logic equations This shows an unoptimized set of logic equations consisting of consisting of 1616 literals literals

d+ea+bc

t5’

t1t2 + fg

F

ab+d

t4h + t2t3

2

Optimized EquationsOptimized Equations

Using technology independent optimization, Using technology independent optimization, these equations are optimized using only these equations are optimized using only 1414 literals:literals:t1 = d + e;

t2 = b + h;

t3 = at2 + c;

t4 = t1t3 + fgh;

F = t4’;

d+e b+h

t4’

at2 +c

t1t3 + fgh

F

d+ea+bc

t5’

t1t2 + fg

F

ab+d

t4h + t2t3

3

Optimized EquationsOptimized Equations

Implement this network using a set of gates Implement this network using a set of gates which form a which form a librarylibrary. Each gate has a cost (i.e. its area, delay, etc.)

4

Technology MappingTechnology MappingTwo approaches:Two approaches:

1.1. Rule-Based [LSS]Rule-Based [LSS]

2.2. Algoritmic [DAGON, MISII]Algoritmic [DAGON, MISII]1.1. Represent each function of a network using a set of Represent each function of a network using a set of base base

functionsfunctions. This representation is called the subject graph.• Typically the base is 2-input NANDs and inverters [MISII]. • The set should be functionally complete.

2.2. Each gate of the library is likewise represented using the Each gate of the library is likewise represented using the base set. This generates base set. This generates pattern graphspattern graphs

• Represent each gate in Represent each gate in all possibleall possible ways ways

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Subject graphSubject graph

d+e b+h

t4’

at2 +c

t1t3 + fgh

b’ h’

a

d’ e’

hg

f

c

Subjectgraph of2-input NANDs andinvertors

FF

6

Algorithmic ApproachAlgorithmic ApproachA A covercover is a collection of pattern graphs such that is a collection of pattern graphs such that

1.1. every node of the subject graph is every node of the subject graph is containedcontained in one (or in one (or more) pattern graphs more) pattern graphs

2.2. each each inputinput required by a pattern graph is actually an required by a pattern graph is actually an outputoutput of some other graph of some other graph (i.e. the inputs of one gate (i.e. the inputs of one gate must exists as outputs of other gates.)must exists as outputs of other gates.)

For minimum area, the cost of the cover is the For minimum area, the cost of the cover is the sum of sum of the areasthe areas of the gates in the cover. of the gates in the cover.

Technology mapping problem:Technology mapping problem: Find a Find a minimum cost minimum cost coveringcovering of the subject graph by choosing from the of the subject graph by choosing from the collection of pattern graphs for all the gates in the collection of pattern graphs for all the gates in the librarylibrary..

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Subject GraphSubject Graph

t1 = d + e;

t2 = b + h;

t3 = at2 + c;

t4 = t1t3 + fgh;

F = t4’;

F

f

g

d

e

h

b

a

c

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Pattern Graphs for the Pattern Graphs for the IWLS LibraryIWLS Library

inv(1) nand3 (3)

oai22 (4)

nor(2)nor3 (3)

xor (5)

aoi21 (3)

nand2(2)

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Subject graph coveringSubject graph covering

t1 = d + e;

t2 = b + h;

t3 = at2 + c;

t4 = t1t3 + fgh;

F = t4’;

F

f

g

d

e

h

b

a

cTotal cost = 23

10

Better CoveringBetter Covering

t1 = d + e;

t2 = b + h;

t3 = at2 + c;

t4 = t1t3 + fgh;

F = t4’;

F

f

g

d

e

h

b

a

c

aoi22(4)

and2(3)

or2(3)

or2(3)

Total area = 19 nand2(2)

nand2(2)

inv(1)

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Alternate CoveringAlternate Covering

t1 = d + e;

t2 = b + h;

t3 = at2 + c;

t4 = t1t3 + fgh;

F = t4’;

F

f

g

d

e

h

b

a

c

nand3(3)nand3(3)

oai21(3)oai21(3)

oai21 (3)oai21 (3)

Total area = 15

and2(3)

inv(1)

nand2(2)

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Technology mapping using Technology mapping using DAG coveringDAG covering

InputInput1.1. Technology independent, optimized logic Technology independent, optimized logic networknetwork

2.2. Description of the gates in the Description of the gates in the librarylibrary with their cost with their cost

OutputOutput– Netlist of gatesNetlist of gates (from library) which minimizes total cost (from library) which minimizes total cost

General ApproachGeneral Approach– Construct a subject DAG for the networkConstruct a subject DAG for the network– Represent each gate in the target library by pattern Represent each gate in the target library by pattern

DAG’sDAG’s– Find an optimal-cost covering of subject DAG using the Find an optimal-cost covering of subject DAG using the

collection of pattern DAG’scollection of pattern DAG’s

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Technology mapping using Technology mapping using DAG coveringDAG covering

Complexity of DAG covering:Complexity of DAG covering:

– NP-hardNP-hard

– Remains NP-hard even when the nodes have Remains NP-hard even when the nodes have

out degree out degree 2 2

– If subject DAG and pattern DAG’s are trees, an If subject DAG and pattern DAG’s are trees, an

efficient algorithm existsefficient algorithm exists

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DAG covering as a binate DAG covering as a binate covering problemcovering problem

• Compute Compute allall possible matches { possible matches {mmk k } } (ellipses in fig.)(ellipses in fig.) for each for each nodenode

• Using a variable Using a variable mmii for each match of a pattern graph in the for each match of a pattern graph in the subject graph, subject graph, ((mmii =1 if match is chosen) =1 if match is chosen)

• Write a Write a clauseclause for each node of the subject graph indicating for each node of the subject graph indicating which matches cover this node. Each node has to be covered.which matches cover this node. Each node has to be covered.– e.g., if a subject node is covered by matches {e.g., if a subject node is covered by matches {mm22, mm55, mm10 10 }, then the

clause would be (mm22 + mm55 + mm1010).

• Repeat for each subject node and take the product over all subject nodes. (CNF) m1 m2 . . . mk

n1 n2 ...nl

nodes

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Any satisfying assignment guarantees that all subject nodes are covered, but does not guarantee that other matchs chosen create outputs needed as inputs needed for a given match.

Rectify this by adding additional clauses.

not an outputof a chosen match

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• Let match mi have subject nodes si1,…,sin as n inputs. If mi is chosen, one of the matches that realizes sij must also be chosen for each input j ( j not a primary input).

• Let Sij be the disjunctive expression in the variables mk giving the possible matches which realize sij as an output node. Selecting match mi implies satisfying each of the expressions Sij for j = 1 … n.This can be written(mi (Si1 … Sin ) ) (mi + (Si1 … Sin ) ) ((mi + Si1) … (mi + Sin ) )

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• Also, one of the matches for each primary output of the circuit must be selected.

• An assignment of values to variables mi that satisfies the above covering expression is a legal graph cover

• For area optimization, each match mi has a cost ci that is the area of the gate the match represents.

• The goal is a satisfying assignment with the least total cost.– Find a least-cost prime:

• if a variable mi = 0 its cost is 0, else its cost in ci

• mi = 0 means that match i is not chosen

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Binate CoveringBinate CoveringThis problem is This problem is more generalmore general than unate-covering for than unate-covering for

two-level minimization becausetwo-level minimization because– variables are present in the covering expression in both variables are present in the covering expression in both

their their truetrue and and complementedcomplemented forms. forms.

The covering expression is a binate logic function, The covering expression is a binate logic function, and the problem is referred to as the and the problem is referred to as the binate-binate-covering problem.covering problem.

This problem has appeared before:This problem has appeared before:– As As state minimizationstate minimization of incompletely specified finite- of incompletely specified finite-

state machines [Grasselli-65]state machines [Grasselli-65]– As a problem in the design of optimal As a problem in the design of optimal three levelthree level NAND- NAND-

gate networks [Gimpel-67]gate networks [Gimpel-67]– In the optimal In the optimal phase assignmentphase assignment problem [Rudell-86] problem [Rudell-86]

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Binate Covering: ExampleBinate Covering: Example

Gate Cost Inputs Produces Covers m1 inv 1 b g1 g1 m2 inv 1 a g2 g2 m3 nand2 2 g1, g2 g3 g3 m4 nand2 2 a, b g4 g4 m5 nand2 2 g3, g4 g5 g5 m6 inv 1 g4 g6 g6 m7 nand2 2 g6, c g7 g7 m8 inv 1 g7 g8 g8 m9 nand2 2 g8, d g9 g9 m10 nand3 3 g6, c, d g9 g7, g8, g9 m11 nand3 3 a, b, c g7 g4, g6, g7 m12 xnor2 5 a, b g5 g1, g2, g3, g4, g5 m13 nand4 4 a, b, c, d g9 g4, g6, g7, g8, g9 m14 oai21 3 a, b, g4 g5 g1, g2, g3, g5

1

2

3

4

5

6

7 8

9

ab

cd

o1

o2

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Generate constraints that each node Generate constraints that each node ggii be covered by be covered by some match.some match.((mm11 + + mm1212 ++ m m1414) ) ((mm22 + + mm1212 ++ m m1414) ) ((mm33 + + mm1212 ++ m m1414))((mm44 + + mm1111 ++ m m1212 ++ m m1313) ) ((mm55 + + mm1212 ++ m m1313))((mm66 + + mm1111 ++ m m1313) ) ((mm77 + + mm1010 ++ m m1111 ++ m m1313))((mm88 + + mm1010 ++ m m1313) ) ((mm99 + + mm1010 ++ m m1313))

To ensure that a cover leads to a valid circuit, extra To ensure that a cover leads to a valid circuit, extra clauses are generated. clauses are generated. – For example, selecting For example, selecting mm33 requires that requires that

• a match be chosen which produces a match be chosen which produces gg22 as an output, and as an output, and

• a match be chosen which produces a match be chosen which produces gg11 as an output. as an output.

The only match which produces The only match which produces gg11 is is mm11, and the only match , and the only match which produces which produces gg22 is is mm22

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The primary output nodes The primary output nodes gg55 and and gg99 must be realized must be realized as an output of some match. as an output of some match.

– The matches which realize The matches which realize gg55 as an output are as an output are mm55, m, m1212,, mm1414;;

– The matches which realize The matches which realize gg99 as an output are as an output are mm99, m, m1010, m, m1313

• Note:Note: – A match which requires a primary input as an input is A match which requires a primary input as an input is

satisfied trivially. satisfied trivially.

– Matches Matches mm11,m,m22,m,m44,m,m1111,m,m1212,m,m1313 are driven only by are driven only by

primary inputs and do not require additional clausesprimary inputs and do not require additional clauses

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• Finally, we getFinally, we get((mm33 + + mm11) ) ((mm33 + + mm22) ) ((mm33 ++mm55) ) ((mm55 + + mm44) ) ((mm66 + + mm44))((mm77 + + mm66) ) ((mm88 + + mm77) ) ((mm88 ++mm99) ) ((mm1010 + + mm66))

((mm1414 + + mm44) ) ((mm55 + + mm1212 ++ m m1414) ) ((mm99 + + mm1010 ++ m m1313))

• The covering expression has 58 implicantsThe covering expression has 58 implicants• The least cost prime implicant isThe least cost prime implicant is

mm33 mm55 mm66 mm77 mm88 mm99 mm1010 mm1212 m m1313 mm1414

• This uses two gates for a cost of This uses two gates for a cost of ninenine gate units. This gate units. This corresponds to a cover which selects matches corresponds to a cover which selects matches mm1212

(xor2)(xor2) and and m m13 13 (nand4).

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1

2

3

4

5

6

7 8

9

ab

cd

o1

o2

Gate Cost Inputs Produces Covers m1 inv 1 b g1 g1 m2 inv 1 a g2 g2 m3 nand2 2 g1, g2 g3 g3 m4 nand2 2 a, b g4 g4 m5 nand2 2 g3, g4 g5 g5 m6 inv 1 g4 g6 g6 m7 nand2 2 g6, c g7 g7 m8 inv 1 g7 g8 g8 m9 nand2 2 g8, d g9 g9 m10 nand3 3 g6, c, d g9 g7, g8, g9 m11 nand3 3 a, b, c g7 g4, g6, g7 m12 xnor2 5 a, b g5 g1, g2, g3, g4, g5 m13 nand4 4 a, b, c, d g9 g4, g6, g7, g8, g9 m14 oai21 3 a, b, g4 g5 g1, g2, g3, g5

mm33 mm55 mm66 mm77 mm88 mm99 mm1010 mm1212 m m1313 mm1414

Note that the node g4

is covered by both matches

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Complexity of DAG Complexity of DAG coveringcovering

More general than unate coveringMore general than unate covering– Finding least cost prime of a Finding least cost prime of a binatebinate function. function.

• Even finding a feasible solution is NP-complete (SAT). Even finding a feasible solution is NP-complete (SAT). • For unate covering, finding a feasible solution is easy.For unate covering, finding a feasible solution is easy.

– DAG-covering: DAG-covering: covering + implicationcovering + implication constraints constraints

Given a Given a subject graphsubject graph, the binate covering provides the , the binate covering provides the exactexact solution to the technology-mapping problem. solution to the technology-mapping problem.– HoweverHowever, better results may be obtained with a different initial , better results may be obtained with a different initial

decomposition into 2-input NANDS and invertersdecomposition into 2-input NANDS and inverters

Methods to solve the binate covering formulation:Methods to solve the binate covering formulation:– Branch and bound [Thelen]Branch and bound [Thelen]– BDD-based [Lin and Somenzi]BDD-based [Lin and Somenzi]

Even for moderate-size networks, these are expensive.Even for moderate-size networks, these are expensive.

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Optimal Tree Covering by TreesOptimal Tree Covering by Trees

• If the subject DAG and primitive DAG’s are If the subject DAG and primitive DAG’s are treestrees, , then an efficient algorithm to find the best cover then an efficient algorithm to find the best cover existsexists

• Based on Based on dynamic programmingdynamic programming• First proposed for optimal code generation in a First proposed for optimal code generation in a

compilercompiler

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Optimal Tree Covering by TreesOptimal Tree Covering by TreesPartitionPartition subject graph into subject graph into forestforest of trees of trees

CoverCover each tree optimally using dynamic programming each tree optimally using dynamic programming

Given:Given:– Subject trees (networks to be mapped)Subject trees (networks to be mapped)– Forest of patterns (gate library)Forest of patterns (gate library)

1.1. Consider a node Consider a node NN of a subject tree of a subject tree

2.2. Recursive Assumption:Recursive Assumption: for all children of for all children of N,N, a a bestbest cost cost match match (which implements the node)(which implements the node) is known is known

3.3. Cost of a Cost of a leafleaf of the tree is 0. of the tree is 0.

4.4. Compute cost of each pattern tree which matches at Compute cost of each pattern tree which matches at NN,,Cost = SUM of best costs of implementing each Cost = SUM of best costs of implementing each inputinput of pattern of pattern

plusplus the cost of the pattern the cost of the pattern

5.5. Choose least cost matching pattern for implementing Choose least cost matching pattern for implementing NN

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Optimum Area AlgorithmOptimum Area AlgorithmOptimal_area_coverOptimal_area_cover(node) {(node) {

/* find optimal cover for all nodes below “node” *//* find optimal cover for all nodes below “node” */foreach input of node {foreach input of node { optimal_area_cover(input); optimal_area_cover(input); /* thus satisfies recursive assumption *//* thus satisfies recursive assumption */}}/* Using these, find the best cover at “node” *//* Using these, find the best cover at “node” */nodenodearea = INFINITY;area = INFINITY;nodenodematch = 0;match = 0;foreach match at node {foreach match at node {

area = matcharea = matcharea;area;foreach pin of match {foreach pin of match {

area = area + pinarea = area + pinarea;area;}}if (area < nodeif (area < nodearea) {area) {

nodenodearea = area;area = area;nodenodematch = match;match = match;

}}}}}}

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Tree Covering in ActionTree Covering in Action

nand2(3)

inv(2)

nand2(8)nand2(13)

inv(2)

nand2(3)inv(5)

and2(4)

inv(6)and2(8)

nand2(7)nand3(4)

nand2(21)nand3(22)nand4(18)

inv(20)aoi21(18)

nand2(21)nand3(23)nand4(22)

nand2 = 3inv = 2nand3 = 4nand4 = 5and2 = 4aio21 = 4oai21 = 4

library

nand4nand4

aoi21aoi21

nand4nand4

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Complexity of Tree Complexity of Tree CoveringCovering

• Complexity is controlled by finding Complexity is controlled by finding allall sub- sub-trees of the subject graph which are trees of the subject graph which are isomorphic to a pattern tree.isomorphic to a pattern tree.

• LinearLinear complexity in both size of subject complexity in both size of subject tree and size of collection of pattern treestree and size of collection of pattern trees

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Partitioning the subject DAG into treesPartitioning the subject DAG into trees

Trivial partition:Trivial partition: break the graph at all multiple- break the graph at all multiple-fanout pointsfanout points– leads to leads to nono “duplication” or “overlap” of patterns “duplication” or “overlap” of patterns– drawback - sometimes results in many of drawback - sometimes results in many of smallsmall trees trees

Leads to Leads to 33 trees trees

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Partitioning the subject DAG into treesPartitioning the subject DAG into treesSingle-cone partition:Single-cone partition:

– from a single output, form a large tree back to the from a single output, form a large tree back to the primary inputsprimary inputs; ; – map successive outputs until they hit map successive outputs until they hit match outputmatch output formed from formed from

mapping previous primary outputs.mapping previous primary outputs.• Duplicates some logic (where trees overlap)Duplicates some logic (where trees overlap)• Produces much larger trees, potentially even better area resultsProduces much larger trees, potentially even better area results

outputoutput

outputoutput

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Logic Decomposition andLogic Decomposition andTechnology Mapping Technology Mapping

Lehman-Watanabe MethodLehman-Watanabe Method

Common Approach:Common Approach:• Phase 1:Phase 1: Technology independent Technology independent

optimizationoptimization– commit to a particular Boolan networkcommit to a particular Boolan network– algebraic decomposition usedalgebraic decomposition used

• Phase 2:Phase 2: AND2/INV decomposition AND2/INV decomposition– commit to a particular decomposition of a commit to a particular decomposition of a

general Boolean network using general Boolean network using 2-input ANDs 2-input ANDs and invertersand inverters

• Phase 3:Phase 3: Technology mapping Technology mapping (tree-(tree-mapping)mapping)

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Logic Decomposition and Technology Logic Decomposition and Technology Mapping - Lehman-Watanabe MethodMapping - Lehman-Watanabe Method

Drawbacks:Drawbacks:Procedures in each phase are disconnected:– Phase 1 and Phase 2 make critical decisions

without knowing much about constraints and library

– Phase 3 knows about constraints and library, but solution space is restricted by decisions made earlier

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Lehman-Watanabe Technology MappingLehman-Watanabe Technology Mapping

Incorporate technology independent procedures (Phase 1 and Phase 2) into technology mapping

Key Idea:– Efficiently encode a set of AND2/INV

decompositions into a single structure called a mapping graph

– Apply a modified tree-based technology mapper while dynamically performing algebraic logic decomposition on the mapping graph

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OutlineOutline1.1. Mapping GraphMapping Graph

– Encodes a set of AND2/INV decompositionsEncodes a set of AND2/INV decompositions

2.2. Tree-mapping on a mapping graph: Tree-mapping on a mapping graph: graph-graph-mappingmapping

3. -mapping:– without dynamic logic decomposition– solution space: Phase 3 + Phase 2

4. -mapping:– withwith dynamic logic decomposition dynamic logic decomposition– solution space: Phase 3 + Phase 2 + Algebraic solution space: Phase 3 + Phase 2 + Algebraic

decomposition (Phase 1)decomposition (Phase 1)

5.5. Experimental resultsExperimental results

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End of lecture 18End of lecture 18

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A set of AND2/INV DecompositionsA set of AND2/INV Decompositions

f = abcf = abc can be represented in various ways can be represented in various ways

f

ab

c

ab

c

a

bc

f

f

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A set of AND2/INV DecompositionsA set of AND2/INV Decompositions

Combine them using a Combine them using a choice nodechoice nodeab

c

ab

c

a

bc

39

Encoding AND2/INV DecompositionsEncoding AND2/INV Decompositions

These decompositions can be represented These decompositions can be represented more compactly as:more compactly as:

This representation encodes even more This representation encodes even more decompositions, e.g.decompositions, e.g.

abcabc

f

bc

a

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Mapping GraphMapping Graph

A Boolean network containing 4 A Boolean network containing 4 modifications:modifications:– Choice node:Choice node: choices on different choices on different

decompositionsdecompositions– Cyclic:Cyclic: functions written in terms of each other, e.g. inverter chain with an arbitrary length functions written in terms of each other, e.g. inverter chain with an arbitrary length– Reduced:Reduced: No two choice nodes with same function. No two AND2s with same fanin. No two choice nodes with same function. No two AND2s with same fanin. (like BDD (like BDD

node sharing)node sharing)– Ugates:Ugates: just for efficient implementation - do not explicitly represent choice nodes and inverters just for efficient implementation - do not explicitly represent choice nodes and inverters

For For benchmark (MCNC’91), there are benchmark (MCNC’91), there are 2.2x102.2x109393 AND2/INV decompositions. All are AND2/INV decompositions. All are encoded with only encoded with only 400400 ugates containing ugates containing 599599 AND2s in total. AND2s in total.

bc

a

bc

a

ab

bc

ac

abc

ugatesugates

41

Tree-mapping on a Mapping GraphTree-mapping on a Mapping Graph

Graph-Mapping on Graph-Mapping on TreesTrees****:: Apply dynamic program-Apply dynamic program-

ming from primary inputs:ming from primary inputs:– find matches at each AND2 find matches at each AND2

and INV, and and INV, and – retain the cost of a best retain the cost of a best

cover at each nodecover at each node1.1. a match may a match may containcontain choice nodes choice nodes2.2. the cost at a choice node is the the cost at a choice node is the minimumminimum of fanin costs of fanin costs3.3. fixed-point iteration on each fixed-point iteration on each cyclecycle, until costs of all the , until costs of all the

nodes in the cycle become stablenodes in the cycle become stable

Run-time is typically Run-time is typically linearlinear in the size of the mapping in the size of the mapping graphgraph

bc

a

b

ca

abc

AND3

** mapping graph may not be a tree, but any multiple fanout node just represents several copies of same function.

42

Example: Tree-mappingExample: Tree-mapping

Delay:Delay: best choice if c is later than a and best choice if c is later than a and b.b.

subject graphsubject graph library pattern library pattern graphgraph

43

Graph-Mapping: TheoryGraph-Mapping: Theory

Graph-mapping( Graph-mapping( ) = ) = minmin (tree-mapping( (tree-mapping())))

:: mapping graph mapping graph

:: AND2/INV decomposition encoded in AND2/INV decomposition encoded in

• Graph-mapping finds an optimal Graph-mapping finds an optimal treetree implementation for each primary output implementation for each primary output overover all AND2/INV decompositions encoded in all AND2/INV decompositions encoded in

• Graph-mapping is Graph-mapping is as powerfulas powerful as applying as applying tree-mapping tree-mapping exhaustivelyexhaustively, but is typically , but is typically exponentially fasterexponentially faster

44

-Mapping-MappingGiven a Boolean network Given a Boolean network , , • Generate a mapping graph Generate a mapping graph : : • For each node of For each node of ,,

1.1. encode all AND2 decompositions for each encode all AND2 decompositions for each productproduct term termEx:Ex: abc abc 3 AND2 decompositions: 3 AND2 decompositions: a(bc), c(ab), b(ca)a(bc), c(ab), b(ca)

2.2. encode all AND2/INV decompositions for the encode all AND2/INV decompositions for the sumsum term termEx:Ex: p+q+r p+q+r 3 AND2/INV decompositions: 3 AND2/INV decompositions:

p+(q+r), r+(p+q), q+(r+p).p+(q+r), r+(p+q), q+(r+p).

3.3. Apply graph-mapping on Apply graph-mapping on

In practice, In practice, is pre-processed so is pre-processed so 1.1. each node has at most each node has at most 10 product terms10 product terms and and

2.2. each term has at most each term has at most 10 literals10 literals

45

-Mapping: Theory-Mapping: TheoryFor the mapping graph For the mapping graph generated for a Boolean generated for a Boolean

network network , let , let – LL be the set of AND2/INV decompositions encoded in be the set of AND2/INV decompositions encoded in be the closure of the set of AND2/INV decompositions be the closure of the set of AND2/INV decompositions

of of under the associative and inverter transformations: under the associative and inverter transformations:ab

c

ac

b

AssociativeAssociativetransformtransform InverterInverter

transformtransform

Theorem:Theorem: = L= L

46

Dynamic Logic Dynamic Logic DecompositionDecomposition

During graph-mapping, During graph-mapping, dynamicallydynamically modify modify the mapping graph: the mapping graph:

find find D-patternsD-patterns and and addadd F-patternsF-patterns

D-pattern: acab

a

b ab

cc

F-pattern: )( cba

47

Dynamic Logic Dynamic Logic DecompositionDecomposition

Note:Note: Adding F-patterns may introduce new D-patterns which may imply Adding F-patterns may introduce new D-patterns which may imply new F-patterns.new F-patterns.

ab

c

ab

c

b

c

ac

a

abc

b

48

-Mapping-Mapping

Given a boolean network Given a boolean network , generate a mapping graph , generate a mapping graph

Iteratively apply graph mapping on Iteratively apply graph mapping on , while performing , while performing dynamicdynamic logic decomposition until nothing changes in logic decomposition until nothing changes in – Before finding matches at an AND2 in Before finding matches at an AND2 in , check if D-pattern , check if D-pattern

matches at the AND2. If so, add the corresponding F-patternmatches at the AND2. If so, add the corresponding F-pattern

– In practice,terminate the procedure when a feasible solution is In practice,terminate the procedure when a feasible solution is foundfound

b

ca c

a

abc

b

49

-Mapping-Mapping

For the mapping graph For the mapping graph generated for a generated for a Boolean network Boolean network , let , let – DD be the set of AND2/INV decompositions be the set of AND2/INV decompositions

encoded in the encoded in the resultingresulting mapping graph. mapping graph.

be the closure of be the closure of under the distributive under the distributive

transformation:transformation:

Theorem:Theorem: = D = D

aab

b

cc

50

-Mapping-Mapping

Theorem:Theorem: If If1.1. ’ ’ is an arbitrary Boolean network obtained is an arbitrary Boolean network obtained

from from by by algebraicalgebraic decomposition. decomposition.

2.2. is an arbitrary is an arbitrary AND2/INVAND2/INV decomposition of decomposition of ’’

then then DD

The resulting mapping graph encodes The resulting mapping graph encodes allall the the AND2/INV decompositions of AND2/INV decompositions of allall algebraic algebraic decompositions of decompositions of ..

51

Solution Space captured by ProceduresSolution Space captured by Procedures

-mapping captures all AND2/INV decompositions of -mapping captures all AND2/INV decompositions of : : Phase 2 (subject graph generation) is subsumedPhase 2 (subject graph generation) is subsumed

-mapping captures all algebraic decompositions: -mapping captures all algebraic decompositions: Phase 2 and Phase 1 are subsumedPhase 2 and Phase 1 are subsumed..

Phase 1:arbitrary algebraic

decomposition

Phase 2:arbitrary AND2/INV

decomposition

Mapping graphassociative transform

Dynamic decompositiondistributive transform

'

D -mapping

L -mapping

‘’‘’

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ExperimentsExperimentsExamples:Examples: MCNC’91 combinational benchmarksMCNC’91 combinational benchmarks

Library:Library: From DEC ALPHA microprocessorFrom DEC ALPHA microprocessor

Cost:Cost: Delay (fastest possible implementation)Delay (fastest possible implementation)

1.1. Apply Apply fourfour different technology independent SIS different technology independent SIS scripts on the initial Boolean network. scripts on the initial Boolean network.

2.2. Encode each of the four optimized boolean network Encode each of the four optimized boolean network into a into a singlesingle mapping graph mapping graph . (. (NoteNote: here we encode : here we encode even more decompositions into )even more decompositions into )

3.3. Apply graph mapping on Apply graph mapping on ( (-mapping).-mapping).

4.4. Collapse the most Collapse the most timing criticaltiming critical region of a mapped region of a mapped network, and encode it in network, and encode it in ..

5.5. Apply graph-mapping with dynamic logic Apply graph-mapping with dynamic logic decomposition decomposition ((-mapping)-mapping)

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Experimental resultsExperimental results

• Delay unit:Delay unit: minimum input-output pin delay over minimum input-output pin delay over all library gatesall library gates

• Area unit:Area unit: minimum gate-area over all library gates minimum gate-area over all library gates• SynFul’s CPU time: ranged from 10 to 300 seconds SynFul’s CPU time: ranged from 10 to 300 seconds

on VAXstation 6000on VAXstation 6000

SynFul SIS-1.2 -mapping -mapping

Name

Delay Area Delay Area Delay Area cc 12.0 167.7 9.5 192.0 8.0 193.3 cm82a 13.2 86.0 10.5 58.3 7.0 78.7 pcle 15.0 255.7 12.0 156.7 10.5 176.7 pm1 13.5 135.0 9.8 135.0 9.2 131.3 x2 17.7 151.0 9.8 109.7 9.8 109.7 cm163a 15.5 130.7 12.0 111.3 9.7 121.0 comp 32.5 401.3 26.0 502.7 21.2 454.3 cu 16.0 145.0 11.8 147.3 9.8 149.0 i1 12.7 183.0 11.5 132.3 9.8 111.0 cm151a 15.0 77.0 10.5 66.3 9.0 88.3 cht 9.2 459.7 9.2 320.7 8.2 323.7 ttt2 21.5 530.7 15.3 576.0 12.7 606.7 cm162a 12.7 164.7 12.0 111.3 9.7 122.7

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ConclusionsConclusions• Logic decomposition during technology mappingLogic decomposition during technology mapping

– Efficiently encode a Efficiently encode a setset on AND2/INV decompositions on AND2/INV decompositions– DynamicallyDynamically perform logic decomposition perform logic decomposition

• Two mapping proceduresTwo mapping procedures -mapping: -mapping: optimal over all AND2/INV decompositions optimal over all AND2/INV decompositions

(associative rule)(associative rule) -mapping: -mapping: optimal over all algebraic decompositions optimal over all algebraic decompositions

(distributive rule)(distributive rule)

• Was implemented and used for commercial Was implemented and used for commercial design projects design projects (in DEC/Compac alpha)(in DEC/Compac alpha)

• Extended for Extended for sequential circuitssequential circuits::– considers all retiming possibilities considers all retiming possibilities (implicitly)(implicitly) and and

algebraic factors across latchesalgebraic factors across latches

Technology Mapping

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