Technology for Planar Power Semiconductor Devices … for Planar Power Semiconductor Devices Package...

Technology for Planar Power Semiconductor Devices Package with

Improved Voltage Rating

by

Jing Xu

Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State

University in partial fulfillment of the requirements for the degree of

DOCTOR OF PHILOSOPHY

in

ELECTRICAL ENGINEERING

Khai. D. T. Ngo

Daan van Wyk

Guoquan Lu

Hardus Odendaal

Yilu Liu

Douglas Nelson

Dec. 5, 2008

Blacksburg, Virginia

Keywords: High voltage, Planar package, Embedded Power, SiC diode, MEDICI

Copyright 2008, Jing Xu

Technology for Planar Power Semiconductor Devices Package with

Improved Voltage Rating

Jing Xu

ABSTRACT

The high-voltage SiC power semiconductor devices have been developed in recent

years. They cause an urgent in the need for the power semiconductor packaging to have

not only low interconnect resistance, less noise, less parasitic oscillations, improved

reliability, and better thermal management, but also High-Voltage (HV) blocking

capability.

The existing power semiconductor packaging technologies includes wire-bonding

interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates

structure (MIPPS), dimple array interconnection (DAI), power overlay (POL)

technology, and embedded power (EP) technology. None of them meets the

requirements of low profile and high voltage rating.

The objective of the work in this dissertation is to propose and design a high-voltage

power semiconductor device packaging method with low electric field stress and low

profile to meet the requirements of high-voltage blocking capability. The main

contributions of the work presented in this dissertation are:

1. Understanding the electric field distribution in the package.

The power semiconductor packaging is simulated by using Finite Element Analysis

(FEA) software. The electric field distribution is known and the locations of high electric

field concentration are identified.

2. Development of planar high-voltage power semiconductor device packaging method

With the proposed structure in the dissertation, the electric field distribution of a planar

device package is improved and the high electric field intensity is relieved.

3. Development of design guidelines for the proposed planar high-voltage device

packaging method.

The influence of the structure dimensions and the material properties is studied. An

optimal design is identified. The design guideline is given.

iii

4. Fabrication and experimental verification of the proposed high-voltage device

packaging method

A detailed fabrication procedure which follows the design guideline is presented. The

fabricated modules are tested by using a high power curve tracer. Test results verify the

proposed method.

5. Simplification of the structure model of the proposed device package

The package structure model is simplified through the elimination of power

semiconductor device internal structure model. The simplified model can be simulated

by a non-power device simulator. The simulation results of the simplified model match

the simulation results of the complete model very well.

iv

Acknowledgements

First and foremost, I would like to express my deepest gratitude to my academic

advisors, Dr. J. D. van Wyk and Dr. Khai D. T. Ngo. Dr. van Wyk introduced me into

this wonderful packaging world and guided me to the research of the topic. In the first

three years of my study, with his greatest patience, he leads me to this very interesting

area, about which I have great passion finally, although knew nothing from the

beginning. Even after his retirement, Dr. van Wyk gave me many support and mentoring

on the research. To me, he is like both an advisor and a grandfather. In the last two years

of my study, Dr. Ngo gave me tremendous supervising on the research. His brilliant

ideas, his illuminating comments and suggestions, and his strict training lead the

completion of this dissertation. I am impressed by his broad thoughts and diligent

attitude. It is such a great experience to be both professors’ student for these years. Both

of them showed me their great intuition, broad knowledge and accurate judgment.

Without their unconditional support in guiding me to conduct and complete this research,

this dissertation would never have come into existence. The most precious thing I learned

from them is the attitude toward research, which can be applied to every other aspect of

life, too.

I also would like to thank Dr. Zhenxian Liang and Mr. Dan Huff. Dr. Liang taught me

everything about embedded power, which is the basis of my dissertation. Dan gave me

tremendously unconditional support from every aspect of the packaging lab, and this

work wouldn’t be done without his help.

I am grateful to have Dr. GQ Lu, Dr. William Hardus Odendaal, Dr. Yilu Liu, and Dr.

Doug Nelson as my doctoral committee members. I owe them a special note of

appreciation for their encouragement and expertise throughout my graduate studies.

I am indebted to the National Science Foundation and Center for Power Electronics

Systems (CPES) at Virginia Tech for funding this research (under award number EEC-

9731677) and providing research facilities. I also appreciate the support from all the staff

in CPES, especially Dan Huff. I wish to thank all the colleagues and friends at CPES for

their insightful discussions, guidance, and helps during my stay at CPES. I will always

cherish our friendships.

v

Table of Contents

ABSTRACT................................................................................................................................... ii

Acknowledgements ...................................................................................................................... iv

Table of Contents .......................................................................................................................... v

List of Figures.............................................................................................................................. vii

List of Tables ...............................................................................................................................xii

Chapter 1: Introduction.......................................................................................................- 1 - 1.1. Requirements for the power semiconductor packaging in power electronics

applications .............................................................................................................................- 1 -

1.2. Review of existing packaging technologies of the power semiconductor devices and

modules ...................................................................................................................................- 2 -

1.2.1. Wire bonding ...................................................................................................... - 3 -

1.2.2. Press Pack ........................................................................................................... - 4 -

1.2.3. Flip-Chip Technology......................................................................................... - 4 -

1.2.4. Metal-Posts Interconnected Parallel Plates (MPIPPs) Technology.................... - 6 -

1.2.5. Dimple Array Interconnect (DAI) Technology .................................................. - 7 -

1.2.6. Power Overlay (POL) Technology ..................................................................... - 8 -

1.2.7. Embedded Power Technology ............................................................................ - 8 -

1.2.8. Summary of existing power semiconductor packaging of the power

semiconductor devices and modules................................................................................. - 10 -

1.3. Research objective and approach..............................................................................- 11 -

1.4. Dissertation outline ...................................................................................................- 12 -

Chapter 2: Survey of Strategies for Reduction of Electric Field in Semiconductor Die

and Packages. ..........................................................................................................................- 13 - 2.1. Introduction...............................................................................................................- 13 -

2.2. Overview of classical techniques for high electric field intensity reduction in power

semiconductors [34][35] .......................................................................................................- 13 -

2.3. Overview of high electric field reduction techniques in wire bonding packages [37][38]

...................................................................................................................................- 16 -

2.4. Summary...................................................................................................................- 19 -

Chapter 3: Development of High-Voltage Embedded Power (HVEP) Technology via

MEDICI......... ..........................................................................................................................- 21 - 3.1. Introduction...............................................................................................................- 21 -

3.2. Evaluation of two LVEP structures ..........................................................................- 23 -

3.3. Parametric study of LVEP #2 ...................................................................................- 26 -

3.4. Medium-Voltage Embedded Power (MVEP) structure............................................- 31 -

3.5. Development of High-Voltage Embedded Power (HVEP) structure .......................- 38 -

3.6. Geometry impact on HVEP structure .......................................................................- 41 -

3.7. Summary...................................................................................................................- 47 -

Chapter 4: Design Guidelines for the HVEP package and Fabrication Process of a

HVEP package ........................................................................................................................- 49 -

vi

4.1. Design guidelines for the HVEP package.................................................................- 49 -

4.1.1. Introduction to engineering design ................................................................... - 49 -

4.1.2. Design practice in the HVEP package .............................................................. - 50 -

4.1.3. Design guidelines for the HVEP package......................................................... - 51 -

4.1.4. A design example.............................................................................................. - 53 -

4.2. Fabrication process of a HVEP package...................................................................- 55 -

4.2.1. Devices and materials ....................................................................................... - 55 -

4.2.2. Design of the fabrication procedure.................................................................. - 56 -

4.2.3. Fabrication process and experimental results ................................................... - 59 -

4.3. Summary...................................................................................................................- 63 -

Chapter 5: Simplified Modeling of the HVEP Package..................................................- 65 - 5.1. Model simplification.................................................................................................- 65 -

5.2. Simulation in MAXWELL 2D..................................................................................- 67 -

5.3. Summary...................................................................................................................- 70 -

Chapter 6: Summary..........................................................................................................- 72 - 6.1. Contributions.............................................................................................................- 72 -

6.2. Recommendations.....................................................................................................- 76 -

Reference....... ..........................................................................................................................- 77 -

Appendix Mathematical Modeling of the Simplified Model of HVEP........................- 81 - A1 Conformal Mapping and Schwarz-Christoffel Transformation......................................- 81 -

A2 Model of HVEP package ................................................................................................- 84 -

A3 The problem ....................................................................................................................- 86 -

vii

List of Figures

Fig. 1.1 Power semiconductor package using wire bonding technology

[14]............................................................................................................ - 1 -

Fig. 1.2 Pictures of the IGBT devices with press pack interconnect [18] © 2004

IEEE. (a) Asymmetric 4500 V/1000 A Press Pack IGBT along with a

submodule comprising 12 IGBT chips. (b) Direct pressure contact on the

gate............................................................................................................ -4-

Fig. 1.3 Examples of BGA package. (a) MOSFET BGA [21]. (b) BGA for

lateral MOSFET [22] © 2004 IEEE. (c) FlipFET [23]. (d) BGA for

Volterra integration module [24]..................................................................... -5-

Fig. 1.4 Flip-chip on flex technology [25] © 2001 IEEE. (a) Picture of a

module. (b) Cross-section schematic............................................................... -6-

Fig. 1.5 Metal-posts interconnected parallel plates technology [29] © 1999

IEEE. (a) Picture of MPIPPs module. (b) Cross-section schematic............... -7-

Fig. 1.6 Dimple array interconnect technology [31]. (a) Picture of DAI. (b)

Schematic cross-section............................................................................ -7-

Fig. 1.7 Cross-sectional schematic of a GE-POL structure.................................... -8-

Fig. 1.8 Embedded power technology. (a) Picture of an IPEM using embedded

power technology. (b) Cross-sectional schematic of an IPEM using

embedded power technology.................................................................... -9-

Fig. 2.1 Electric field crowding for a planar diffused junction.............................. -13-

Fig. 2.2 Cross-section of edge termination with a single floating field ring.......... -14-

Fig. 2.3 Cross-section of edge termination with multiple field rings..................... -14-

Fig. 2.4 Planar junction with field plate................................................................. -15-

Fig. 2.5 Cross section of field plate with step oxide.............................................. -15-

Fig. 2.6 Cross section of field plate with step oxide.............................................. -16-

Fig. 2.7 Cross section of resistive field plate......................................................... -16-

Fig. 2.8 Cross Edge termination design combining floating field rings with field

plate........................................................................................................... -16-

Fig. 2.9 Cross-sectional diagram of an IGBT module package using wire

bonding..................................................................................................... -17-

Fig. 2.10 Cross Electric field concentration due to proximity between track and

bonding..................................................................................................... -17-

Fig. 2.11 Influence of a resistive layer..................................................................... -18-

Fig. 2.12 Influence of modification of metal edge................................................... -19-

Fig. 2.13 Module reinforcement at the copper edges............................................... -19-

Fig. 3.1 Cross sectional view of an IPEM.……………………………………… -22-

Fig. 3.2 Enlarged cross-sectional schematic of the package of a semiconductor

device using LVEP.…………………………………………………….. -22-

viii

Fig. 3.3 Cross-sectional schematic of a 10 kV PiN SiC diode [42]....................... -23-

Fig. 3.4 Electric field and potential distribution for an abrupt parallel-plane

P+/N junction [34].................................................................................... -23-

Fig. 3.5 Simulation model and result of LVEP structure in MEDICI. (a)

Dimensions and materials of the structure. (b) Distribution of

equipotential lines..................................................................................... -25-

Fig. 3.6 Electric field intensity in the insulation materials of LVEP structure

when the applied voltage on the cathode is 13.5 kV. (a) Along the x

direction (lateral direction) line AB in the polyimide. (b) Along the y

direction (vertical direction) line CD in the embedded insulation

material.Electric field intensity in the insulation materials of LVEP

structure when the applied voltage on the cathode is 13.5 kV. (a)

Along the x direction (lateral direction) line AB in the polyimide. (b)

Along the y direction (vertical direction) line CD in the embedded

insulation material. ................................................................................... -26-

Fig. 3.7 Simulation model and result of LVEP #2 structure in MEDICI. (a)



Fig. 3.8 Electric field intensity in the insulation materials of LVEP #2 structure

when the applied voltage on the cathode is 13.5 kV. (a) Along the x

direction (lateral direction) line AB in the polyimide. (b) Along the y

direction (vertical direction) line CD in the embedded insulation

material..................................................................................................... -28-

Fig. 3.9 Comparison of the maximum electric field intensity between two

LVEP structures........................................................................................ -28-

Fig. 3.10 Parameters in the LVEP#2 structure study............................................... -29-

Fig. 3.11 Variation of maximum electric field intensity with the thickness of

polyimide. (a) Inside the polyimide at the upper corner. (b) Inside the

embedded insulation material at the upper and lower corner................... -29-

Fig. 3.12 Comparison of the equipotential lines distribution between two

different thicknesses of polyimide. (a) D = 100µm. (b) D = 500 µm..... -30-

Fig. 3.13 Variation of maximum electric field intensity with the dielectric

constant of polyimide. (a) Inside the polyimide. (b) Inside the

embedded insulation material................................................................... -31-


different dielectric constant of polyimide. (a) εr = 3. (b) εr = 1............. -31-


constant of embedded insulation material. (a) Inside the polyimide. (b)

Inside the embedded insulation material................................................... -32-


different dielectric constant of embedded insulation material. (a) εr’ =

4. (b) εr’ = 15........................................................................................... -32-

ix

Fig. 3.17 Simulation model and result MVEP structure in MEDICI. (a)



Fig. 3.18 Electric field intensity in the insulation materials of MVEP structure.

(a) In the polyimide. (b) In the embedded insulation material................ -35-

Fig. 3.19 Comparison of the maximum electric field intensity between two

LVEP structures and the MVEP structure................................................ -36-

Fig. 3.20 Parameters in the MVEP structure study.................................................. -36-

Fig. 3.21 Variation of maximum electric field intensity with the thickness of

polyimide. (a) Inside the polyimide at the upper corner. (b) Inside the

embedded insulation material................................................................... -36-


different thicknesses of the polyimide. (a) D = 100 µm. (b) D = 500

µm............................................................................................................. -37-


constant of polyimide. (a) Inside the polyimide at the upper corner. (b)

Inside the embedded insulation material................................................... -37-


different dielectric constant of polyimide. (a) εr = 4. (b) εr = 8............. -37-

Fig. 3.25 Equivalent circuit model of LVEP#2. (a) Structure of LVEP#2. (b)

Series capacitor model of a small area in the LVEP#2 structure.............. -38-

Fig. 3.26 Simulation model and result of HVEP structure in MEDICI. (a)



Fig. 3.27 Electric field intensity in the insulation materials of HVEP structure.

(a) In the polyimide. (b) In the embedded insulation material................ -40-

Fig. 3.28 Comparison of the maximum electric field intensity of different

structures................................................................................................... -40-

Fig. 3.29 Parameters in the HVEP structure study................................................... -41-

Fig. 3.30 Variation of maximum electric field intensity at the corner of the

device with the thickness of the polyimide............................................... -42-

Fig. 3.31 Variation of maximum electric field intensity with the position of the

inserted metal layer. (a) Maximum electric field intensity in two

insulation materials. (b) Distribution of Equipotential lines at t =

200µm. ..................................................................................................... -42-

Fig. 3.32 Distribution of equipotential lines with different combination of the

position and the voltage of the inserted metal layer. (a) t = 0µm and V

= 0 V. (b) t = 200 µm and V = 5 kV. ................................................. -43-

Fig. 3.33 Variation of maximum electric field intensity with different

combination the pos of the inserted metal layer and its voltage............... -44-

x

Fig. 3.34 Variation of maximum electric field intensity with the width of the

inserted metal layer. (a) Maximum electric field intensity in the

polyimide. (b) Maximum electric field intensity in the embedded

insulation material..................................................................................... -45-

Fig. 3.35 Distribution of equipotential lines with different width of the inserted

metal layer. (a) w = 500µm. (b) w = -400 µm....................................... -45-

Fig. 3.36 Variation of the maximum electric field intensity along the horizontal

line at y = -100 µm with the angle of the polyimide .............................. -46-

Fig. 3.37 Distribution of equipotential lines with different angle of the

polyimide. (a) θ = 30°. (b) θ = 90°........................................................ -46-

Fig. 3.38 Comparison of the maximum electric field intensity of different

structures................................................................................................... -47-

Fig. 4.1 Engineering design process of HVEP package......................................... -51-

Fig. 4.2 A design example. (a) Physical layout design. (b) Inserted metal layer

design. (c) Polyimide layer design. (d) Top metallization design.......... -54-

Fig. 4.3 Picture and dimensions of a 2 kV SiC diode............................................ -55-

Fig. 4.4 Major fabrication steps of the LVEP package.......................................... -58-

Fig. 4.5 Major fabrication steps of the HVEP package.......................................... -59-

Fig. 4.6 Fabrication process of the HVEP package: step 1. Ceramic cutting........ -60-

Fig. 4.7 Fabrication process of the HVEP package: step 2. Chip embedding....... -60-

Fig. 4.8 Fabrication process of the HVEP package: step 3. Shim soldering.......... -60-

Fig. 4.9 Fabrication process of the HVEP package: step 4. Masking.................... -61-

Fig. 4.10 Fabrication process of the HVEP package: step 5. Thin layer copper

deposition.................................................................................................. -61-

Fig. 4.11 Fabrication process of the HVEP package: step 6. Interlayer patterning. -61-

Fig. 4.12 Fabrication process of the HVEP package: step 7. Top metallization

deposition.................................................................................................. -61-

Fig. 4.13 Fabrication process of the HVEP package: step 8. Electroplating and

etching....................................................................................................... -62-

Fig. 4.14 Test result of the fabricated HVEP package............................................. -62-

Fig. 4.15 Cross-sectional picture of one fabricated HVEP package........................ -63-

Fig. 4.16 ESEM picture of one fabricated HVEP package. (a) Copper shim edge.

(b) Package edge....................................................................................... -63-

Fig. 5.1 Model of the power semiconductor device. (a) Model in MEDICI. (b)

Simplified model....................................................................................... -66-

Fig. 5.2 Simplified model of the HVEP package................................................... -66-

Fig. 5.3 Voltage distribution on JTE...................................................................... -67-

Fig. 5.4 Simplified model for mathematical calculation and simulation............... -67-

Fig. 5.5 Comparison of the voltage distribution on JTE in MEDICI and

MAXWELL. (a) Voltage distribution in MEDICI. (b) Voltage

distribution in MAXWELL....................................................................... -68-

xi

Fig. 5.6 Comparison of the electric field intensity at different y locations.

Upper: MEDIC; Lower: MAXWELL 2D (a) y = 0. (b) y = 10 µm. (c)

y = 50 µm. (d) y = 100 µm. (e) y = 200 µm. (f) y = 300 µm................. -69-

Fig. 5.7 Explanation of two values in Fig. 5.6....................................................... -69-

Fig. 5.8 Errors of the simulation results in MAXWELL compared to the results

in MEDICI................................................................................................ -70-

Fig. A.1 Schwarz-Christoffel transformation. (a) Polygon (original plane) (b)

Upper-half plane (destination plane)........................................................ -82-

Fig.A.2 Elliptic function of first kind. (a) Rectangle (original plane) (b)

Upper-half plane (destination plane)........................................................ -82-

Fig.A.3 Transformation of the simplified structure. (a) Simplified structure

(rotate 90°). (b) Transformed structure.................................................... -84-

Fig.A.4 Equipotential lines approximation............................................................ -85-

Fig.A.5 Transformations. (a) Original rectangle (u-v). (b) Upper-half plane

after Elliptic Jacobian transformation (s-t). (c) Upper-half plane after

linear-fractional transformation (m-n). (d) Destination rectangle after

elliptic integral of the first kind (ξ-ζ)....................................................... -86-

Fig.A.6 Variation of aspect ratio with the parameter k.......................................... -87-

Fig. A.7 Error generation in the forward mapping. (a) upper-half plane in s-t

plane. (b) p-q plane after exponential transformation. (c) m-n plane

after linear-fractional transformation. (d) Destination rectangle in ξ-ζ

plane.......................................................................................................... -88-

xii

List of Tables

Table I Properties of silicon and 4H-SiC........................................................ -2-

Table II Comparison of different power semiconductor device packaging

technologies ....................................................................................... -11-

Table III Dimensions of the simulation model and material properties ........... -24-

Table IV Simulation setting in MEDICI .......................................................... -24-

Table V Parameters of the LVEP#2 structure study......................................... -27-

Table VI Parameters of the MVEP structure study............................................ -33-

Table VII Parameters of the HVEP structure study............................................ -41-

Table VIII Comparison of designed values and fabricated values of HVEP

package............................................................................................... -62-

- 1 -

Chapter 1: Introduction

1.1. Requirements for the power semiconductor packaging in power

electronics applications

Power electronics devices and modules are the key components in power systems for

maneuvering the storage, conversion, and conditioning of massive electromagnetic

energy. Marketing demands on higher power density, higher frequency, higher current,

higher voltage, and higher temperature are the driving forces on pushing the packaging

technologies to a higher level.

Electronic packages provide protection (mechanical, chemical and electromagnetic),

heat dissipation, and power and signal distribution for electrical components and their

interconnections [1]. Hierarchically, the packaging begins at the interface of the

semiconductor chip itself, which is considered the power semiconductor packaging. The

power semiconductor packaging deals with the attachment of one or more bare chips to a

substrate, the interconnection from these chips to package leads, and the encapsulation.

The power semiconductor interconnection plays an important role because it directly

interfaces with the chips that contain millions of transistor circuits electrically, thermally

and mechanically.

In the specific application of power semiconductor devices and modules, the power

semiconductor packaging must fulfill very different requirements compared to those for

microelectronic Integrated Circuit (IC) chips. First, the current and power handling

capability per bond or joint increases by several orders of magnitude. This requires a

larger cross-section area for these interconnections. Second, the voltage rating varies

with the power semiconductor and the applications and can be as high as several

kilovolts. This leads to high breakdown voltage demands on the insulation and the

encapsulation. Third, since these devices operate at high frequencies, in order to maintain

high efficiency, parasitic noise must be reduced. Therefore, the conduction path must be

minimized. Furthermore, the increased power density drives the power semiconductor

packaging to improve its role in heat dissipation [2]. Last, reliability of the power

- 2 -

semiconductor interconnections is vital in ensuring that the electronic assemblies have an

extended lifetime.

Silicon Carbide (SiC) has gained tremendous interest as a promising wide-bandgap

material for high power and high temperature applications. Table I shows the

comparison of the properties between Silicon (Si) and 4H-SiC [3]. The high critical

breakdown electric field lends the SiC material the development of High-Voltage (HV)

devices. Substantial progress has been made in the recent years in SiC power device

development, especially in high-voltage area. The SiC PiN diodes of 10 kV or even

higher blocking voltage have been reported [4]-[8], and the SiC MOSFETs of 10 kV are

also demonstrated and evaluated in recent years [9]-[12].

With the increasing of the voltage rating of the SiC semiconductor devices, the power

semiconductor packaging is required to have not only low interconnect resistance, less

noise, less parasitic oscillations, improved reliability, and better thermal management, but

also HV blocking capability, which increases the electric field stress in the insulation and

encapsulation in the package.

1.2. Review of existing packaging technologies of the power

semiconductor devices and modules

The existing power semiconductor packaging of the power semiconductor devices and

modules include wire-bonding, press pack, flip-chip technology, metal posts

TABLE I

PROPERTIES OF SILICON AND 4H-SIC

Property Si 4H-SiC

Bandgap, Eg (eV) 1.12 3.26

Electron mobility, µn (cm2/Vs) 1400 800

Hole mobility, µp (cm2/Vs) 450 140

Intrinsic carrier concentration, ni (cm-3

) at 300 K 1.5×1010

5×10-9

Electron saturated velocity, vnsat (x 107 cm/s) 1.0 2.0

Critical breakdown electric field, Ecrit (kV/mm) 25 220

Thermal conductivity, Θ (W/cm⋅K) 1.5 3.0-3.8

Dielectric constant 11.8 9.8

- 3 -

interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI),

power overlay (POL) technology, and embedded power (EP) technology.

1.2.1. Wire bonding

Wire bonding is the most common chip-level interconnect technology in power

electronics nowadays. Fine wires are attached between the I/O pads on a chip and its

associated package pins. This technology originated from AT&T’s bean lead bonding in

the 1950s. It accounted for over 90% of all of chip-to-package interconnections formed

in 1999 [13].

In a power semiconductor package, the power semiconductor dice are solder-attached

to a copper heat spreader or substrate, and the source and gate terminals are connected

from the Aluminum (Al) chip bonding pads to the nickel-plated copper leads by

Aluminum wires. The top of the dice and the bonding wires are encapsulated with

molding compound for insulation, mechanical support and protection. Fig. 1.1 shows a

picture of wire bonded power semiconductor without the encapsulation [14].

The advantages of the wire bonding technology include the highly flexibility chip-to-

package interconnection process, the high yield interconnection processing, the easily

programmed bonding cycles, the very large industry infrastructure supporting the

technology, and the rapid advances in equipment, tools, and material technology. The

disadvantages include the slower interconnection rates due to the point-to-point

processing of each wire bond, the long chip-to-package interconnection length, the

degraded electrical performance, the larger footprint required for chip-to-package

Fig. 1.1. Power semiconductor package using wire bonding technology [14].

- 4 -

interconnection, the potential for wire sweep during encapsulation over molding, and the

limited heat dissipation capability.

1.2.2. Press Pack

Press pack is one of the technologies without using the bonding wires. It was originally

developed by Fuji, Toshiba and ABB [15]-[18], and applied to the high-power devices,

such as diodes, thyristors, GTOs, etc., in the area of HVDC, SVC, transportation system,

and motor drives. The press pack structure has evolved to a sandwiched structure and

involves the Molybdenum (Mo) strain buffers, gate connection and insulation, Copper

(Cu) pole-piece and a ceramic ring. Fig. 1.2 shows the pictures of the IGBT devices with

press pack interconnection [18].

The press pack technology has a proven reliability record for the applications that

require extended thermal and power cycling reliability. Since there is no soldering

process is involved, this method eliminates the residual stress on each material. It also

enables the redundant converter design and double-sided cooling. The concerns of press

pack technology includes its higher manufacturing cost, the more complicated mounting

arrangement to maintain the pressure, and the damage caused by the pressure force.

1.2.3. Flip-Chip Technology

(a) (b)

Fig. 1.2. Pictures of the IGBT devices with press pack interconnect [18] © 2004 IEEE. (a) Asymmetric

4500 V/1000 A Press Pack IGBT along with a submodule comprising 12 IGBT chips. (b) Direct

pressure contact on the gate.

- 5 -

Flip-chip technology is another available technology for the power semiconductor

packaging. It firstly emerged in IC as low-cost, high density and reliable

interconnections [19][20]. The key material in the structure is the solder balls. The Ball

Grid Array (BGA) is one of the applications of Flip-chip technology. Some examples are

shown in Fig. 1.3 [21]-[24]. The advantages of BGA include higher interconnect density,

better electrical performance than wire-bond due to short interconnection path, better

thermal performance by using thermal vias, and the reduced placement and handling

issues. One big drawback of BGA is the difficulty to inspect the formed solder joints

after assembling, which is very time-consuming.

The flip-chip on flex is the extension of the flip-chip technology and the flex circuitry

technology to the power electronics packaging and takes the advantages of these two

technologies [25]-[28]. As shown in Fig. 1.4, the module using flip-chip on flex

technology has a multilayer structure. The bottom layer is a direct-bond copper (DBC)

substrate which provides both the thermal and electrical path. The top layer of the

structure is a double-sided flexible copper-clad laminate which is an adhesiveless

composite of polyimide file bonded to copper foil. A novel triple-stacked solder

(a) (b)

(c) (d)

Fig. 1.3. Examples of BGA package. (a) MOSFET BGA [21]. (b) BGA for lateral

MOSFET [22] © 2004 IEEE. (c) FlipFET [23]. (d) BGA for Volterra integration module

[24].

- 6 -

bumping technique is used to connect the power devices to the flexible substrate with a

circuit pattern for gate drive components. The module is encapsulated in underfill

polymer materials to reduce the thermo-mechanical stresses imposed on the solder joints.

Finally, the gate drive and control circuits are built on the top of the flex circuitry using

either flip-chip or surface-mount technology. This power semiconductor packaging

reduces the parasitcis, minimizes the thermal rise, and realizes a three-dimensional (3D)

structure. However, this technology relies on the solder balls for the interconnection,

thus it has the same problem as the BGA technology.

1.2.4. Metal-Posts Interconnected Parallel Plates (MPIPPs) Technology

The metal-posts interconnected parallel plates (MPIPPs) technology is another power

semiconductor packaging [29][30]. It uses the directly bonded metal posts to replace the

bonding wires, as shown in Fig. 1.5. An Aluminum Nitride (AlN) DBC is employed as

the base substrate. The power devices are attached to the substrate directly by soldering.

The copper (Cu) posts of different sizes and heights are soldered on the top of the devices

and the copper metallization on the AlN substrate. The top DBC plate is etched to a

desired pattern and attached onto the copper posts.

This technology has lower DC resistance than the conventional wire bonding, and it is

also conclude that the parasitic noise is much lower than the wire bonding technology.

However, this technology requires the solderable devices through the metallization of the

Aluminum (Al) contact.

Integrated Communications, Gate Drives and Protection

DeviceDevice

Double-sided FlexDevice Device

Solder bump Encapsulant

DeviceDevice-


Heat Spreader

Adhesive

DeviceDevice


Underfill

DeviceDevice-

Device Device

Heat Spreader

DBC


DeviceDevice



DeviceDevice-

Double-

Device Device

Heat Spreader

Adhesive

DeviceDevice


Underfill

DeviceDevice-

Device Device

Heat Spreader

DBC


DeviceDevice



DeviceDevice-


Heat Spreader

Adhesive

DeviceDevice


Underfill

DeviceDevice-

Device Device

Heat Spreader

DBC


DeviceDevice



DeviceDevice-

Double-

Device Device

Heat Spreader

Adhesive

DeviceDevice


Underfill

DeviceDevice-

Device Device

Heat Spreader

DBC

(a) (b)

Fig. 1.4. Flip-chip on flex technology [25] © 2001 IEEE. (a) Picture of a module. (b) Cross-section

schematic.

- 7 -

1.2.5. Dimple Array Interconnect (DAI) Technology

The dimple array interconnect (DAI) is a 3D power semiconductor packaging

technique. The electrical interconnection is established by the formation of solder bumps

between device electrodes and the preformed array of dimples on a metal sheet, as shown

in Fig. 1.6 [31]. The result is a low-profile planar interconnection that is suitable for

multilayer integration with other components. With the exception of fabrication the

dimpled copper sheet, the DAI process follows the typical solder joint fabrication

process.

This technique reduces the interconnect parasitics and increases thermal capability of

the power semiconductor packaging. However, in a joint formed by controlled collapse

bonding (CCB), the mismatch of the coefficient of thermal expansion (CTE) between the

Al Pad

Passivation

UBM

Solder

Bump

Solder Dimple on Copper Flex

Underfill

Silicon ChipAl Pad

Passivation

UBM

Solder

Bump

Solder Dimple on Copper Flex

Underfill

Silicon Chip

(a) (b)

Fig. 1.6. Dimple array interconnect technology [31]. (a) Picture of DAI. (b) Schematic cross-section.

Metal PostsEncapsulant

AlN

CuHybrid Driver Circuit

Heat Sink (MMC, Al, etc)

Power device

Device DeviceDevice Device

or AluminaHeat Sink (MMC, Al, etc)


Metal PostsEncapsulant

AlN

CuHybrid Driver Circuit

Heat Sink (MMC, Al, etc)

Power device


or AluminaHeat Sink (MMC, Al, etc)


(a) (b)

Fig. 1.5. Metal-posts interconnected parallel plates technology [29] © 1999 IEEE. (a) Picture of

MPIPPs module. (b) Cross-section schematic.

- 8 -

dimpled copper sheet and the silicon causes thermal-mechanical problems which are the

stress concentrated along the high-angle joint edge on the silicon.

1.2.6. Power Overlay (POL) Technology

The Power Overlay (POL) Technology developed by GE is another approach which

eliminates the wire bonding through the utilization of the metalized Cu vias/polyimide to

achieve power and control interconnection [32][33]. As shown in Fig. 1.7, power

semiconductor devices are soldered to a Direct Bonded Copper (DBC) substrate from the

backside. The difference in device thickness is compensated by copper shims. A thin

layer of polyimide sheet is laminated over the die after vias are laser machined or

mechanically punched through the film. The whole top surface is metalized

(electroplated) with copper. Circuit patterns are achieved by the application of photo-

resist and chemical etching processes.

The POL technology eliminates the wire bonds with metallurgical interconnections. It

has better electrical performance through reduced interconnections parasitics. The

thermal performance is improved through the reduced number of thermal interfaces and

double-sided heat removal. The reduced profile and more flexible packaging provide the

options for stacking additional circuits. However, this POL structure has not been

successfully tested for high-power applications.

1.2.7. Embedded Power Technology

Fig. 1.7. Cross-sectional schematic of a GE-POL structure.

- 9 -

Another multi-layer integration technology which can be applied to the power

semiconductor packaging is the Embedded Power Technology. A multi-layer structure

that uses ceramic substrates, screen-printable dielectric materials and solder is employed

to enclose the power semiconductor devices, as shown in Fig. 1.8 (b). The power

semiconductor devices are mounted in the openings on the ceramic frame with adhesive

polymer that surrounds the device edges. The interlayer dielectric is a kind polymer that

is screen printed with designed pattern, for example, the vias corresponding to the pads of

the devices. The deposited Cu pattern is on the top as the interconnect layer. In order to

handle high current, a copper electroplating process is employed to thicken the deposited

Cu seed layer. This multi-layer planar stacking construction not only provides the power

semiconductor packaging through metallurgical contact to aluminum pads on the power

semiconductor devices, but also carries the wiring for the top electric circuitry. Fig. 1.8

(a) is the picture of an Integrated Power Electronics Module (IPEM) that uses the

Embedded Power Technology.

(a)

Heat Spreader

C-ChipS-ChipS-Chip

Componen

t

I/O PinsComponentComponent

Base Substrate

Ceramic Solder

Via

Heat Spreader

C-ChipS-ChipS-Chip

Componen

t

Componen

t

I/O PinsComponentComponentComponent

Base Substrate

Ceramic SolderSolder

Via

(b)

Fig. 1.8. Embedded power technology. (a) Picture of an IPEM using embedded power technology. (b)

Cross-sectional schematic of an IPEM using embedded power technology.

- 10 -

This technology features the building-up of interconnections on planar power

semiconductor devices which are embedded in a ceramic frame. The integrated power

stage similar to the Integrated Circuits (ICs) is fabricated through a thin- and thick-file

approach, which is an extension of wafer level process technology. The compact

interconnection also eliminates the bond wires and one-side contact interface. Both

electrical and thermal performance is improved by the low profile structure. Beside all

the merits of the POL technology, the passive components can be easily embedded in the

ceramic frame as the power semiconductor devices in the Embedded Power Technology,

which is not realized in the POL technology.

1.2.8. Summary of existing power semiconductor packaging of the power semiconductor devices and modules

Wire bonding is the most mature and low-cost technology. However, its large

footprint, high parasitics, and other disadvantages make it less attractive. The press pack

is widely used as well, but the concerns of this technology come from the pressure and

the structure itself. The flip-chip on flex technology, the metal-posts interconnected

parallel plates technology, and the dimple array interconnect technology are 3D

integration technology. They are good for power semiconductor packaging as well as the

multi-chip system packaging. The elimination of the wire bonds makes the electrical

parasitics much less than the wire bonding package. However, the thermo-mechanical

stress and the process make them less favorable. The power overlay technology and the

embedded power technology utilizes the metallurgical contact to form a multi-layer

stackable structure. The low profile, low parasitics, high thermal performance, and the

flexibility in packaging are the common advantages of these two technologies.

Compared to the POL technology, the embedded power technology uses the thin- and

thick-film approach in the IC fabrication process, and enables both power semiconductor

device and passive components to be integrated in one package. With the consideration

of the integration of more components in one package, the embedded power technology

is a good candidate for both power semiconductor packaging and system packaging.

The voltage rating, current rating, and availability of these technologies are compared

in Table II.

- 11 -

1.3. Research objective and approach

The high-voltage packaging involves both structure optimization and material

improvement in the package. The structure optimization is to minimize the electric field

intensity hotspots and make the electric field distribution in the structure as even as

possible. The material study focuses on the high dielectric strength material selection and

application. In addition, the proper selection of the power semiconductor packaging for

the high-voltage system packaging is also required to be considered.

The embedded power technology is an attractive candidate for both power

semiconductor and system packaging, thus it is selected as a candidate for the high-

voltage packaging. This research proposes the high-voltage packaging that is suitable for

both power semiconductor packaging and the system packaging derives from the

embedded power technology, so called high-voltage embedded power (HVEP)

technology.

In designing for the high-voltage package, the objective is to build even electric field

distribution and keep the profile as low as possible. With the in-depth study on the

electric field distribution in the package using the embedded power technology, hotspots

are identified and analyzed. Furthermore, after a parametric study on the dimensions and

the material properties in the structure, a design guideline is suggested. This guideline

can facilitate the future design of the package, thus reduce the design cycle time.

TABLE II

COMPARISON OF DIFFERENT POWER SEMICONDUCTOR DEVICE PACKAGING TECHNOLOGIES

Voltage Rating Current Rating Commercialization

Wire Bonding > 6 kV > 4 kA Yes

Press Pack 6.5 kV > 1 kA Yes

Flip Chip on Flex 42 V 6.5 A No

Metal Post interconnected parallel

plate

400 V 10 A No

Dimple array interconnect 600 V 50 A No

Power Overlay 2.4 kV 25 A No

Embedded Power 400 V 10 A No

- 12 -

1.4. Dissertation outline

This dissertation consists of seven chapters including necessary background, motivation

and the objectives of the research effort in Chapter 1. Chapter 1 also gives the review of

existing power semiconductor packaging technologies for the power semiconductor

devices and modules. Chapter 2 surveys the existing methods to relieve the high electric

field intensity in high-voltage power semiconductor devices and the wire bonding

packages.

In Chapter 3, the low-voltage package using embedded power technology (LVEP) is

studied in details. The materials are evaluated and the electric field distribution is

simulated in MAWELL. Based on the simulation results, simple solutions are discussed

as well. Chapter 4 presents the simulation in MEDICI of LVEP simulated in

MAXWELL in Chapter 3, and compares the results in two different simulators firstly.

Then the medium-voltage embedded power (MVEP) technology and the high-voltage

embedded power (HVEP) technology are proposed. Next, the dimensions and material

properties in the HVEP structure are studied. In Chapter 5, the design guideline of HVEP

structure is suggested and the fabrication process of the HVEP module is proposed. The

HVEP structure and the design guidelines are verified by a fabricated 2 kV SiC diode

package in house. In Chapter 6, a simplified model of the power semiconductor device is

proposed. The feasibility of the application of the conformal mapping to the simplified

structure to calculate the electric field distribution mathematically is studied. Simulations

in MAWELL with the simplified model is done and compared to the simulation results in

MEDICI for the HVEP structure. Finally, Chapter 7 contains a summary of the research

and the contribution of this work towards new packaging technology for high-voltage

devices and modules.

- 13 -

Chapter 2: Survey of Strategies for Reduction of Electric

Field in Semiconductor Die and Packages

2.1. Introduction

Inside the power semiconductor, the PN junction bares the high voltage applied to the

device. Many measures have taken to reduce the electric field crowding at the PN

junction. These measures are reviewed firstly in this Chapter.

There are ways that have been reported to increase the voltage capability of a package

using wire bonding technology. The high electric field concentration is studied through

simulation and several solutions are developed to limit the peak electric field intensity in

the literature. These methods are discussed secondly.

2.2. Overview of classical techniques for high electric field intensity

reduction in power semiconductors [34][35]

From the theoretical analysis, there is an upper bound for the breakdown voltage of

parallel-plane (semi-infinite) junction in power devices. However, in practice this value

can be reduced by the presence of high electric field concentration at the edges of the

device. As shown in Fig. 2.1, which is a planar diffused junction, there is electric field

crowding at the edges.

An elegant approach to reduce the electric field at these edges is by the placement of

floating field rings, which is shown in Fig. 2.2. The objective of this method is to extend

the depletion boundary along the surface and reduce the electric field at the main

Fig. 2.1. Electric field crowding for a planar diffused junction

- 14 -

junction. A single field ring reduces depletion layer curvature, reduces the electric field

crowding, and enhances the breakdown voltage. An even greater improvement in

breakdown voltage can be obtained by using multiple float field rings working in

conjunction with each other. The depletion layer extends gradually away from the main

junction, as shown in Fig. 2.3.

Another method for reducing the depletion layer curvature involves changing the

surface potential. One way for achieving this is to place a metal field plate at the edge of

the planar junction, as illustrated in Fig. 2.4. Because the shape of the depletion region

depends on the surface potential, the depletion layer spreading at the surface is sensitive

to the potential applied to the filed plate. At the edge of the field plate, small oxide

thickness creates high peak electric field, but in the vicinity of the junction, thin oxide is

Fig. 2.3. Cross-section of edge termination with multiple field rings.

Fig. 2.2. Cross-section of edge termination with a single floating field ring.

- 15 -

helpful to decrease the peak electric field created by the surface charges and the radius

effect. Thus a multiple step oxide method is proposed as shown in Fig. 2.5.

Semi-insulating POlycrystalline Silicon (SIPOS) are thin SiOx films (O<x<2),

deposited by means of low pressure chemical vapor deposition on suitable substrates

(silicon or sapphire). Its conductivity varies in a wide range and depends on the oxygen

content as illustrated in Fig. 2.6 [36]. Due to the potential difference between its two

terminals, which are the metal on the top of N+ doping and P+ doping, a resistive field

plate with this material, as illustrated in Fig. 2.7, induces the leakage current to flow from

one terminate to the other. If the resistance is uniform in the SIPOS, there is a uniform

electric field along the surface direction in the SIPOS film. This uniform electric field

will modulate the surface electric field and extend the depletion boundary.

A common practice is to combine the field plate with the floating field ring, as shown

in Fig. 2.8. Each floating field ring is connected to a field plate. The filed plate extends

beyond the edge of floating field ring. The field plate reduces the electric field crowding

at each of the floating field rings.

Fig. 2.5. Cross section of field plate with step oxide.

Fig. 2.4. Planar junction with field plate.

- 16 -

2.3. Overview of high electric field reduction techniques in wire

bonding packages [37][38]

In [37] and [38], the study shows the high electric field concentration location in a

wire-bonding IGBT module using finite element simulations in association with partial

Fig. 2.8. Cross Edge termination design combining floating field rings with field plate.

Fig. 2.7. Cross section of resistive field plate.

Fig. 2.6. Cross section of field plate with step oxide.

- 17 -

discharge measurements and proposes some solutions to lower the high electric field

concentration.

The high voltage IGBT module is shown in Fig. 2.9. One side of two IGBT or diode

chips is connected to the copper layer; the other side is connected by the bonding wires to

the copper traces on the top of the substrate. The whole module is encapsulated by a

silicon gel. In the simulation, the IGBTs were modeled with the dielectric constant and

resistivity of silicon.

The simulation results show that the high electric field concentrates at four locations:

(1) the metallization edge, (2) the silicon die, (3) from trace to trace and (4) from trace to

bonding wire. This is illustrated in Fig. 2.10. The original value of the maximum electric

field intensity at the metallization edge is about 40kV/mm when the applied voltage is 2

kV. There are several solutions proposed to relieve the high electric field concentration at

the metallization edge.

0.500E+07

0.400E+07

0.300E+07

0.100E+07

0.200E+07

0.500E+07

0.400E+07

0.300E+07

0.100E+07

0.200E+07

Fig. 2.10. Cross Electric field concentration due to proximity between track and bonding. © 2003 IEEE

Fig. 2.9. Cross-sectional diagram of an IGBT module package using wire bonding. © 2003 IEEE

- 18 -

One of these solutions is the deposition of a resistive layer on the top of the substrate.

This is shown in Fig. 2.11. The function of the deposited resistive layer is explained in

the papers with the following reasoning. The deposited resistive layer has lower

resistivity in comparison to the insulation material and the substrate. Thus leakage

current flows through this layer, and the maximum electric field intensity is limited. The

resistivity depends on the structure and other material properties. An optimal value of

about 107 Ωm is given in the papers for their structures, and the maximum electric field

intensity is reduced to 9 kV/mm. Furthermore, the resulting leakage current is low

because the resistive layer doesn’t connect the metallization on both sides of the

substrate. This provides more freedom to choose the value of resistivity.

The second solution is to modify the shape of the metallization edge as shown in Fig.

2.12. The high electric field at the metallization edge can be reduced by modifying its

curvature. Furthermore, the metallization can be embedded in the substrate. This

arrangement has much better electrical characteristics and the maximum electric field

intensity is reduced to 9.2 kV/mm.

The third solution is an alternative solution to the previous one. Instead of embedding

the metallization in the substrate, it can be reinforced by a material with high field

breakdown value as shown in Fig. 2.13. This solution doesn’t reduce the maximum

electric field strength.

Fig. 2.11. Influence of a resistive layer. © 2003 IEEE

- 19 -

2.4. Summary

In this Chapter, the classical high electric field reduction techniques in power

semiconductor are reviewed firstly. These techniques include the floating field ring, three

methods of field plate, and the combination of these two techniques. Then the measures

in a wire bonding package to reduce the high field concentration is introduced. Several

high field locations were found, and three solutions were presented in the paper. The

results showed that the maximum electric field can be reduced to less than 1/4 of the

original value.

From the measures utilized in the power semiconductor and the methods proposed for

the IGBT module package, it can be seen great effort has been taken to reduce the

curvature of the equipotential lines in the package besides using better material to replace

Fig. 2.13. Module reinforcement at the copper edges. © 2003 IEEE

Fig. 2.12. Influence of modification of metal edge. © 2003 IEEE

- 20 -

the existing material. Thus, it is important to know the equal-potential line distribution in

the structure as well as the electric field distribution.

In the simulation of the IGBT module package, the devices are modeled as a lump

material; the internal information of the IGBT device structure is not included. The study

on the low-voltage embedded power (LVEP) structure in the next chapter is simulated by

following the same method as in this chapter. The simulation provides a quick and

simple concept of the internal of the package, which is useful for the structure

improvement in the future.

- 21 -

Chapter 3: Development of High-Voltage Embedded Power

(HVEP) Technology via MEDICI

In the previous Chapter, an IGBT wire bonding module is evaluated in [37] and [38].

The IGBTs are modeled as a piece of lump Si material, which doesn’t reflect the real

situation inside the semiconductor devices. From the electromagnetic field theory, the

external electric field in the packaging material and internal electric field in the device are

not independent to each other. In the device packaging design, it is important to know

how the electric field inside the device influences the external electric field in the

packaging materials. Software which models the semiconductor device structure is

necessary to simulate the internal electric field of the device.

MEDICI is a powerful device simulation program that can be used to simulate the

behavior of semiconductor devices. It models the two-dimensional (2D) distributions of

potential in a device and can be used to predict electrical characteristics for arbitrary bias

conditions [39]. Thus, extensive 2D simulations using MEDICI are performed to study

the high-voltage planar package of a 10 kV SiC diode [43] based on the LVEP

technology.

In this Chapter, the Low-Voltage Embedded Power (LVEP) module and the SiC diode

used in MEDICI for the device package design are introduced first. Then, the LVEP

structure and an improved structure, which is called LVEP #2, are evaluated in MEDICI.

Next, the geometry parameters and material properties that could influence the electric

field are studied. Based on the simulation results, a Medium-Voltage Embedded Power

(MVEP) package is proposed, and the influence of the geometry parameters and material

properties to this package is simulated as well. A High-Voltage Embedded Power

(HVEP) is proposed and simulated. The influence of geometry parameters of this

structure is studied intensively.

3.1. Introduction

The existing embedded power technology is a planar integration technology which is

originally developed for the packaging of the Integrated Power Electronics Modules

(IPEMs). The IPEM integrates the switching devices, conductors, controls and sensors,

- 22 -

etc. into a standardized manufacturable compact subassembly with improved electrical,

thermal, and mechanical performance. In this approach, the power chips are embedded in

a special encapsulating structure, as well as that all interconnections are deposited planar

metallization as shown in Fig. 3.1. The key elements in this structure is the embedded

power stage which is comprised of ceramic frame, power chips, insulation material, and

the metallization circuit that supports the high density interconnections of all IPEM

components [40]-[42].

Since it is difficult to measure the electric field inside the IPEM shown in Fig. 3.1,

finite element analysis is employed to explore the fields inside the modules. The

simulation only focuses on the region in dashed-line rectangle shown above, which

represents the package of the semiconductor device. Fig. 3.2 is the enlarged picture of

this region.

A 10 kV SiC PiN diode is designed in [43], and its cross-sectional schematic is shown

in Fig. 3.3. The device has a 110 µm thick lightly doped N-type (N-) region with the

doping concentration of 6×1014

cm-3

. There is a novel multi-zone, single-implanted JTE

in the device to achieve the high blocking capability.

Ceramic carrierEmbedded insulation

Embedded chip Metallization Top insulation

Thick metallization

Thin metallization

Fig. 3.2. Enlarged cross-sectional schematic of the package of a semiconductor device using LVEP.

Heat Spreader

C-ChipS-ChipS-Chip

Component

I/O PinsComponentComponent

Base Substrate

Ceramic Solder

Via

Heat Spreader

C-ChipS-ChipS-Chip

Component

Component

I/O PinsComponentComponentComponent

Base Substrate

Ceramic SolderSolder

Via

Fig. 3.1. Cross sectional view of an IPEM.

- 23 -

When the power semiconductor is in the state of blocking voltage, the voltage is

dropped on the depletion region formed at the PN junction. The potential outside the

depletion region is identical in the P-type region and N-type region respectively, as

shown in Fig. 3.4. Varies Junction Termination Technologies (JTEs) are employed to

extend the boundary of depletion region laterally and reshape the distribution of the

electric field. Laterally, the voltage is dropped on the JTE region. The potential at the

top of the device is equal to the potential on the bottom of the device. This situation is

the same to all the semiconductors that use JTE to improve their blocking capability.

Thus, MEDICI is employed to simulate both semiconductor and its package to model this

lateral voltage drop.

3.2. Evaluation of two LVEP structures

The LVEP structure and its improved structure are revisited in MEDICI with the

mentioned 10 kV SiC PiN diode. The simulation model of half of the LVEP structure is

Fig. 3.4. Electric field and potential distribution for an abrupt parallel-plane P+/N junction [34].

Fig. 3.3. Cross-sectional schematic of a 10 kV PiN SiC diode [42].

- 24 -

shown in Fig. 3.5 (a). The dimension of the simulation model and the properties of the

materials are shown in Table III. The simulation settings are shown in Table IV.

Fig. 3.5 (b) shows the equipotential lines in the whole package. The total number of the

equipotential lines is 50, and the voltage difference between two lines is around 275 V.

Since the voltage is applied to the metallization on the top of the polyimide and the

cathode of the diode, and the thickness of the polyimide is much less than the thickness

of the ceramic, most of the equipotential lines bend down at the upper corner of the

device, and some of them also bend at the lower corner of the device. Thus two electric

field “hotspot” are located at the upper corner and the lower corner of the devices inside

the embedded insulation material and the polyimide respectively, as shown in the two

circles in Fig. 3.5 (b).

Fig. 3.6 (a) is the maximum electric field inside polyimide, which is measured along the

x direction from the left of the polyimide layer to the right, as the dash-dot line AB

shown in Fig. 3.5 (a). Fig. 3.6 (b) is the maximum electric field intensity inside the

embedded insulation material, which is measured along the y direction from the top of

this material to the bottom, as the dashed line CD shown in Fig. 3.5 (a). The highest

electric field intensity points in both polyimide and the embedded insulation material are

located at the upper corner of the device; in the embedded insulation material, the second

highest electric field intensity is at the lower corner of the device. The remaining electric

TABLE IV

SIMULATION SETTINGS IN MEDICI

Anode Cathode

Applied voltage (kV) 0 13.5

Meshing method Manual meshing

Simulation stop criteria Leakage current > 1 µA

Simulation method Variable step simulation

TABLE III

DIMENSIONS OF THE SIMULATION MODEL AND MATERIAL PROPERTIES

SiC diode Polyimide Embedded insulation material Ceramic

Thickness (µm) 115.5 100 508 508

Width (µm) 500 1100 500 100

Dielectric constant 9.72 3 4 3.8

- 25 -

field peaks in the polyimide are nearby the locations of the main junction and JTEs. The

maximum electric field intensity in the polyimide is 5 times of its dielectric strength at

13.5 kV, and the maximum electric field intensity in the embedded insulation material is

as high as 24 times of its dielectric strength.

From the simulation result shown in Fig. 3.5, it is the bending of the equipotential lines at

upper and lower corner which makes high electric field intensity at these two locations.

An improved LVEP is proposed as shown in Fig. 3.7 (a), which is called LVEP #2 here.

(a)

(b)

Fig. 3.5. Simulation model and result of LVEP structure in MEDICI. (a) Dimensions and materials of

the structure. (b) Distribution of equipotential lines.

Cathod

Anode

y

x

SiC

Ceramic Embedded

Insulation

Material

100 µm

115.5 µm

508 µm

10 µm 500 µm

1000 µm

1100 µm

Polyimide

0

200

400

0.00 0.20 0.40 0.60 0.80 1.00

Distance

(µm)

Distance (mm)

Upper corner

Lower corner

A B

D

C

- 26 -

The bottom of the package is covered by metallization compared to LVEP to prevent the

bending of the equipotential lines at the lower corner. This structure is simulated in

MEDICI verify the idea. As shown in Fig. 3.7 (b), although the equipotential lines bend

down at the upper corner of the device with the same mechanism as it in the LVEP

structure, they bend to the right at the bottom of the LVEP #2 structure due to the

presence of the metallization on the bottom of the package. This reduces the high electric

field at the lower corner of the device significantly, as shown in Fig. 3.8. A comparison

of the simulation results between two LVEP structures is shown in Fig. 3.9.

3.3. Parametric study of LVEP #2

Although the electric field intensity at the lower corner of the device is reduced greatly,

its value and the field intensity at the other hotspot are still much higher than the

dielectric strength of two insulation materials. Both LVEP structures cannot survive at a

voltage of 13.5 kV. The LVEP structure involves several materials and has many

dimension variables. A parametric study is done to show the influence of the material

properties and the structure dimensions to LVEP #2 structure before any improvement is

made on it. Table V gives the parameters shown in Fig. 3.10 and the values.

E = 250 kV/mm

JTE1

JTE2

JTE3

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

E (

kV

/mm

)

050

100

150

200

25

0

E = 250 kV/mm

JTE1

JTE2

JTE3

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

E (

kV

/mm

)

050

100

150

200

25

0 E = 600 kV/mm

E = 250 kV/mm

Distance (um)

0.00 100 200 300 400 500

E (

kV

/mm

)

0.0

0200

400

600 E = 600 kV/mm

E = 250 kV/mm

Distance (um)

0.00 100 200 300 400 500

E (

kV

/mm

)

0.0

0200

400

600

(a) (b)

Fig. 3.6. Electric field intensity in the insulation materials of LVEP structure when the applied voltage

on the cathode is 13.5 kV. (a) Along the x direction (lateral direction) line AB in the polyimide. (b)

Along the y direction (vertical direction) line CD in the embedded insulation material.

A B C D

- 27 -

TABLE V

PARAMETERS OF THE LVEP#2 STRUCTURE STUDY

Nominal

value

Swept values Experimental

value

Polyimide thickness D (µm) 100 100-500 100

Dielectric constant of Polyimide εr 3 1-4 3

Dielectric constant of embedded insulation material εr’ 4 1-4 4

(a)

(b)

Fig. 3.7. Simulation model and result of LVEP #2 structure in MEDICI. (a) Dimensions and materials

of the structure. (b) Distribution of equipotential lines.

Anode

Cathode

10 µm

y

x

500 µm

1000 µm

1100 µm

Polyimide

SiC

Embedded

insulation

material Ceramic

100 µm

115 µm

508 µm

0

200

400

0.00 0.20 0.40 0.60 0.80 1.00

Distance

(µm)

Distance (mm)

Upper corner

Lower corner

A B

C

D

- 28 -

The first parameter studied is the thickness of the polyimide layer, D, as labeled in Fig.

3.10. Since the electric field is related to the thickness of the structure, increasing the

thickness will help to reduce the electric field intensity. The polyimide layer is thinner

than the ceramic, which leads most of the equipotential lines to bend down at the upper

corner of the device. The highest electric field in the polyimide is compared with

different thickness, as shown in Fig. 3.11. With the increasing of the thickness, more

equipotential lines distribute in the polyimide, which leads the peak electric field

intensity to reduce. This can be seen from the comparison shown in Fig. 3.12. When the

thickness of the polyimide is comparable to the thickness of the ceramic, further

0

100

200

300

400

500

600

SiC Polyimide (upper

corner)

Embedded

insulation material

(upper corner)

Embedded

insulation material

(lower corner)

Ceramic

E (k

V/m

m)

Dielectric strength LVEP LVEP #2

10x

4x

5x

24x

0

100

200

300

400

500

600


corner)

Embedded

insulation material

(upper corner)

Embedded

insulation material

(lower corner)

Ceramic

E (k

V/m

m)

Dielectric strength LVEP LVEP #2

10x

4x

5x

24x

Fig. 3.9. Comparison of the maximum electric field intensity between two LVEP structures.

E (

kV

/mm

)

050

10

015

020

02

50

0.20 0.40 0.60 0.80 1.00

Distance (mm)

E = 250 kV/mm

JTE3

JTE2

JTE1E (

kV

/mm

)

050

10

015

020

02

50

0.20 0.40 0.60 0.80 1.00

Distance (mm)

E = 250 kV/mm

JTE3

JTE2

JTE1 E (

kV

/mm

)

050

20

040

060

00

100 200 300 400 500

Distance (um)

E = 600 kV/mm

E = 100 kV/mm

(a) (b)

Fig. 3.8. Electric field intensity in the insulation materials of LVEP #2 structure when the applied

voltage on the cathode is 13.5 kV. (a) Along the x direction (lateral direction) line AB in the polyimide.

(b) Along the y direction (vertical direction) line CD in the embedded insulation material.

A B C D

- 29 -

increasing cannot help to reduce the field intensity very much. Thus, increasing the

thickness of the polyimide doesn’t convert the LVEP package to a HVEP package.

The second parameter studied is the dielectric constant of the polyimide. The influence

of this parameter is shown in Fig. 3.13. From the schematic of the structure, it can be that

the polyimide layer is in series with the embedded insulation material. Thus, when the

dielectric constant of the polyimide increases, more voltage drops on the embedded

insulation material, which means more equipotential lines bend down and cross the area

of the material and leads to higher electric field intensity at the upper corner of the

0

50

100

150

200

250

300

350

0 200 400 600D (um)

E (

kV

/mm

)

0

100

200

300

400

500

600

0 200 400 600D (um)

E (

kV

/mm

)

Upper corner Lower corner

(a) (b)

Fig. 3.11. Variation of maximum electric field intensity with the thickness of polyimide. (a) Inside the

polyimide at the upper corner. (b) Inside the embedded insulation material at the upper and lower

corner.

508 µm

L

D

10 µm

1000 µm

1100 µm

115.5 µm

x

y

Polyimide

Embedded insulation material

SiC

Ceramic

εεεεr

Anode

Cathode

D

εεεεr’

Fig. 3.10. Parameters in the LVEP#2 structure study.

- 30 -

device. This can be observed from Fig. 3.14. As the previous study showed, the

maximum electric field intensity inside the polyimide is at the upper corner of the device.

Thus, the maximum electric field intensity in the polyimide increases with the dielectric

constant of the polyimide.

When the dielectric constant of the embedded insulation material increases, the

variation of the maximum electric field intensity is the opposite because of the same

mechanism. This can be seen from the simulation results in Fig. 3.15 and Fig. 3.16.

From these two simulations of material property influence, it is observed that the

dielectric constant of these two insulation material should match with their thickness. In

Fig. 3.14 (a), the dielectric constant of the polyimide and the embedded insulation

material is 3 and 4 respectively, there are around 14 equipotential lines distributed in the

polyimide area which means the voltage drop is around 3.8 kV. In Fig. 3.14 (b), the

dielectric constant of the polyimide and the embedded insulation material is 1 and 4

respectively, there are around 26 equipotential lines distributed in the polyimide area

which means the voltage drop is around 7 kV. In this way, the thin polyimide layer with

low dielectric constant could have the same voltage distribution as the thick embedded

insulation material with high dielectric constant. Thus the voltage can distributes in the

whole insulation area evenly, which leads to a lower electric field intensity. However,

this material selection is so critically dependent on the development of the material.

The parametric study shows that thickening the polyimide layer cannot help to convert

the LVEP structure to a HVEP structure. Change of material according to the physical

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

200

400

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

200

400

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

200

400

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

40

0

20

0

-20

0

-40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

40

0

20

0

-20

0

-40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

40

0

20

0

-20

0

-40

0

(a) (b)

Fig. 3.12. Comparison of the equipotential lines distribution between two different thicknesses of

polyimide. (a) D = 100µm. (b) D = 500 µm.

- 31 -

dimension helps to reduce the high electric filed intensity at corners of the device.

However, this is determined by the availability of different materials. Thus, new

structures have to be developed to block this high voltage.

3.4. Medium-Voltage Embedded Power (MVEP) structure

From the observation of the equipotential line distribution in two LVEP structures, it

can be seen that the presence of the metallization on the bottom of LVEP #2 structure

changes the bending direction of the equipotential lines and thus avoids the high electric

field intensity at the lower corner. The bending down of the potential lines makes the

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(µ

m)

0

20

0

4

00

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(µ

m)

0

20

0

4

00

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

20

0

400

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

20

0

400

(a) (b)

Fig. 3.14. Comparison of the equipotential lines distribution between two different dielectric constant of

polyimide. (a) εr = 3. (b) εr = 1.

0

50

100

150

200

250

300

350

0 2 4 6

Dielectric constant of polyimide

E (kV

/mm

)

0

100

200

300

400

500

600

700

800

900

0 2 4 6Dielectric constant of polyimide

E (

kV

/mm

)

Upper corner) Lower corner

(a) (b)

Fig. 3.13. Variation of maximum electric field intensity with the dielectric constant of polyimide. (a)

Inside the polyimide. (b) Inside the embedded insulation material.

- 32 -

high electric field intensity at the upper corner of the device, thus a structure that has less

potential lines bending down could help to relieve the high electric field intensity.

A Medium-Voltage Embedded Power (MVEP) structure is proposed and shown in Fig.

3.17 (a). The thickness of the polyimide on the top is increased to 400 µm based on the

parametric study of LVEP #2. In this structure, the bottom of the package is metalized

and connected to the cathode of the device. This metallization is also extended to the top

of the package through a via in the ceramic carrier. Thus, the metallization connected to

the anode and cathode is both on the top of the structure. The extended metallization

connected to the cathode alleviates the bending of equipotential lines at the upper corner

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(µ

m)

0

20

0

40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(µ

m)

0

20

0

40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(µ

m)

0

20

0

40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

200

40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

200

40

0

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

200

40

0

(a) (b)


embedded insulation material. (a) εr’ = 4. (b) εr’ = 15.

0

50

100

150

200

250

300

0 5 10 15 20Dielectric constant of embedded

insulation material

E (

kV

/mm

)

0

100

200

300

400

500

600

700

0 5 10 15 20Dielectric constant of embedded

insulation material

E (

kV

/mm

)

Upper corner) Lower corner

(a) (b)

Fig. 3.15. Variation of maximum electric field intensity with the dielectric constant of embedded insulation

material. (a) Inside the polyimide. (b) Inside the embedded insulation material.

- 33 -

of the device, as given in Fig. 3.17 (b), which means the crowding of the electric field is

reduced too. This can be seen from Fig. 3.18, which is the electric field intensity drawing

in the polyimide and the embedded insulation material respectively. The maximum

electric field intensity in these two insulation materials at the upper corner of the device

is reduced to 1/4 – 1/3 of the value of the LVEP structure, and the maximum electric field

intensity at the lower corner of the device in epoxy is more than 10 times less than in the

original structure. Fig. 3.19 shows the comparison.

In the MVEP structure, the voltage between two pieces of top metalization is the

applied voltage. This requires that the insulation material between these two pieces of

metalization can stand the applied voltage. Thus, the minimum distance in the design in

between of two pieces metalization has to be greater than the applied voltage divided by

the dielectric strength of the insulation material, which is around 300 µm in the

simulation model.

A parametric study is performed as well to learn the influence of the material properties

and the dimensions. Table VI gives the parameters labeled in Fig. 3.20 and the values.

The first parameter is the thickness of the polyimide, as shown Fig. 3.21. From the

simulation results, it can be seen that with the increasing of the thickness, the highest

electric field decreases, which is the same as the LVEP #2. This mechanism can be seen

from Fig. 3.22. However, there is a phenomenon of saturation when the thickness

reaches certain value, which means further increasing of the thickness cannot help to the

reduction of the field crowding. The other parameter studied is the dielectric constant of

the polyimide, as shown in Fig. 3.23. The higher the dielectric constant is, the higher is

the maximum electric field intensity. This trend is the same as it in the LVEP #2

structure. This is also indicated by that more potential lines bend down to the area of the

embedded insulation material as the dielectric constant increases, as shown in Fig. 3.24.

It can be also found that the variation of the dielectric constant in this MVEP structure

TABLE VI

PARAMETERS IN THE MVEP STRUCTURE STUDY

Nominal value Swept values

Polyimide thickness D (µm) 400 100-500

Dielectric constant of Polyimide εr 3 4-8

- 34 -

doesn’t influence the electric field intensity at the lower corner of the device inside the

embedded insulation material with 500 µm thick polyimide.

The influence of these two parameters to the LVEP #2 and MVEP can be explained

using a simplified circuit. Since the polyimide and the embedded insulation material are

in series with each other, as the area in the dashed-line rectangle area in Fig. 3.25 (a),

these two can be simplified to two parallel plate capacitors Cp and Ce in series, as shown

in Fig. 3.25 (b). The capacitance is calculated from the dielectric constant, area and the

thickness in (3.1). The voltage drop on two series connected capacitors is shown in (3.2)

(a)

(b)

Fig. 3.17. Simulation model and result MVEP structure in MEDICI. (a) Dimensions and materials of


Anode

Polyimide

y

x

Embedded

insulation

material

Ceramic

400 µm

115 µm

508 µm

500 µm 1000 µm

1100 µm

10 µm

0

-200

-400

200

400

0.00 0.20 0.40 0.60 0.80 1.00

Distance (mm)

Distance

(µm)

SiC

A B

D

C

- 35 -

and (3.3). It is desired that the voltage drop on the capacitor made of embedded

insulation material is as low as possible, which means less equipotential lines bend down

into this material. From (3.3), this can be realized by decreasing the capacitance of the

capacitor made of polyimide Cp, which can be implemented by either decreasing the

dielectric constant or increasing the thickness. On the other hand, increasing the

dielectric constant of the embedded insulation material can do the same job. Thus, when

the thickness of the materials is fixed, it is desired to decrease the ratio between the

dielectric constant of the polyimide and the embedded insulation material.

D

AC rε= (3.1)

ep

ep

CC

CV

+= (3.2)

ep

p

eCC

CV

+= (3.3)

E = 90 kV/mmJTE1

JTE2

JTE3

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

E (

kV

/mm

)

025

50

75

10

01

25

E = 90 kV/mmJTE1

JTE2

JTE3

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

E (

kV

/mm

)

025

50

75

10

01

25

E = 150 kV/mm

E = 20 kV/mm

Distance (mm)0.00 100 200 300 400 500

E (

kV

/mm

)

05

010

01

50

E = 150 kV/mm

E = 20 kV/mm

Distance (mm)0.00 100 200 300 400 500

E (

kV

/mm

)

05

010

01

50

(a) (b)

Fig. 3.18. Electric field intensity in the insulation materials of MVEP structure. (a) In the polyimide. (b)

In the embedded insulation material.

Cathode

- 36 -

Anode

Cathodey

500 µm1000 µm

1100 µm

D

115.5 µm

x

10 µm

SiC

CeramicEmbedded insulation material

Polyimide εεεεr

Fig. 3.20. Parameters in the MVEP structure study.

0

50

100

150

200

250

300

350

0 200 400 600D (um)

E (k

V/m

m)

0

100

200

300

400

500

600

0 100 200 300 400 500 600

D (um)

E (

kV

/mm

)


(a) (b)

Fig. 3.21. Variation of maximum electric field intensity with the thickness of polyimide. (a) Inside the

polyimide at the upper corner. (b) Inside the embedded insulation material.

0

100

200

300

400

500

600


corner)

Embedded

insulation

material (upper

corner)

Embedded

insulation

material (lower

corner)

Ceramic

E (

kV

/mm

)

Dielectric strength LVEP LVEP #2 MVEP

5x

2x6x

10x

4x

0.8x

24x

Fig. 3.19. Comparison of the maximum electric field intensity between two LVEP structures and the

MVEP structure.

- 37 -

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

400

20

0

-200

-40

0

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

400

20

0

-200

-40

0

02

00

40

0

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(u

m)

Distance (mm)

20

04

00

(a) (b)


polyimide. (a) εr = 4. (b) εr = 8.

020

04

00

0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

um

)

Distance (mm) Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

400

200

-20

0

-400

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

400

200

-20

0

-400

(a) (b)

Fig. 3.22. Comparison of the equipotential lines distribution between two different thicknesses of the

polyimide. (a) D = 100 µm. (b) D = 500 µm.

80

90

100

110

120

130

140

150

160

170

3 5 7 9

Dielectric constand of polyimide

E (

kV

/mm

)

0

50

100

150

200

250

300

350

400

450

3 5 7 9

Dielectric constant of polyimide

E (

kV

/mm

)


(a) (b)

Fig. 3.23. Variation of maximum electric field intensity with the dielectric constant of polyimide. (a)

Inside the polyimide at the upper corner. (b) Inside the embedded insulation material.

- 38 -

3.5. Development of High-Voltage Embedded Power (HVEP)

structure

From the simulations in the previous section, it is known that the equipotential lines

bend down at the upper corner of the device because of the internal structure of the

device. This leads to the high electric field intensity at the corners of the device.

Although the MVEP structure has greatly improved the blocking capability of the

package, it is still cannot stand the voltage as high as 10 kV because the hotspot at the

upper corner of the device still exists.

To eliminate this high electric field crowding at the upper corner, one good method is

to prevent the equipotential lines from entering the area of the embedded insulation

material. A piece of metalization can be inserted to the device package to reshape the

electric field distribution. This is the idea of high-voltage embedded power (HVEP)

structure, as shown in Fig. 3.26 (a). Compared to the MVEP structure, the bottom

cathode metallization of the package is extended to the surface of the ceramic carrier and

the embedded insulation material, instead of to the top of the whole package. It has the

same potential as the cathode of the device, which is also the potential of the body of the

device in blocking mode. This inserted metal layer prevents the equipotential lines from

entering the embedded insulation material, and lets the entire voltage drop on the

0 V

Anode

Cathode y

500 µm1000 µm

1100 µm

D

115.5 µm

x

10 µm

SiC

14 kV CeramicEmbedded insulation

material

Polyimide εεεεr

εεεεr’

D’

Anode

Cathode y

500 µm1000 µm

1100 µm

D

115.5 µm

x

10 µm

SiC


material

Polyimide εεεεr

εεεεr’

D’

Anode

Cathode y

500 µm1000 µm

1100 µm

D

115.5 µm

x

10 µm

SiC


material

Polyimideεεεεr

εεεεr’

D’

Cp

Ce

(a) (b)

Fig. 3.25. Equivalent circuit model of LVEP#2. (a) Structure of LVEP#2. (b) Series capacitor model of

a small area in the LVEP#2 structure.

- 39 -

polyimide layer, which can be seen in Fig. 3.26 (b). This inserted metal layer is called

fileld-shaping metal layer.

(a)

(b)

Fig. 3.26. Simulation model and result of HVEP structure in MEDICI. (a) Dimensions and materials of


Anode

Cathode

y

x

10 µm 500 µm 1000 µm

1100 µm

508 µm

115 µm

400 µm Polyimide

Embedded

insulation

material

Ceramic

0

200

400

-200

-400

0.00 0.20 0.40 0.60 0.80 1.00

Distance

(µm)

Distance (mm)

5 µm

- 40 -

It can be observed that the electric intensity at the area adjacent to the JTEs in the

device is high. This high electric field intensity cannot be reduced by improving the

structure geometry because it depends on the internal structure of the device, which is

determined by the device manufacturers, and it is taken care by the passivation on the top

of the device from the manufacturers. Furthermore, since the field-shaping metal layer

prevents the equipotential lines from entering the embedded insulation material, even

with the presence of the voids in the embedded insulation material, it won’t degrade the

voltage rating of the package.

JTE3

JTE2

JTE1

E = 125 kV/mm

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

E (

kV

/mm

)

02

55

07

510

01

25

JTE3

JTE2

JTE1

E = 125 kV/mm

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

E (

kV

/mm

)

02

55

07

510

01

25

E (

kV

/mm

)0

12

30

100 200 300 400 500Distance (um)

E = 3.2 kV/mm

E = 0.2 kV/mm

(a) (b)

Fig. 3.27. Electric field intensity in the insulation materials of HVEP structure. (a) In the polyimide. (b)

In the embedded insulation material.

0

100

200

300

400

500

600

SiC Polyimide (upper corner)

Embedded insulation

material (upper corner)

Ceramic

E (

kV

/mm

)

Dielectric strength LVEP LVEP #2 MVEP HVEP

5x

24x

2x

6x

10x

4x

0.8x

0.9x 0.1x


(lower corner)

Fig. 3.28. Comparison of the maximum electric field intensity of different structures.

- 41 -

3.6. Geometry impact on HVEP structure

There are several geometric parameters need to be determined in the design of a HVEP

structure. These parameters include the thickness of the polyimide – D, the position of

the inserted metal layer – t, the width of the field-shaping metal layer – w, and the angle

of the edge of the polyimide - θ, as shown in Fig. 3.29. Table VII gives the parameters

shown in Fig. 3.29 and the values

From the simulation results in Fig. 3.30, with the increasing of the thickness of the

polyimide, the maximum electric field at the upper corner of the device in the polyimide

layer decreases. It influences the electric field intensity in the area in which the

equipotential lines are uniform as well, as shown in Fig. 3.26.

TABLE VII

PARAMETERS IN THE HVEP STRUCTURE STUDY

Nominal value Swept values

Polyimide thickness D (µm) 400 400 - 1000

Field-shaping metal layer position t (µm) 0 0 - 200

Field-shaping layer width (µm) 0 -400 - 500

Polyimide edge angle θ (°) 90 30 - 90

Anode

Cathodey

500 µm1000 µm

1100 µm

D

115.5 µm

x

10 µm

SiC

CeramicEmbedded insulation material

Polyimide

t

w

θθθθ

flat area

Fig. 3.29. Parameters in the HVEP structure study.

- 42 -

When the field-shaping metal layer is extended from the cathode metallization on the

bottom of the package, its voltage is tied to 0 V. The impact of the variation of the

position of this layer on the maximum electric field intensity at the upper corner of the

device in the polyimide layer is shown in Fig. 3.31. From the simulation result shown in

Fig. 3.31 (b), the highest electric field intensity happens at the edge of the inserted metal

layer instead of the corner of the device. Furthermore, besides this value exceeds the

dielectric strength of the polyimide with the movement of the metal layer, the maximum

electric field intensity at the device corner in the embedded insulation material is

increases 3 times.

0

10

20

30

40

50

60

70

80

0 50 100 150 200t (um)

E (

kV

/mm

)

Embedded insulation material Polyimide Plat area

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

40

0

20

0

-200

-400

(a) (b)

Fig. 3.31. Variation of maximum electric field intensity with the position of the inserted metal layer. (a)

Maximum electric field intensity in two insulation materials. (b) Distribution of Equipotential lines at t =

200µm.

0

10

20

30

40

50

400 600 800 1000D (um)

E (

kV/m

m)

Polyimide Flat area

Fig. 3.30. Variation of maximum electric field intensity at the corner of the device with the thickness of the

polyimide.

- 43 -

The increased electric field intensity at the edge of the field-shaping metal layer can be

alleviated by thicken the polyimide layer. When t is 80 µm and D is 1000 µm, the

maximum electric field intensity at the edge of the inserted metal drops to 40 kV/mm.

However, this measure cannot help to reduce the maximum electric field intensity in the

embedded insulation material which is still 2 times higher than the maximum electric

field intensity when t is equal to 0.

Since the inserted metal layer is connected to the cathode metallization, its voltage is

13.5 kV. Actually the voltage applied to this metal layer can be different values. Fig.

3.32 shows the equipotential line distribution of two cases. As shown in Fig. 3.32 (b), the

equipotential lines bend down into the embedded insulation material, and the high

electric field intensity occurs at the upper corner. Fig. 3.33 shows the comparison of the

simulation results of different combination of the applied voltage and the position of the

field-shaping metal layer. When the field-shaping metal layer is tied to higher voltages,

the equipotential lines bend down into the embedded insulation material, which results

high electric intensity at the corner of the device inside both the polyimide and the

embedded insulation material. Thus, the best position of this metal layer is at the same

surface as the device and its voltage is tied to the cathode voltage.

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

400

200

-20

0 -4

00

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce

(µ

m)

0

40

0

20

0

-20

0

-40

0

0 V

13.5 kV

5 kV

(a) (b)

Fig. 3.32. Distribution of equipotential lines with different combination of the position and the voltage of

the inserted metal layer. (a) t = 0µm and V = 0 V. (b) t = 200 µm and V = 5 kV.

- 44 -

The width of the -metal layer has great impact on the electric field distribution as well.

The definition of this parameter is the distance between the edges of the field-shaping

metal layer and the device. The origin is at the edge of the device. As shown in Fig.

3.34, there is an optimal point where the field-shaping metal is long enough to reach the

edge of the device which means w equals to 0. When the metal layer is too short which

means w is greater than 0, as can be seen from Fig. 3.35 (a), equipotential lines bend

down and the metal layer lose its shield effect. When the metal layer is too long which

means w is less than 0, as shown in Fig. 3.35 (b), it blocks the equipotential lines from

entering the embedded insulation material extremely well. However, the near-evenly

distributed equipotential lines on the surface of the device have to bend to reach the edge

of the metal layer, which creates high electric field concentration at the edge of the metal

layer and the surface of the device. Thus, the optimal width of the field-shaping metal

layer is realized when the edge of the field-shaping metal layer touches the edge of the

device, which means w equals to 0.

Furthermore, when the field-shaping metal layer slightly covers the edge of the device,

the maximum electric field intensity in the polyimide doesn’t increase dramatically, as

shown in Fig. 3.35 (a). Thus, it is preferred that there is little overlap between the field-

shaping metal layer and the device edge to that the field-shaping metal layer is apart from

the device edge.

0

200

400

600

800

1000

1200

1400

1600

1800

2000

Polyimide (upper corner) Embedded insulation material

(upper corner)


(lower corner)

E (

kV

/mm

)

V = 13.5 kV, t = 0 um V = 13.5 kV, t = 100 um V = 5 kV, t = 0 um

V = 5 kV, t = 200 um V = 10kV, t = 100 um V = 10 kV, t = 200 um

Fig. 3.33. Variation of maximum electric field intensity with different combination the position of the

inserted metal layer and its voltage

- 45 -

In the previous simulations, the angle of the polyimide edge θ shown in Fig. 3.29 is

90°. Practically, this angle is usually less than 90° because the overflow of the

polyimide. Thus, the influence of different angles is simulated. In Fig. 3.36, the

maximum electric field intensity along a horizontal line at y = -100 µm is compared

among different angles. As it can be seen from Fig. 3.37, the equipotential lines are

compressed at the edge of the polyimide because of the small angle there. Thus, the

electric field at the same position in the area near the edge of the polyimide is higher

when the angle is small.

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

400

200

-200

-400

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

400

20

0

-200

-400

(a) (b)

Fig. 3.35. Distribution of equipotential lines with different width of the inserted metal layer. (a) w =

500µm. (b) w = -400 µm.

0

200

400

600

800

1000

-400 -200 0 200 400

w (um)

E (

kV

/mm

)

0

50

100

150

200

250

-400 -200 0 200 400

w (um)

E (

kV

/mm

)


(a) (b)

Fig. 3.34. Variation of maximum electric field intensity with the width of the inserted metal layer. (a)

Maximum electric field intensity in the polyimide. (b) Maximum electric field intensity in the embedded

insulation material.

- 46 -

Although this angle is inevitable in the process, it can be moved to avoid the high field

crowding, as shown in Fig. 3.38 (a). Assume the angle of the polyimide edge is 30°, by

increasing its height, h, the maximum electric field of the horizontal line at y = -100 µm

is reduced. Thus, in reality, a “dam” can be built to lift the sharp angle of the polyimide

edge to avoid increasing the electric field intensity in that area.

Since the field-shaping metal layer and the top metallization are in parallel, an extra

capacitor in the device package is introduced. The capacitance can be estimated by using

(3.1).

AAD

AC r 66

10400

1085.836

12

=×

××==

−

−

ε nF

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tance (

µm

)

0

400

20

0

-200

-400

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

40

0

20

0

-20

0

-40

0

(a) (b)

Fig. 3.37. Distribution of equipotential lines with different angle of the polyimide. (a) θ = 30°. (b) θ =

90°.

30

35

40

45

50

55

60

65

70

20 40 60 80 100

Theta (deg)

E (

kV

/mm

)

Fig. 3.36. Variation of the maximum electric field intensity along the horizontal line at y = -100 µm with

the angle of the polyimide .

- 47 -

Assume that the area is usually less than 100 mm2, the capacitance is less than 10 fF,

which is negligible.

3.7. Summary

In this Chapter, two LVEP structures are revisited in MEDICI with a 10 kV SiC diode

embedded in the structures. The MEDICI simulations show that the double-sided

metallization can help to reduce the high electric field intensity at the lower corner of the

device inside the embedded insulation material. Some parameters in the LVEP #2

structure are studied to obtain their influences on the maximum electric field intensity.

The higher thickness of the polyimide layer can decrease the maximum electric field at

the corners of the device in two insulation material. However, when the thickness of the

polyimide is comparable to the thickness of the ceramic, further increasing cannot help to

reduce the field intensity very much. From the material property point of view, low

dielectric constant of the polyimide is desired.

Based on the simulations of the LVEP structures, a MVEP structure is proposed. The

cathode metallization is extended to the top of the structure. The maximum electric field

intensity at the corners of the device inside two insulation material is reduced greatly.

However, at a voltage of 13.5 kV, these values are still higher than their dielectric

strength. Some parameters in the structure are investigated as well. It is shown that the

Distance (mm) 0.00 0.20 0.40 0.60 0.80 1.00

Dis

tan

ce (

µm

)

0

400

200

-200

-400

h

30°°°°

30

35

40

45

50

55

60

0 50 100 150 200

h (um)

E (

kV

/mm

)

(a) (b)

Fig. 3.38. Influence of the height of the angle of the polyimide when θ = 30°. (a) Structure. (b) Electric

field intensity variation with different values of the height.

- 48 -

influence of the thickness and the dielectric constant of the polyimide is the same as that

in the LVEP #2 structure. This can be explained by simplifying the structure to a circuit

that consists of two capacitors in series.

A HVEP structure is proposed finally. A thin layer of metal is field-shaping to the

middle of the structure and it is tied to the cathode metallization. This field-shaping

metal layer prevents the equipotential lines from entering the embedded insulation

material. Thus, the maximum electric field at the corners inside the two insulation

materials is reduced to the value below their dielectric strength. Furthermore, since there

is no electric field in the embedded insulation material, even with the presence of the

voids in the embedded insulation material, the voltage rating of the package won’t be

degraded.

The HVEP structure design involves several geometry parameters. They are the

thickness of the polyimide – D, the position of the field-shaping metal layer – t, the

extension length of the field-shaping metal layer – w, and the angle of the edge of the

polyimide - θ. The thickness of the polyimide is proportional to its dielectric strength

and the applied voltage in the flat area. The best position for the field-shaping metal

layer is on the same surface as the device, and the optimal voltage applied this metal

layer is the same as the cathode. Simulation also indicates that, the optimal width of the

field-shaping metal layer is that the edge of the field-shaping metal layer touches the edge

of the device. It can be found that the angle of polyimide edge is less than 90°

practically, and this smaller angle could influence the package voltage rating greatly.

Although this angle is unavoidable, it can be solved by the application of a thick “dam”.

It is preferred that the angle of the polyimide would be 90° or even larger with the aid of

this “dam”.

The meshing method in MEDICI is manual meshing. The number of meshes

influences the accuracy of simulation results. However, since the critical areas are

known in the structures, the meshing in those areas is much denser than other non-critical

areas. Thus, the accuracy is insured by this way.

- 49 -

Chapter 4: Design Guidelines for the HVEP package and

Fabrication Process of a HVEP package

The main task of engineers is to apply their scientific and engineering knowledge to the

solution of technical problems, and then to optimize those solutions within the

requirements and constraints set by material, technological, economic, legal,

environmental and human-related considerations. An engineering design process is a

process used by engineers to help develop products. The engineering design includes

many aspects and wide-range activities. Both engineer’s scientific knowledge and

experience play important roles in the engineering design. Guidelines are useful in the

old product re-design and the new product design. The idea behind the design guidelines

is that there is a fundamental set of the principles that determines good design practice.

These design guidelines can be derived from the knowledge when a set of judgments

based on the design rules can yield correct solutions to all problems.

In this Chapter, the general engineering design practice is reviewed first. Then the

practice of the engineering design of the HVEP package is introduced. Next, the design

guidelines for the HVEP package are derived. Based on the design guidelines, a HVEP

package for a 2 kV SiC diode is developed. After the package is designed, it fabrication

process is designed based on the device dimensions, materials, and the optimal rules in

the design guidelines, and the detailed the fabrication process is shown. Finally, the

package is tested at the rated voltage and the experimental results are presented.

4.1. Design guidelines for the HVEP package

4.1.1. Introduction to engineering design

The engineering design is defined as the process of devising a system, component or

process to meet desired needs. It is a decision-making process (often iterative), in which

the basic sciences, mathematics, and engineering sciences are applied to convert

resources optimally to meet a stated objective. Among the fundamental elements of the

- 50 -

design process are the establishment of objectives and criteria, synthesis, analysis,

construction, testing, and evaluation. The engineering design process involves ten steps.

They are: (1) identifying a need; (2) defining the problem; (3) conducting research; (4)

narrowing the research; (5) analyzing set criteria; (6) finding alternative solutions; (7)

analyzing possible solutions; (8) making a decision; (9) presenting the product; and (10)

communicating and selling the product [44].

Modeling is a technique used by the engineer to define a real situation for generating

quantitative solutions. Relevant approximations in the modeling are critical for obtaining

the best solution to the engineering problem. Thus, the engineer must have a clear

understanding of the physical basis of the real situation. Usually, more than one solution

exists, the best one is generally found based on the engineer’s scientific knowledge and

experience. An evaluation of the solutions to find the optimal one is necessary.

4.1.2. Design practice in the HVEP package

In [45], the design practice in a thermal design is introduced. Similarly, in the electrical

design of the high-voltage packaging, the first task is to identify the objectives of the

design, which is to keep the maximum electric field intensity of the insulation material at

or below its dielectric strength. Three general ways of analyzing the design situation

include analytical analysis, mathematical modeling, and experiments. Some common

solutions to achieve this objective include justified selection of high dielectric strength

material and the manipulation of the structure. Optimization of the design generally

concentrates on selectively choosing the best values of design parameters that optimize

performance reliability at lowest cost. Finally, the best design parameter quantity will be

chosen as the output of the design for prototype preparation.

The design process of a HVEP package can be illustrated in Fig. 4.1. The input to the

design includes the device dimensions, ratings, the electrical schematics, the packaging

material properties and dimensions, and the requirements from process. The electric field

modeling can be performed with analytical analysis or mathematical modeling. Since the

structure of the device and the package is complex, the mathematical modeling has to

simplify the structure and approximate the real case. Therefore, experimental validation

is always required to validate the accuracy of the model if mathematical modeling is used

- 51 -

as a tool for the electric field analysis. The numerical modeling is another method to

describe the behavior of the package. Compared to the mathematical method, it can

analyze much more complicated situation. Thus the numerical method is often used to

mathematically describe and obtain information on the electric field distribution. After

the parametric study, an optimized design is obtained. With the consideration of the

concurrent engineering design process in which the electrical, thermal, and process

constraints are performed in parallel, a good product design is achieved.

4.1.3. Design guidelines for the HVEP package

A design guideline is defined by a standard or principle by which to make a judgement

or determine a policy or course of action. Design guidelines can be from theory,

empirics, or practices. The role of the design guidelines is to provide some insight to the

design parameters during the design process. Although the engineer may be faced with

the available choices for the design, the key point in using the design guidelines is to

recognize the available information as well as the known constraints. By understanding

the behaviour of the electric field, the engineer can choose appropriate materials and

geometries to optimize the design.

The purpose of the design guidelines is to provide more suggestive and general rules in

determining and predicting the electric field distribution in the HVEP package. From the

Device information

Electrical layout

information

HVEP package design input

HVEP package modeling

Parametric studies

Design Optimization

Design Output

Check with Process

Constraints

Check with Electrical

constraints

Experimental Validation

Not Satisfied Satisfied

Satisfied

Not Satisfied

Fig. 4.1. Engineering design process of HVEP package.

- 52 -

simulations in Chapter 4, the guidelines for the design of HVEP package can be

summarized as the followings.

(1) Position of the field-shaping metal layer.

The position of field-shaping metal layer influences the electric field intensity at the

corners of the device in both insulation materials. When the field-shaping metal layer

moves up, it loses its effectiveness of shielding the embedded insulation material. Thus,

the electric field intensity increases in both insulation materials at the corners of the

device.

When the voltage applied to this layer is 0 V, the position of the field-shaping metal

layer should be as close as possible to the surface of the device. The best position is on

the same surface as the device.

(2) Width of the field-shaping metal layer.

When the field-shaping metal layer is nonadjacent to the edge of the device, the electric

field intensity at the device corners increases with the increasing of the distance between

the field-shaping metal layer and the edge of the device. In this situation, the metal layer

cannot prevent the equipotential lines from bending down into the embedded insulation

material. When the field-shaping metal layer overlaps the device, it blocks the

equipotential lines from bending down into embedded insulation material completely.

However, high electric field concentrates at the edge of this layer due to the bending of

equipotential lines, and the maximum electric field intensity increases dramatically with

the increasing of the overlapping length.

When the field-shaping metal layer touches the edge of the device, it gives the best

electric field distribution. It is more favourable that the metal layer overlaps little of the

device than that it is nonadjacent to the edge of the device.

(3) Voltage applied to the field-shaping metal layer

Different combination of applied voltage and position of the field-shaping metal layer

gives different electric field intensity at the corners of the device in the two insulation

materials. The higher applied voltage is, the less shielding effect is the field-shaping

metal layer.

The best applied voltage is the same as the cathode voltage.

(4) Thickness of the polyimide layer

- 53 -

The maximum electric field intensity at the upper corner in the polyimide decreases

with the increasing of the thickness. The electric field between the field-shaping metal

layer and the top metallization is nearly uniform. The minimum thickness of the

polyimide can be estimated by ratio between the rated voltage and the thickness.

Simulation is necessary for more accurate results.

(5) Angle of the polyimide edge

The small angle of the polyimide edge introduces higher electric field intensity in the

material. It is desired to keep that angle being 90°. This can be controlled by adding a

“dam” in the structure. When the “dam” is high enough, small angle doesn’t influence

the electric field too much. Thus, a “dam is needed in the package and its thickness is the

same as the polyimide layer.

The best position and the best width of the field-shaping metal layer are called optimal

rule.

4.1.4. A design example

The designed guideline in the previous section can be applied to a single device

package or a multi-device package. A design example is given in Fig. 4.2, which is the

package of an IGBT and its anti-parallel diode.

(1) From the input of the design, for example, the dimensions of the devices and

materials, the electrical rating and properties, and the electrical schematics, the physical

layout is designed, as shown in Fig. 4.2 (a).

(2) The layout of the field-shaping metallization is designed. From the design

guidelines above, the field-shaping metallization should be on the same surface as the

device, touches the edges of both devices and be tied to the bottom metallization, as

shown in Fig. 4.2 (b). Here the connection of the field-shaping metallization and the

bottom metallization is designed to be realized through a via.

(3) The polyimide layer is designed. From the design guideline, the minimum

thickness of the polyimide can be estimated. Simulation is necessary for more accurate

results. Dams for the device contacts are added to form 90° polyimide angles, as shown

in Fig. 4.2 (c).

- 54 -

(4) The layout of the top metallization is designed. With the consideration of the

electrical schematics, the top metallization and the arrangement of the components are

designed, as shown in Fig. 4.2 (d).

(5) After all the requirements and constraints are checked, some of the designed layouts

may be revised.

Ceramic

Diode IGBT


AnodeCollector Gate

ViaJTEs

(a)

Ceramic

Diode IGBT

Metallization

Field-shaping Metal layer

(b)

Ceramic

Diode IGBT

Polyimide

Dam for anode Dam for collector Dam for gate

(c)

Ceramic

Diode IGBT

Polyimide

Lead/Pin Lead/PinComponents

(d)

Fig. 4.2. A design example. (a) Physical layout design. (b) Inserted metal layer design. (c) Polyimide

layer design. (d) Top metallization design.

- 55 -

4.2. Fabrication process of a HVEP package

From the design guidelines for the HVEP package, a package for a 2 kV SiC diode is

developed firstly. Then the designed package is fabricated and tested to validate the

design.

4.2.1. Devices and materials

The 2 kV SiC diode is from Cree Inc. Its picture and dimensions are shown in Fig. 4.3.

The thickness of this device is 381 µm (15 mil). The anode and the cathode metallization

is gold which is solderable. The JTEs are around the anode contact and covered by

passivation from the manufacturer.

The polyimide is Epo-Tek 600 from Epoxy Technology Inc. It is a one-component

polyimide system. The dielectric constant is 2.4, and its dielectric strength is 17 kV/mm.

This material needs to be cured at 150°C for 1 hour and then at 275°C for 1 hour [46].

The thickness of the polyimide is determined by the simulation. The device in the

simulations is the same device as previous section. The results show that the maximum

electric field intensity at the upper corner is less than 17 kV/mm when the thickness is

150 µm. Thus, the thickness of the polyimide layer is selected as 150 µm.

EP3HT from Master Bond Inc. is selected as the embedded insulation material. It is a

one-component, heat-curing epoxy adhesive/sealant. The ceramic carrier provides the

mechanical support to the device, and its thickness is 508 µm (20 mil). The metallization

is copper in the package.

3.5 mm

5 mm

1.5 mm

2.7 mm

Fig. 4.3. Picture and dimensions of a 2 kV SiC diode.

Anode

JTEs with

passivation on

the top

- 56 -

4.2.2. Design of the fabrication procedure

Although both the LVEP package and the HVEP package are based on the embedded

power technology, the HVEP package has more complicated structure than the LVEP

package. Therefore, the fabrication of the HVEP package needs to be re-designed.

The fabrication of the LVEP package is shown in Fig. 4.4. It includes 6 major steps.

First, the opening for the device is cut on the ceramic carrier by using a laser machine.

Second, the device is embedded in the ceramic and epoxy is dispensed around the device

to seal it in the ceramic. The surface of the device is aligned with the ceramic and the

epoxy on the top side. Third, the polyimide is patterned on the flat surface through

screen-printing. Fourth, thin layer of copper is deposited on the top surface by sputtering.

Fifth, the top metallization is thickened by electroplating for the electrical conduction.

Last, the unnecessary thin layer copper is etched away.

Besides all these steps, the fabrication of the HVEP package needs the deposition of the

double-sided metallization and the field-shaping metal layer, and the formation of the

“dam”. The designed fabrication procedure of the HVEP package is shown in Fig. 4.5.

The different steps between the LVEP package and the HVEP package are highlighted by

solid-line rectangle. The detailed fabrication steps are as followings.

(1) Layout design. The dimensions of the opening for the device are designed based on

the dimensions of the diode. The position of the via is determined by the mechanical

strength of the ceramic empirically, which requires at least 3 mm distance between

openings. Then the dimensions of the ceramic carrier is designed based on the opening

and the via. All the design drawings are done in CAD software.

(2) Ceramic cutting. A piece of ceramic is cut in this step by using the laser machine.

First, the design drawings are imported to the program that controls the laser machine.

Then parameters that control the power, repetitive rate, pulse width, and speed of the

laser are setup for cutting the ceramic. Finally, the laser is run by the program to

execute the command that cuts the opening and via in the design.

(3) Chip embedding. First, a piece of the Kapton tape is attached to one face of the

ceramic carrier right on the opening as the holder of the device. Second, the diode is

fitted into the opening with the anode adhered to the Kapton tape. Third, the EP3HT

- 57 -

material is dispensed to the space between the device and the ceramic by using a

dispenser, and it is cured at 160 °C for 10 minutes in an oven. Since the presence of the

field-shaping metal layer in the HVEP structure, the process control effort is greatly

reduced since the voids introduced in the EP3HT in this step are no longer a threat to the

package breakdown voltage.

(4) Shim soldering. First, the size of the copper shim is determined by the contact

dimensions of the device. Then a mask is designed to cover the size of the shim. Third, a

piece of copper is coated with photoresist. After 20 minutes soft bake at 80 °C, this piece

of copper is covered by the designed mask and exposed under the UV light for 20

minutes. This is called photolithography process. Forth, the exposed copper piece is

washed in the diluted D4000, and the ratio between D4000 and water is 1 to 20. After

this step, the shim area is protected by the photoresist on the copper piece. Fifth, the

copper piece is put into an etching tank and etched. The duration of etching is

determined by the thickness of the copper. Sixth, the photoresist on the copper shim is

rinsed off by Aceton after the etching is done. The copper shim from the etching

machine is soldered to the anode of the diode by using 180 °C Pb/Sn solder paste and

hotplate of 210 °C. Since the shape of the cross-section the shim is trapezoidal due to the

etching step, the larger area side is preferred to be soldered with the contact to form an

obtuse-angle dam for the polyimide layer.

(5) Field-shaping metal layer deposition. First, a piece of Kapton ring mask which fits

the dimensions of the JTEs of the device is cut by using the laser machine. Second, this

Kapton mask is adhered to the device and protects the JTE area. Third, the device

package is put in the chimer of a sputtering machine to deposit both titanium and copper.

The deposition duration of the titanium and copper is 45 minutes respectively, and the

thickness of these two metals is around 500- 600 µm and 1000 µm, respectively. Forth,

the Kapton ring mask is peeled off. In this step, from the simulation results in the

previous section, the Kapton mask is preferred to be smaller than the actual JTE

dimensions since it is difficult to precisely control the mask to be the same size as the

JTEs. The via is deposited as well.

(6) Interlayer patterning. First, a piece of Kaption mask is necessary to protect the top

of the copper shim. Second, a designed screen is loaded to a screen printer and the

- 58 -

device package is fixed to the platform of the screen printer with the anode side faced up.

Third, the polyimide is printed onto the anode side using the screen printer. Forth, the

Kapton mask is peeled off and the device packaging is put into an oven and cured

following the curing profile given in the datasheet. If thick polyimide layer is necessary,

this step can be performed repetitively.

(7) Sputtering. The device package is put into the chamber of the sputtering machine

and thin layers of metals are deposited on both sides of the package by two rounds of this

step.

(8) Electroplaing. First, a mask is designed for pattern of the anode-side metallization.

Second, the photolithography process is preceded on the device package as described in

step (4). Third, the device package is put into the copper-plating solution with the

desired pattern open. The current of the electroplating is set to 0.1 A since the area is

small.

(9) Micro--etching. The excessive sputtered copper and titanium are removed by the

micro-etchant respectively.

(10) Final cutting and assembling. The excessive ceramic carrier is cut by using the

laser machine. The external components or I/O pin can be soldered in this step.

1. Ceramic Cutting

6. Etching

Ceramic

2. Chip EmbeddingDeviceEpoxy

3. Interlayer Patterning

Polyimide

4. Sputtering

Thin-film copper

5. Electroplating

Thick-film copper

Fig. 4.4. Major fabrication steps of the LVEP package.

- 59 -

4.2.3. Fabrication process and experimental results

The fabrication process is shown in Fig. 4.6 through Fig. 4.13. The final package is

less than 1 mm thick. The Five HVEP package are fabricated and tested by using a high-

power curve tracer. The test results show that fabricated package can block the rated

voltage which is 2 kV, as it can be seen in Fig. 4.14, which is one of the results. In the

mean time, two LVEP package are fabricated and tested as well. Both of them failed at

1.1 kV-1.2 kV.

The cross-sectional view of one of the fabricated package is shown in Fig. 4.15. The

dimensions of the fabricated HVEP package are measured using an Environmental SEM

Device

Epoxy

Device

Epoxy

Via

Copper

shim

Thin-film

copper

Thicker

polyimide

Thicker

polyimide

Thin-film copperThin-film copper

Thick-film copperThick-film copper

1. Ceramic Cutting

6. Etching

2. Chip Embedding


4. Sputtering

5. Electroplating

3. Shim Soldering

4.Field-shapping Metal Layer Deposition

Kaptonring mask4. Masking of JTEs

Device

Epoxy

Device

Epoxy

Via

Copper

shim

Thin-film

copper

Thicker

polyimide

Thicker

polyimide

Thin-film copperThin-film copper

Thick-film copperThick-film copper

1. Ceramic Cutting

6. Etching

2. Chip Embedding


4. Sputtering

5. Electroplating

3. Shim Soldering

4.Field-shapping Metal Layer Deposition

Kaptonring mask4. Masking of JTEs

Fig. 4.5. Major fabrication steps of the HVEP package.

- 60 -

(ESEM). One of the measurement results is shown in Fig. 4.16. From Fig. 4.16 (a), it

can be clearly seen that the angle formed by the copper shim is greater than 90°. The

total thickness of the shim and the solder layer is around 155 µm. The thickness of the

polyimide at the shim edge is much thicker than the shim because the screen-printing

process cannot be well-controlled at the location. Fig. 4.16 (b) is the ESEM picture at the

package edge. At this location, the screen-printing process can be well-controlled.

Therefore the thickness of the polyimide is around 140 µm to 150 µm. A comparison of

the designed values and the fabricated values are shown in Table VIII.

3. Shim soldering

Top view

Copper shim (thickness = 0.254 mm)

3. Shim soldering

Top view

Copper shim (thickness = 0.254 mm)

Fig. 4.8. Fabrication process of the HVEP package: step 3. Shim soldering.

2. Chip embedding

Top view Bottom view

Anode (gold) Cathode (gold)

Epoxy Epoxy

2. Chip embedding


Anode (gold) Cathode (gold)

Epoxy Epoxy

Fig. 4.7. Fabrication process of the HVEP package: step 2. Chip embedding.

1. Ceramic cutting

3 mm

5 mm

Ceramic

( thickness = 0.508 mm)1.8 kV SiC diode

(thickness = 0.381 mm)

Opening for the diode

Via for interconnection between inserted metal and cathode

1. Ceramic cutting1. Ceramic cutting

3 mm

5 mm

Ceramic

( thickness = 0.508 mm)1.8 kV SiC diode


Opening for the diode

Via for interconnection between inserted metal and cathode

Fig. 4.6. Fabrication process of the HVEP package: step 1. Ceramic cutting.

- 61 -

7. Top metallization sputtering

Anode + Copper shim

Top metallization

7. Top metallization sputtering

Anode + Copper shim

Top metallization

Fig. 4.12. Fabrication process of the HVEP package: step 7. Top metallization deposition.

6. Interlayer patterning

Anode + Copper shim

Polyimide


6. Interlayer patterning

Anode + Copper shim

Polyimide


Fig. 4.11. Fabrication process of the HVEP package: step 6. Interlayer patterning.

5. Inserted and bottom metallization sputtering

Top view

Anode + copper shim

Inserted metallization

Guard rings (un-

sputtered)

5. Inserted and bottom metallization sputtering

Top view

Anode + copper shim

Inserted metallization

Guard rings (un-

sputtered)

Fig. 4.10. Fabrication process of the HVEP package: step 5. Thin layer copper deposition.

4. Masking

Top view

Kapton ring (as a mask to prevent the sputtering on the guard rings)

4. Masking

Top view

Kapton ring (as a mask to prevent the sputtering on the guard rings)

Fig. 4.9. Fabrication process of the HVEP package: step 4. Masking.

- 62 -

TABLE VIII

COMPARISON OF DESIGNED VALUES AND FABRICATED VALUES OF HVEP PACKAGE

Designed value Fabricated value

Polyimide thickness D (µm) 150 230 @ shim edge

140 @ package edge

Shim thickness (µm) 150 155

Polyimide edge angle θ (°) 90 125 - 135

8. Final package


Anode + Copper shim

Thick copper

8. Final package8. Final package


Anode + Copper shim

Thick copper

Fig. 4.13. Fabrication process of the HVEP package: step 8. Electroplating and etching.

10

Leakage current (uA)

20

30

40

50

60

70

80

90

Blocking voltage (kV)0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

2.012 kV, 5 µA

Diode breakdown

Fig. 4.14. Test result of the fabricated HVEP package.

- 63 -

4.3. Summary

In this Chapter, the general engineering design practice is reviewed first. The design

procedure of the HVEP package is presented. From the parameters study in previous

Shim

Solder

SiC Diode

Polyimide

Ceramic

Polyimide

(a) (b)

Fig. 4.16. ESEM picture of one fabricated HVEP package. (a) Copper shim edge. (b) Package edge.

SiC Diode Ceramic Via

Shim Polyimide

Epoxy

Silicone gel

Solder mask

Metal clip

Fig. 4.15. Cross-sectional picture of one fabricated HVEP package.

- 64 -

Chapter, a general design guideline is proposed. A 2 kV SiC diode package is designed

by following the design guidelines.

The structure of the HVEP package is more complicated than that of the LVEP

package. Thus the fabrication procedure of the LVEP package needs to be re-designed to

satisfy the requirement of the HVEP package. The fabrication of the LVEP package is

revisited first. Then the new fabrication process for the HVEP package is proposed. In

the fabrication, the thickness of the polyimide which is through screen-printing, and the

accuracy of the alignment of the Kapton ring mask for the JTE area cannot not be easily

controlled.

Five HVEP packages are fabricated in house. The test results show that they can block

the rated voltage which is 2 kV. An environmental SEM measurement is done to

measure the dimensions of the fabricated package. The experimental results validate the

simulations and the design guidelines.

- 65 -

Chapter 5: Simplified Modeling of the HVEP Package

Simulation in MEDICI contains the internal information of the power semiconductor

devices, and its results are closer to the reality. However, the simulation is very time-

consuming. Usually it takes hours to run one simulation on a Linux system in the

previous Chapter. On the other hand, in the early stage of design, it is not necessary to do

this elaborated simulation. Simple and quick methods are needed to give an overall idea

of the design.

The complexity of the HVEP package partly comes from the internal structure of the

device. It is not easy to model this in a mathematical way or in an electromagnetic field

simulation software like MAXWELL 2D. Thus, the model of the power device needs to

be simplified first. Then the HVEP package can be either mathematically calculated or

simulated in a quick and simple way.

5.1. Model simplification

Although the internal structures are different from one power semiconductor device to

the other, the mechanism is the same when they are blocking voltages. The JTE relieves

the high electric field crowding at the corner of the main PN junction, and establishes a

horizontal voltage drop on the surface of the device instead of a vertical one.

When the device is blocking voltages, its surface has a voltage drop in certain scheme

and the rest of the device body has the same potential. From this mechanism, a

simplified model can be built as shown in Fig. 5.1. The JTE is modelled as a conductor

and its voltage is a function of the x-axis as in Fig. 5.1 (b). The bottom, the left and the

right of the device are at same potential. This model can be further simplified as a piece

of conductor that has different voltage added to different segments. Then the HVEP

structure can be simplified as well, as shown in Fig. 5.2. Since the area of the embedded

insulation material and the ceramic is fully shielded, this part can be eliminated and the

only the polyimide material and different voltage boundaries are left in the model.

Since the purpose of the JTE is to avoid electric field crowding in the structure, it

makes the voltage drop on it as linear as possible. Fig. 5.3 shows the voltage distribution

- 66 -

on the JTE of the device in the simulation. Therefore, the voltage distribution can be

simplified as a linear function of the distance in x direction. The final simplified model

can be used in the mathematical calculation and the simulation is shown in Fig. 5.4. Only

the polyimide area is of interest.

V = 0 V V = f(x)

x

V = 10 kV

Embedded

insulation

material

Ceramic

Polyimide

y

Fig. 5.2. Simplified model of the HVEP package.

P+P-JTE

N-

N+

V = 10 kV

V = 0 V

SiC

V = 0 V V = f(x)

x

V = 10 kV

Main

junction

JTE N body

(a) (b)

Fig. 5.1. Model of the power semiconductor device. (a) Model in MEDICI. (b) Simplified model.

- 67 -

5.2. Simulation in MAXWELL 2D

MAWELL 2D is a powerful electro-magnetic simulation software. It is user-interface

friendly, simple and fast when it runs static electric field simulations. However, it cannot

model the internal structure of the power semiconductor devices in the software. With

the simplified structure in Fig. 5.4, the internal information of the device is unnecessary,

then it is possible to perform the initial simulations in MAXWELL 2D.

The voltage distribution on the JTE is modelled in MAWELL 2D, as compared to

MEDIC results in Fig. 5.5. The origin is at point C, and the curve is reconstructed by 6

segments, as shown in (5.1).

V = 0 V V = f(x)

x

V = 10 kV

Polyimide

yA

B

C D E F

Fig. 5.4. Simplified model for mathematical calculation and simulation.

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Voltage (

kV

)

5.0

0

2.5

7.5

1

2.5

10

Fig. 5.3. Voltage distribution on JTE.

- 68 -

( )

( )

( )

( )

=

+−=

+−=

+−=

+−=

=

13500

1300037.00599.0

500

1170032.00499.0

1300

780027.00499.0

3900

20017.00999.0

4600

0

6

5

4

3

2

1

V

xV

xV

xV

xV

V

>

<<

<<

<<

<<

<<

mmx

mmxmm

mmxmm

mmxmm

mmxmm

mmx

5.0

43.037.0

37.032.0

32.027.0

27.017.0

17.00

(5.1)

The electric field distribution along the x direction at different y positions in Fig. 5.4 is

shown in Fig. 5.6. The upper dashed- line gives the electric field intensity at the position

of the corner of the device, and the lower dashed- line gives the electric field intensity in

the uniform distribution area, as explained in Fig. 5.7. The error of the MAXWELL

simulation results is define in (5.2) and it is shown in Fig. 5.8.

%100×−

=MEDICI

MEDICIMAXWELLerror (5.2)

Distance (mm)

0.00 0.20 0.40 0.60 0.80 1.00

Voltage (

kV

)

5.0

0

2.5

7.5

1

2.5

10

12

.51

07

.55

.02

.50

Vo

lta

ge

(kV

)

0.11 0.33 0.55 0.990.77 1.1

Distance (mm)

Linear model

Segmental model

(a) (b)

Fig. 5.5. Comparison of the voltage distribution on JTE in MEDICI and MAXWELL. (a) Voltage

distribution in MEDICI. (b) Voltage distribution in MAXWELL.

- 69 -

V = 0 V V = f(x)

x

V = 10 kV

Polyimide

yA

B

C D E F

Fig. 5.7. Explanation of two values in Fig. 5.6.

200

E (

kV

/mm

)

0.2

Distance (mm)

150

50

10

0100

80

60

40

20

0.4 0.6 0.8 1.0

E (

kV

/mm

)

40 kV/mm

34 kV/mm

42 kV/mm

35 kV/mm

8

0E

(kV

/mm

)0.2

Distance (mm)6

02

04

08

06

04

02

00.4 0.6 0.8 1.0

E (

kV

/mm

)

40 kV/mm

34 kV/mm

40 kV/mm

35 kV/mm

50

E (

kV

/mm

)

0.2

Distance (mm)

30

10

20

50

40

10

0.4 0.6 0.8 1.0

E (

kV

/mm

)

40 kV/mm

34 kV/mm

40 kV/mm

35 kV/mm

40

60

20

30

(a) (b) (c)

E (

kV

/mm

)

0.2

Distance (mm)

30

10

20

40

0.4 0.6 0.8 1.0

E (

kV

/mm

)

37 kV/mm

34 kV/mm

37 kV/mm

34.5 kV/mm

40

20

30

E (

kV

/mm

)

0.2

Distance (mm)

30

10

20

10

0.4 0.6 0.8 1.0

E (

kV

/mm

)

35 kV/mm

34 kV/mm

33 kV/mm 34 kV/mm

20

30

35

25

15

E (

kV

/mm

)

0.2

Distance (mm)

30

10

20

10

0.4 0.6 0.8 1.0

E (

kV

/mm

)

33 kV/mm 34 kV/mm

30 kV/mm 34 kV/mm35

20

30

25

15

5

(d) (e) (f)

Fig. 5.6. Comparison of the electric field intensity at different y locations. Upper: MEDIC; Lower:

MAXWELL 2D (a) y = 0. (b) y = 10 µm. (c) y = 50 µm. (d) y = 100 µm. (e) y = 200 µm. (f) y = 300

µm.

Uniform distribution area x position of pink dash line value

- 70 -

From the comparison, it can be seen that the MAWELL simulation results give less

than 10% error compared to the MEDICI simulation. With the simplified model, the

simulation in MAXWELL can be used as initial simulation of the structure and it can

give an overall idea of the structure. More elaborated and accurate simulations need to be

performed in MEDICI.

5.3. Summary

Although the simulations in MEDICI include the internal information of the device,

and it gives an accurate and comprehensive electric field distribution, the simulation is

very time-consuming. In the early stage of design, it is not necessary to spend so long

time to do the simulation. On the contrary, a simplified structure is preferred to give a

simple, quick and clear overall understanding of the package first.

In this Chapter, the proposed HVEP structure is simplified. The device is replaces by a

conductor with 0 V and a conductor with a piece-wise linear voltage distribution in

series. In this simplified structure, only the polyimide area is of interest.

The simplified structure can be applied to perform the simulation in MAXWELL 2D.

After the voltage distribution on the JTEs is modelled, the simulation results in both

MEDICI and MAXWELL are presented. The MAWELL simulation results give less


-10

-8

-6

-4

-2

0

2

4

6

0 10 50 100 200 300

y (um)

Err

or

(%)

Device corner Uniform area

Fig. 5.8. Errors of the simulation results in MAXWELL compared to the results in MEDICI.

- 71 -



done in MEDICI.

- 72 -

Chapter 6: Summary

The high-voltage SiC power semiconductor devices have been developed in recent

years. They cause an urge in the need for the power semiconductor packaging to have

not only low interconnect resistance, less noise, less parasitic oscillations, improved

reliability, and better thermal management, but also High-Voltage (HV) blocking

capability. With the ever-rising electric field intensity in the package caused by the high

voltage, the understanding the distribution of the electric field is becoming crucial to the

design, providing proper structure for high-voltage.

The primary objective of the high-voltage power semiconductor package is to limit the

maximum electric field intensity of the insulation materials to be lower than their

dielectric strength. A good understanding of electric field distribution can help in both

identifying potential dielectric failure and designing appropriate structure improvement

strategies for the package. Simulation tools and experimentation are commonly used to

perform the analysis. Advanced material that has high dielectric strength will also aid in

blocking high voltage of the package.

In this research, a thorough static electric field analysis is performed and an in-depth

understanding of the electric field distribution of the LVEP, MVEP and HVEP. The

objectives discussed in Chapter 1 are accomplished. The summary and contributions of

this research are discussed in the following.

6.1. Contributions

I. Understanding of the electric distribution in the Low-Voltage Embedded Power

(LVEP) package in MEDICI

a. The studies show that two electric field hotspots are at the upper and lower corner

of the device in the LVEP package.

The LVEP structure is revisited with a 10 kV SiC PiN diode. With the internal

structure of the device, the simulation shows two hotspots in both insulation materials are

at the upper and lower corner of the device. The internal structure of the device makes

the bending of the equipotential lines at both corners in the insulation materials.

- 73 -

b. Studies show the electric field distribution of the double-sided metallization LVEP

structure and the impact of the parameters in this structure on the electric field

distribution.

The double-sided metallization is proved to be an effective way to reduce the high

electric field concentration at the lower corner of LVEP structure. The higher thickness

of the polyimide layer can decrease the maximum electric field at the corners of the

device in two insulation material. However, when the thickness is comparable to the

thickness of the ceramic, it is less effective. From the material property point of view,

low dielectric constant of the polyimide is desired.

II. Development of a Medium-Voltage Embedded Power (MVEP) structure in

MEDICI

a. Development of a MVEP structure in MEDICI.

Based on the understanding of the LVEP structure, a MVEP structure is proposed. The

cathode metallization of the MVEP structure is extended to the top of the structure. The

maximum electric field intensity at the corners of the device inside two insulation

material is reduced greatly.

b. Studied show the impact of the parameters on the electric field distribution in the

MVEP structure.

The higher thickness of the polyimide layer can decrease the maximum electric field at

the corners of the device in two insulation material. However, when the thickness

reaches certain value, it is less effective. From the material property point of view, low

dielectric constant of the polyimide is desired. The influence of the thickness of the

polyimide and the properties of the materials is explained by simplifying the structure to

a circuit that consists of two capacitors in series.

III. Development of a High-Voltage Embedded Power (HVEP) structure in MEDICI

a. Development of a HVEP structure in MEDICI.

A thin layer of metal is inserted to the middle of the structure and it is tied to the

cathode metallization. This field-shaping metal layer is a shield to the embedded

insulation material. Thus, the maximum electric field at the corners inside the two

- 74 -

insulation materials is reduced to the value below their dielectric strength. Furthermore,

since the embedded insulation material is shielded by the field-shaping metal layer, even

with the presence of the voids in the embedded insulation material, it won’t degrade the

voltage rating of the package.

b. Studies show the impact of parameters on the electric field distribution in the

HVEP.

The thickness of the polyimide is proportional to its dielectric strength and the applied

voltage. The best position for the field-shaping metal layer is on the same surface as the

device, and the optimal voltage applied this metal layer is 0 V. Simulation also indicates

that the length of the field-shaping metal layer should neither exceed the edge of the

device nor be apart from the edge too much. The best result is obtained when the edge of

the field-shaping metal is right at the edge of the device. It can be found that the angle of

polyimide edge is less tan 90°, and this smaller angle could influence the package voltage

rating greatly. Although this angle is unavoidable, it can be solved by the application if a

thick enough “dam”.

IV. Development of design guidelines for the HVEP package and verification

a. Development of design guidelines for the HVEP structure.

The design procedure of the HVEP package is presented. Based on the simulations and

parameter study, the design guidelines are given. (1) The best position of the field-

shaping metal layer is on the same surface as the device. (2) The best width of the field-

shaping metal layer is when the field-shaping metal layer touches the edge of the device.

(3) The best applied voltage is the same as the cathode voltage. (4) The thickness of the

polyimide layer is determined by the rated voltage and the dielectric strength of the

material from calculation or simulation. (5) A “dam” that has the same thickness as the

polyimide is needed in the package to prevent the natural angle of polyimide caused high

electric field concentration.

b. Development of fabrication process of a HVEP package.

Due to the difference of the HVEP structure and LVEP structure, several steps are

added to the standard LVEP fabrication process and the dimensions are changed

accordingly. The shim soldering, field-shaping metallization and double-sided

- 75 -

metallization deposition, and thicker polyimide layer are the core difference between two

processes. A HVEP package for a 2 kV SiC diode is designed following the given design

guidelines and fabricated following the proposed procedure.

c. Experimental verification of the proposed HVEP structure and the design

guidelines.

Test results show that the fabricated 2 kV SiC diode package can block at least 2 kV.

The Environmental SEM image shows that the fabricated package follows the design

guidelines.

V. Development of a simplified model of HVEP package

a. Simplification of the model of the power semiconductor devices.

The model of power semiconductor devices is simplified to a conductor with difference

voltage on different segments. No more internal information of the device is necessary.

This simplified model can be applied to both mathematical analysis and non-

semiconductor simulator software, such as MAWELL to do quick and simple calculation

or simulation compared to MEDIC which is very time-consuming.

b. Investigation on the feasibility of the application of conformal mapping to the

electric field calculation in the HVEP package.

Conformal mapping is a very useful mathematical theory to calculation field problems.

Theoretically, after a series of the conformal mapping the simplified model of the HVEP

structure can be transformed to a rectangle in which the potential distribution is known.

Then this potential distribution can be inverse transformed back to the original simplified

model and the electric field intensity can be calculated accordingly. However, due to the

limitation of the mathematical software, severe error occurs in both forward and inverse

mapping procedure, which finally fails the effectiveness of the mapping.

c. Comparison of the simulation in MAWELL with the simplified model and that in

MEDICI.

From the comparison, it can be seen that the MAWELL simulation results give less



- 76 -


done in MEDICI.

6.2. Recommendations

New materials. The selection of the insulation materials is important to achieve high-

voltage blocking capacity and better reliability. Although the current design of the HVEP

package is based on the current available insulation material with low dielectric strength,

the selection of the insulation materials should continue to search for emerging insulation

materials that have high dielectric strength.

Electrical performance. Although the package using embedded power technology has

a promising electrical performance of switching and conduction, it is necessary to test the

forward characteristics of the HVEP package since new layer is added to the LVEP

structure. These tests include the in-circuit switching speed, switching and conduction

loss, EMI, etc.

Reliability and thermo-mechanical performance. In the structure, the CTE mismatch of

the copper and the semiconductor will cause thermo-mechanical issues in the package.

The thermo-mechanical stress investigation, thermal performance, and cooling

technology are needed to be studied.

Expandability to HV module package. Embedded power technology can be used to

power semiconductor device package as well as the system package. Theoretically, the

HVEP device package can easily expended to a HV module package. However, issues

include the layout design, thermal problems, EMI, etc.

- 77 -

Reference

[1] R. R. Tummala, E. J. Rymaszewski and A. G. Klopfenstein, Microelectronics

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[2] S. Wen and G. Q. Lu, “Finite-element modeling of thermal and thermomechanical

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- 78 -

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- 81 -

Appendix Mathematical Modeling of the Simplified Model of

HVEP

The electric field calculation is quite simple and straight-forward when the structure

and the material are simple enough. However, the voltage distribution of the simplified

model shown in Fig. 5.4 is irregular. Hence the electric field cannot be calculated

directly. Some further mathematical manipulation is needed.

A1 Conformal Mapping and Schwarz-Christoffel Transformation

A conformal mapping is a transform of geometric figures in which infinitely small

pieces are transformed into similar ones [47]-[55]. A map is called conformal at z0 if it

preserves oriented angles between curves through z0, as well as their orientation. A

Schwarz-Christoffel mapping is a transformation of the complex plane that maps the

upper half-plane conformally to a polygon. A polygon in w plane shown in Fig. A.1 (a)

has vertices at w1, w2,…, wn with corresponding interior angles a1, a2, …, an, respectively.

The points w1, w2, …, wn are mapped into points x1, x2, …, xn on the real axis of the z

plane shown in Fig. A.1 (b), respectively. A transformation which maps the interior R of

the polygon of the w plane on to the upper half plane R’ of the z plane and the boundary

of the polygon on to the real axis is given by (1) and (2),

( ) ( ) ( ) 11

2

1

1121 −−−

−−−=πππ na

n

aaxzxzxzA

dz

dwL (1)

( ) ( ) ( )( ) BdzxzxzxzAw na

n

aa+−−−= ∫

−−− 11

2

1

1121 πππ

L (2)

where A and B are complex constants.

- 82 -

Consider a rectangle in the W plane, which is symmetrical with respect to the imaginary

axis, as shown in Fig. A.2 (a), it can be conformally mapped onto the upper-half plane.

The boundary points B, 0, C = -b, 0, b are mapped into the boundary points -1, 0, 1 in the

R plane respectively. Let the image of the point E be a point of the real axis 1/k; due to

the principle of symmetry the image of the point A is the point -1/k. From the Schwarz-

Christoffel transformation, the function realizing the inverse mapping of the upper-half

plane onto the rectangle is:

( )( )∫−−

=r

k

dCw

0 2221

11 ξξ

ξ (3)

iH

b-b 0

C

EA

B

u

v

W Plane

C EA B

-1 1 1/k-1/k

t

s

R Plane

(a) (b)

Fig.A.2. Elliptic function of first kind. (a) Rectangle (original plane) (b) Upper-half plane (destination

plane)

u

v

w1

w2

w3

w4

a1a2

a3

a4

R

x

y

x1 x2 x3 x4

R’

(a) (b)

Fig. A.1. Schwarz-Christoffel transformation. (a) Polygon (original plane) (b) Upper-half plane

(destination plane)

- 83 -

The function

( )( )( )∫

−−=

r

m

dCmrF

0 221

11,

ξξ

ξ (4)

is called the elliptic integral of the first kind. The number m is called the parameter and

the number mk = is called the modulus of the elliptic integral. Provisionally suppose

that 0 < m < 1.

The value

( )( )( ) ∫∫

−=

−−=

2/

0 2

1

0 22 sin111,1

s

m

d

mss

dsmF

ϕ

ϕ (5)

is called the complete elliptic integral of the first kind and is designated as K(m) or

simply K. Thus the segment (-1, 1) is mapped into the segment (-K, K) by this function.

The point mkE /1/1 == in the R plane is mapped into the point

( )( )( ) ( )( )∫∫

−−+

−−==

k

mss

dsi

mss

dsmkFw

/1

1 22

1

0 22 1111,/1 (6)

The first term in this formula is the complete elliptic integral and the second term is

transformed by the change of the variable

1' 22 =+ ymms (7)

where mm −= 1' is the so-called complementary parameter of the elliptic integral, and

( )( ) ( )( )∫∫−−

=−−

1

0 22

/1

1 22 '1111 ymt

dt

mss

dsk

(8)

For brevity the value of the complete elliptic integral of the first kind of the

complementary parameter K(m’) is designated as K’. Therefore, the point

mkx /1/12 == is mapped into the point K+iK’, and the whole upper-half plane is

mapped onto the rectangle with the base 2K and the height K’.

The parameter m is unknown when searching for the function (3). It can be found from

the equation

( )( ) b

H

mK

mK=

−1 (9)

where H is the height of the rectangle in the w plane, and b is the half width of the

rectangle, as shown in Fig. A.2 (a).

- 84 -

Then the constant C1 is determined as

( )mK

bC =1 (10)

where C1 is the constant in the integration in (3).

A2 Model of HVEP package

Neither the equipotential lines nor the electric field can be mathematically plotted in the

simplified model in Fig. 5.4. It is desired to have a structure that either the electric field

distribution or the equipotential lines can be easily expressed or calculated. For example,

Assume that the aspect ration (AC/CD) is very small, then the equipotential lines can be

approximately straight, as shown in Fig. A.4.

Thus, the strategy in this section is to convert the structure shown in Fig. A.3 (a) to a

structure similar to Fig. A.3 (b) through a series of conformal mapping. Then, the easily

calculated potential distribution information can be transformed back to the original

V = 0 V

V = f(y)

x

V = 10 kV

Polyimide

y

A

B C

D

E

V = g(ξ)

ζ

V = 10 kVPolyimide

ξ

V = 0 V

A

C D

E

(a) (b)

Fig.A.3. Transformation of the simplified structure. (a) Simplified structure (rotate 90°). (b) Transformed

structure.

- 85 -

structure through the reverse transformation. Finally, both the potential and electric field

distribution in the original structure are known.

Through the elliptic integral of the first kind and its inverse mapping, the Elliptic

Jacobian functions, a rectangle and the upper-half plane can be transformed between each

other. Thus, this transformation is done firstly, as shown in Fig. A.5 (a) and (b). The

parameter 2km = is defined approximately as the function of the ratio

( ) ( ) bHmKmK //' = by mean of interpolation based on the dimensions of the original

structure.

The destination rectangle in ξ-ζ plane is shown in Fig. A.5 (d) and its corresponding

upper-half plane after the transformation are in Fig. A.5 (c). Thus there is one more

transformation is necessary to map the upper-half plane Fig. A.5 (b) to the upper-half

plane in Fig. A.5 (c). A linear-fractional transformation can perform this.

The transformation

δγ

βα

+

+=

z

zf , 0≠− βγαδ (11)

is called linear-fractional transformation. It can be considered as combinations of the

transformation of translation, rotation, stretching and inversion. This transformation

maps circle in z plane into circles in the w plane.

If z1, z2, z3 and z4 are four distinct points in the z plane, then the quantity

( )( )

( )( )13

23

24

14

zz

zz

zz

zzL

−

−

−

−= (12)

V = g(ξ)

ζ

V = 10 kV

ξ

V = 0 V

A

C D

EEquipotential lines

Fig.A.4. Equipotential lines approximation

- 86 -

is called the cross ratio of z1, z2, z3 and z4. This ratio is invariant under the

transformation, and this property can be used in obtaining specific transformation

mapping three points into three other points.

Thus, the destination rectangle can be mapped from the original rectangle through the

Elliptic Jacobian transformation, linear-fractional transformation, and elliptic integral of

the first kind.

A3 The problem

u

v

A

B C

D

E

-b b

H

d0

t

s

-1/k -1 +1 d1 1/k

A B C D E

(a) (b)

n

m

-1/p -1 +1b2 1/p

A B C D E

ξ

ζ

A

B

C D

E

-l l

G

b3

(c) (d)

Fig.A.5. Transformations. (a) Original rectangle (u-v). (b) Upper-half plane after Elliptic Jacobian

transformation (s-t). (c) Upper-half plane after linear-fractional transformation (m-n). (d) Destination

rectangle after elliptic integral of the first kind (ξ-ζ).

- 87 -

As mentioned in the previous section, the parameter m comes from the interpolation,

and there is an assumption that the aspect ratio of the destination rectangle is small.

However, it is found that the aspect ratio of the destination rectangle is about 1.5 when

the dimensions of the structure in Chapter 5 are applied.

Fig. A.6 shows the variation of the aspect ratio of both original rectangle and the

destination rectangle. It can be seen that in the whole range of k, the aspect ratio of the

destination rectangle is always greater than 1. It is also observed that when k is very

close to 1, the aspect ratio can be close to 0. Thus, in the last transformation, which is the

mapping from the upper-half plane to the destination rectangle, the p parameter has to be

very close to 1 to make the aspect ratio of the destination rectangle to be small.

Therefore, one more transformation has to be added to this mapping.

An exponential transformation can be applied. The exponential function of the

complex variables is defined as

yieyeeeew xxiyxz sincos +=== (13)

The aspect ratio of the destination rectangle is reduced to 0.2 after this transformation is

added. However, from the nature of the exponential function, it amplifies more on the

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.5

1

1.5

2

2.5

3

k

Asp

ect ra

tio

G/2l

H/2b

Fig.A.6. Variation of aspect ratio with the parameter k.

- 88 -

large numbers than the small numbers. Due to the limitation of the mathematical

software, MATLAB, it cannot identify these amplified large numbers individually. This

causes big errors in the both forward mapping and inverse mapping. As shown in Fig.

A.7, point s1 is a small number, and points s2, s3, and s4 are large numbers. After the

exponential transformation, point s1 is mapped into point p1 in the p-q plane. However,

because the mapped points of s2, s3 and s4 are too large, the software recognizes them as

one point in the p-q plane, infinity. After the linear-fractional transformation and the

elliptic integral of the first kind are done, point s1 is mapped into a point somewhere on

the boundary of the destination rectangle, points s2, s3 and s4 are mapped to the same

point, iG. This wrong forward mapping gives the wrong information to the inverse

mapping as well. Points s2, s3, and s4 are merged to one point back to the original

rectangle after the inverse mapping. This mapping error is caused by the software and it

is inevitable.

Theoretically, the electric field distribution of the simplified structure shown in Fig. 5.4

can be calculated through a series of conformal mapping mathematically, however, the

limitation of the mathematical software causes inevitable error during the calculation,

which fails the mapping.

s1 s2 s3 s4

s

t

p1

p2

p3

p4

p

q

inf

(a) (b)

m1

m2

m3

m4

m

n

inf

ξ1+iζ1

ξ

ζ

iζ2 iζ3 iζ4iG

(c) (d)

Fig. A.7. Error generation in the forward mapping. (a) upper-half plane in s-t plane. (b) p-q plane after

exponential transformation. (c) m-n plane after linear-fractional transformation. (d) Destination rectangle

in ξ-ζ plane.

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