Technical University Tallinn, ESTONIA 1 Boolean derivatives Calculation of the Boolean derivative:...
-
Upload
edwina-richards -
Category
Documents
-
view
222 -
download
0
Transcript of Technical University Tallinn, ESTONIA 1 Boolean derivatives Calculation of the Boolean derivative:...
Technical University Tallinn, ESTONIA 1
Boolean derivatives
316254142321 ))((( xxxxxxxxxxxxy
5
562414233121
5
625414233121
5
625414233121
5
625414233121
5
625414233121
5
))((
)))(((
)))(((
))))((((
x
xxxxxxxxxxxx
x
xxxxxxxxxxxx
x
xxxxxxxxxxxx
x
xxxxxxxxxxxx
x
xxxxxxxxxxxx
x
y
Calculation of the Boolean derivative:
Given:
Technical University Tallinn, ESTONIA 2
Derivatives for complex functions
Boolean derivative for a complex function:
Example:
i
j
j
k
i
jk
x
F
F
F
x
XXFF
)),((
y
x2
x1x3x44
3
3
1
14 x
x
x
x
x
y
x
y
Additional condition:
03
2
x
x
Technical University Tallinn, ESTONIA 3
Boolean differentials and fault diagnosis
&
1
&
x1
x2
x3
&1
1
1
0
1
10
y
)( 321 xxxy
x1 = 0x2 = 1x3 = 1dy = 0
))())((( 332211 dxxdxxdxxydy
0)(1 321 dxdxdxdy
Correct output signal:
1)(13
12
01 dxdxdx 1
01 x
&
1
&
x1
x2
x3
&1 0
1
1
0
0
0
1 y
x1 = 0x2 = 0x3 = 0dy = 1
Erroneous output signal:
1)(1 321 dxdxdxdy
103
02
01 dxdxdx
Technical University Tallinn, ESTONIA 4
Boolean differentials and fault diagnosis
1)(13
12
01 dxdxdx 1
01 dx
103
02
01 dxdxdx
Rule: 010 kk dxdx
103
02 dxdx
1)(13
03
02
03
02
12
01 dxdxdxdxdxdxdx
= 0Diagnosis:
113
03
02
01 dxdxdxdx
The line x3 works correct
There is a fault: The fault is missing
12 x11 x
Technical University Tallinn, ESTONIA 5
Binary Decision Diagrams
Functional synthesis BDDs:
43124321 ))(( xxxxxxxxy
Shannon’s Theorem:
0111 )()(
)(
kk xxXFxXFx
XFy
xky1
)(kx
XF
0)(
kxXF
x1y2432 )( xxxx
x2
x3 x4
43xxx3
x4
43 xx
Using the Theoremfor BDD synthesis:
Example:
Technical University Tallinn, ESTONIA 6
Binary Decision Diagrams
D
C
q c
q’
D
S
C
q
Elementary BDDs
R
0
')'(
SR
qcRqScq
c
q’
S
R q’
R
U
D Flip-Flop
RS Flip-Flop
JK Flip-Flop
S
J
q
R c
q’
S
R q’
C
KK
J
U - unknown value
Technical University Tallinn, ESTONIA 7
Building a SSBDD for a Circuit
&
1
1x1
x2
x3
x21
x22y
a
b
))((& 322211 xxxxbay
a by
a x1
x21
b x22
x3
ay x22
x3
y x22
x3
x1
x21
DD-library:
Superposition of DDs
Superposition of Boolean functions:
Given circuit:
Compare to
SSBDD
Structurally Synthesized BDDs:
b a
Technical University Tallinn, ESTONIA 8
High-Level DDs for Finite State Machines
1/0
3/0
5/0
6/1
4/1
2/1
x1 x1
x2 x2
x1
x1
ResRes q’ x1
3.0
x2 4.1
5.0
6.1x1
1.0
*.0
q.y
1
1 1
2
3
4
5
6
*
3 42.1
5
6
8
9
10
12
11
13
7
1.02
0
0
0
1
1
1
State Transition Diagram: DD:
Technical University Tallinn, ESTONIA 9
High-Level Decision Diagrams
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Superposition of High-Level DDs:
A single DD for a subcircuit
R2
R2 + M3
Instead of simulating all the components in the circuit, only a single path in the DD should be traced
M1
M2
Technical University Tallinn, ESTONIA 10
Decision Diagrams for Microprocessors
I1: MVI A,D A IN
I2: MOV R,A R A
I3: MOV M,R OUT R
I4: MOV M,A OUT A
I5: MOV R,M R IN
I6: MOV A,M A IN
I7: ADD R A A + R
I8: ORA R A A R
I9: ANA R A A R
I10: CMA A,D A A
High-Level DDs for a microprocessor (example):
Instruction set:
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Technical University Tallinn, ESTONIA 11
Mapping Transistor Faults to Logic Level
Shortx1
x2
x3
x4
x5
y )()(* dydyy d
))(( 53241 xxxxxyd 54321 xxxxxy
Test calculation by Boolean derivative:
1
))(()(*
5432154315421
5324154321
xxxxxxxxxxxxx
d
dxxxxxdxxxxx
d
y
Generic function with defect:
Function:
Faulty function:
Technical University Tallinn, ESTONIA 12
Functional Fault Model
Example:
x1
x2
x3
y&&
x1
x2 x3
y&&
&
321
321321
)'(
)()(*
xydxx
xyxxdxxxdy
Equivalent faulty circuit:
Bridging fault causes a feedback loop:
1'/* 321 yxxxdyW d
Sequential constraints:
A short between leads xk and xl changes the combinational circuit into sequential one
t x1 x2 x3 y
1 0 1 02 1 1 1 1
Technical University Tallinn, ESTONIA 13
Structural Test Generation
Structural gate-level testing:
Path activation
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
DDD
D D
11
1
1
Fault sensitisation:
x7,1= DFault propagation:
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
x7= D = 0: x3 = 1, x4 = 1
b = 1: (already justified)
c = 1: (already justified)
1))(( 721212,753,761,7
xxxxxxxxxx
y
))(( 2,751,7213,76 xxxxxxxy Symbolic fault modeling:D = 0 - if fault is missingD = 1 - if fault is present
11
11
Test pattern
Technical University Tallinn, ESTONIA 14
Example: Test Generation with SSBDDs
&
&
&
1
&
x1
x2
x3x4
y
x1 x2 x3 x4 y
1 0 0 1 0
Testing Stuck-at-1 faults on paths:
Test pattern:
x11
x21
x12
x31
x13
x22x32
Tested faults: x211, x311, x130
x11y x21
x12 x31 x4
x13x22 x32
1
0
1
1
Technical University Tallinn, ESTONIA 15
Example: Test Generation with BDDs
&
&
&
1
&
x1
x2
x3x4
y
x1 x2 x3 x4 y
D 1 0 - D
Testing Stuck-at faults on inputs:
Test pair D=0,1:
x11
x21
x12
x31
x13
x22x32
Tested faults: x10, x11
x11y x21
x12 x31 x4
x13x22 x32
0
1x1y x2
x4 x3
x2
SSBDD:
BDD:
Technical University Tallinn, ESTONIA 16
Test generation
Test generation by using disjunctive normal forms
32143121 xxxxxxxxy
x1 x2 x1 x3 x4 x1 x2 x3 y x1 x2 x3 x40 1 0 0 1 1 1 0 0 0 1 0 11 0 1 0 1 0 0 0 0 1 0 0 10 0 0 1 1 1 0 1 0 0 0 1 11 0 1 1 0 0 0 1 0 1 0 1 01 1 1 1 0 1 1 1 No test
1 1 1 0 0 1 0 1 1 1 01 0 1 1 1 0 0 1 1 1 0 1 10 1 0 1 1 1 1 1 0 1 1
Technical University Tallinn, ESTONIA 17
Multiple Fault Testing
To test a path under condition of multiple faults, two pattern test is needed
As the result, either the faults on the path under test are detected or the masking fault is detected
Example:The lower path from b to output is
under test
A pair of patterns is applied on b There is a masking fault c 1
1st pattern: fault on b is masked
2nd pattern: fault on c is detected
&
&
10
11
1111(00)
10(11)
11
01(00)
01
0100
ab
c
d
Testing multiple faults by pairs of patterns
The possible results:
01 - No faults detected
00 - Either b 0 or c 1 detected
11 - The fault b 1 is detected
1 faults
(11)
Technical University Tallinn, ESTONIA 18
Delay Faults
Two models:
- gate delay
- path delay
Test pattern pairs: The first test initializes the circuit, and the second pattern sensitizes the fault
Robust delay test: If and only if when L is faulty and a test pair is applied, the fault is detected independently of the delays along the path
&
&
&11
&A
D
C
Bx1
x2
x3
01
11
1xxx0
1x0
0xxxx1
1
Delay fault activated, but not detected
&
&
&00
&A
D
C
Bx1
x2
x3
10
11
0xxx1
11
1xxxx0
0xxxxx1
Robust delay test
y
y
Technical University Tallinn, ESTONIA 19
Test Generation
I1: MVI A,D A IN
I2: MOV R,A R A
I3: MOV M,R OUT R
I4: MOV M,A OUT IA
I5: MOV R,M R IN
I6: MOV A,M A IN
I7: ADD R A A + R
I8: ORA R A A R
I9: ANA R A A R
I10: CMA A,D A A
Test program generation for a microprocessor (example):
Instruction set:
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
IN2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Technical University Tallinn, ESTONIA 20
Test Generation
Test program generation for a microprocessor (example):
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
IN2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Scanning test for adder:Instruction sequence I5 I1 I7 I4
for all needed pairs of (A,R)
OUT I4
A I7
A
R
I1
IN(2)
IN(1)
R I5
Time:t t - 1 t - 2 t - 3
Observation Test Load
Technical University Tallinn, ESTONIA 21
Test Generation
Test program generation for a microprocessor (example):
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
IN2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Conformity test for decoder:Instruction sequence I5 I1 D I4
for all DI1 - I10 at given A,R,IN
Data generation:
IN 0A 101DataR 110
I1, I6 IN 0I2, I3 I4, I5 A 101
I7 A + R 1011I8 A R 111I9 A R 0
Functions
I10 A 0
Data IN,A,R are generated so that the values of all functions were different
Technical University Tallinn, ESTONIA 22
Deductive Fault Simulation
&
&
1
1
1
2
3
45 a
c
b1
1
0
00
0
0
11
y
Fault list calculation:
La = L4 L5
Lb = L1 L2
Lc = L3 La
Ly = Lb - Lc
-----------------------------------------------------------
Ly = (L1 L2) - (L3 (L4 L5))
Gate-level fault list propagation
La – faults causing
erroneous signal on the node a
Ly – faults causing erroneous signal
on the output node y
Library of formulas for gates
Technical University Tallinn, ESTONIA 23
Deductive Fault Simulation
&
&
1
1
1
2
3
45 a
c
b1
1
0
00
0
0
11
y
Fault list calculated:
Ly = (L1 L2) - (L3 (L4 L5))
Solving Boolean differential equation:
Macro-level fault propagation:
)]())([())(( 5544332211 dxxdxxdxxdxxdxxydy
)(1 54321 dxdxdxdxdxdy
)()( 54321 dxdxdxdxdxdy kdx Lk
Technical University Tallinn, ESTONIA 24
Critical Path Tracing
&
&
1
1
1
2
3
45 a
c
b1
1
0
00
0
0
11
y
1 2
3 4
5
y
Problems:&
&
11
10/1
y
&
&
11
01
y
1/0
1
1
1/0
1
1
The critical path is not continuous
The critical path breaks on the fan-out
Technical University Tallinn, ESTONIA 25
Parallel Critical Path Tracing
&
1
x1
y
0110321
xxx
y
1011
1110
10011011
Detected faults vector: - 10 -
T1: No faults detectedT2: x1 1 detectedT3: x1 0 detectedT4: No faults detected
x3
x2
Handling of fanout points: • Fault simulation• Boolean differential calculus
x y
xk
x2
x1
F
))(),...,(( 11 x
xx
x
xxFy
x
y kk
Technical University Tallinn, ESTONIA 26
Combinational Fault diagnosis
F1 F2 F3 F4 F5 F6 F7
T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1
Fault F5 located
Faults F1 and F4 are not distinguishable
Fault localization by fault tables
E1 E2 E3
0 0 10 1 00 1 01 0 11 0 10 0 0
No match, diagnosis not possible
Technical University Tallinn, ESTONIA 27
Combinational Fault Diagnosis
• To reduce the cost of building a fault table, the detected faults may be dropped from simulation
• All the faults detected for the first time by the same vector produce the same column vector in the table, and will included in the same equivalence class of faults
• Testing can stop after the first failing test, no information from the following tests can be used
Minimization of diagnostic data F1 F2 F3 F4 F5 F6 F7
T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 0 0 0 0 0 1 0T4 0 0 0 0 1 0 0T5 0 0 0 0 0 0 0T6 0 0 0 0 0 0 1
With fault dropping, only 19 faults need to be simulated compared to the all 42 faults
The following faults remain not distinguishable:
{F2, F3}, {F1, F4}.
A tradeoff between computing time and diagnostic resolution can be achieved by dropping faults after k >1 detections
Technical University Tallinn, ESTONIA 28
Improving Diagnostic Resolution
Method:
• F1 may influence both outputs, F2 may influence only x8
• A test pattern 0010 activates F1 up to the both outputs, and F2 only to x8
• If both outputs will be wrong, F1 is present, and if only x8 will be wrong, F2 is present
Generating tests to distinguish faults
F1: x3,1 0
Faults are influencing on differentoutputs:
x2
x3
x4
x3,1
x3,2
x5
x6
x7
x8
1
1
1x1
0
0
1
0
F2: x4 1
Technical University Tallinn, ESTONIA 29
Improving Diagnostic Resolution
Method:
• Both faults influence the same output of the circuit
• One of them should be blocked
Two possibilities:
• A test pattern 0100 activates the fault F2. F1 is not activated: the line x3,2 has the same value as it would have if F1 were present
• A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate
Generating tests to distinguish faults
F1: x3,2 0 F2: x5,2 1
How to activate a fault without activating another one?
x5,1x5,2
x2
x3
x4
x3,1x3,2
x5
x6
x7
x8
1
1
1x1
0
1
0/1
0
Technical University Tallinn, ESTONIA 30
Sequential Fault Diagnosis
Sequential fault diagnosis by Edge-Pin Testing
T1 F1,F4,F5,F6,F7
PT2
PF1,F4
F2, F3 T3P
F3
F
F
F2
F
F5,F6,F7 T3P
F5,F7
F
F6
T4P
F7
F
F5
F1,F2
F3,F4
F5,F6
F7
F1 F2 F3 F4 F5 F6 F7
T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1
Two faults F1,F4 remain indistinguishable
Not all test patterns used in the fault table are needed
Different faults need for identifying test sequences with different lengths
The shortest test contains two patterns, the longest four patterns
Diagnostic tree:
Technical University Tallinn, ESTONIA 31
Sequential Fault Diagnosis
Guided-probe testing at the gate level
x8
No faultsP
F
x6
P
F
x4
x5,2
P
F
OR- x8 is faulty
x2
P
F
x3,1 PF
NOR- x5 is faulty
x3
P
F
Line x3,1 is faulty
Line x3 is faultyLine x2 is faulty
Line x2
is faultyF
P
x3,2
P AND- x6 is faultyF x3
P
F
Line x3,2 is faulty
Line x3 is faulty
x2
x3
x4
x3,1
x3,2
x5,1x5,2
x5
x6
x7
x8
1
1
1
Searh tree:
Faulty circuit
Technical University Tallinn, ESTONIA 32
Sequential Fault Diagnosis
Guided-probe testing at the macro-level
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
100
1 0
1
1
1
1
6 73
1
2
5
7271
y
0
1
There is a fault on the line 71
Nodes to be pinpointed: Gate level: c, e, d, 1, a, 71 (6 attempts)Macro level (DD): 1, 71 (2 attempts)
Rules on DDs:
• Only the nodes where the leaving direction coincides with the leaving direction from the DD should be pinponted• If simulation shows that these nodes cannot explain the faulty behavior they can be dropped
01