Technical Seminar Tour 2006 - Page 1 MachXO / XP / Overview Technical Seminar Tour 2007 LATTICES...
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Transcript of Technical Seminar Tour 2006 - Page 1 MachXO / XP / Overview Technical Seminar Tour 2007 LATTICES...
Technical Seminar Tour 2006 - Page 1MachXO / XP / Overview
Technical Seminar Tour 2007
LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS
Welcome to
Technical Seminar Tour 2006 - Page 2MachXO / XP / Overview
Lattice Mach4000TM
Lattice MachXOTM
Lattice MachXPTM
Jörg Siemers, TMM; Avnet-Memec
Non-volatile Solutions
Technical Seminar Tour 2006 - Page 3MachXO / XP / Overview
Mach4000
100
1000
10000
100 1000 10000 100000
I/O
Registers
LatticeXPFPGAMachXO
CrossoverispMACHCPLD
Technical Seminar Tour 2006 - Page 4MachXO / XP / Overview
ispMACH 4000 Family Overview
SuperFAST CPLD Family400 MHz fMAX and 2.5ns tPD for high-system performance
Low Static PowerFull CMOS design with static power as low as 40W (Z-type)
Low Dynamic Power1.8V core for low dynamic power consumption
Flexible ArchitectureGet designs to market fast
Flexible Solution- 32 to 512 macrocells- 3.3V, 2.5V or 1.8V supply- Commercial/Industrial/Automotive
Technical Seminar Tour 2006 - Page 5MachXO / XP / Overview
Zero Power
Flexible ArchitectureSuperFASTPerformance
ispMACH 4000 - Optimal CPLD Solutions
Mainstream CPLDs
• 1.8/2.5/3.3V Power Supply• 1.8/2.5/3.3/5V I/O• 32 to 512 Macrocells•Commercial/Industrial/ Automotive
100
200
300
400
256 512 768 1024
Density (Macrocells)
f MA
X (
MH
z)
Competition BCompetition B
LatticeCompetition ACompetition A
LatticeLatticeLeadershipLeadership
LatticeLatticeLeadershipLeadership
ORPGenericLogicBlock
I/OBlock Generic
LogicBlock
ORP
I/OBlock
ORPGenericLogicBlock
I/OBlock Generic
LogicBlock
ORP
I/OBlock
GlobalRouting
Pool(GRP)B
AN
K 0
BA
NK
1
Technical Seminar Tour 2006 - Page 6MachXO / XP / Overview
ispMACH 4000 Family
SupportsSupports
1.8, 2.5, or 3.3V 1.8, 2.5, or 3.3V
Power SupplyPower Supply
Technical Seminar Tour 2006 - Page 7MachXO / XP / Overview
ispMACH 4000 Automotive
LOCATION APPLICATION Auto PCCar Phone "Hands Free" Module Car TelevisionDashboard Lighting ControllerEmergency Calling Systems GPS Computer ModuleInternet RadioNavigation ControlVoice Recognition ModuleEngine Control ModuleFuel Injection ControllerStarter GeneratorTransmission Control Module
"In Cabin"
"Underthe
Hood"
Applications
Operation –40OC to 125OC
Highest Performance
Design Flexibility
Lowest Power Consumption
1.8, 2.5 and 3.3V I/O (with 5V Tolerance)
4000 Automotive Features4000 Automotive Features
Technical Seminar Tour 2006 - Page 8MachXO / XP / Overview
ispMACH 4000V Automotive Family
Macrocells
fMAX(MHz)tPD (ns)tCO (ns)tS (ns)
I/O
Packages
32
1687.54.54.5
30/32
44 TQFP48 TQFP
128
1687.54.54.5
64/92/96
100 TQFP128 TQFP144 TQFP
256
1687.54.54.5
64/96/128
100 TQFP
144 TQFP176 TQFP
64
1687.54.54.5
30/32/64
44 TQFP48 TQFP
100 TQFP
4128V4064V4256V4032V
Technical Seminar Tour 2006 - Page 9MachXO / XP / Overview
ispMACH 4000Z Automotive Family
Macrocells
fMAX(MHz)tPD (ns)tCO (ns)tS (ns)
I/O
Packages
32
1507.54.54.5
32
48 TQFP
128
1507.54.54.5
64/92
100 TQFP
64
1507.54.54.5
32/64
48 TQFP100 TQFP
4128Z4064Z4032Z
256
1507.54.54.5
64/128
100 TQFP176 TQFP
4256Z
Technical Seminar Tour 2006 - Page 10MachXO / XP / Overview
MachXO Crossover
100
1000
10000
100 1000 10000 100000
I/O
Registers
LatticeXPFPGAMachXO
CrossoverispMACHCPLD
Technical Seminar Tour 2006 - Page 11MachXO / XP / Overview
MACHXOMACHXO
ReconfigurableReconfigurable
Non-VolatileNon-Volatile
FLASHFLASH
SRAMSRAM
Bringing the BestTogether
FPGAswithout Compromise
Technical Seminar Tour 2006 - Page 12MachXO / XP / Overview
Fujitsu Technology PartnershipG
eo
me
try
Time
130nmLogic
130nmFlash + Logic
Proven 130nm and 90nm Industry Leading 130nm Flash 300mm Fab for Lower Costs 65nm Development Underway
90nmLogic
65nmLogic
Fujitsu & Lattice Bringing the Best
Together
1.2-volt core 1.2-volt core
Technical Seminar Tour 2006 - Page 13MachXO / XP / Overview
MachXO Brings the Best Together
Attribute CPLD FPGA MachXO
High Pin-to-Pin Speed Fast Wide Logic High I/O to Logic Ratio Instant-On Register Intensive Distributed & Embedded Memory
MachXO Brings Together CPLD and FPGA Attributes to Optimally Serve Traditional CPLD Applications
Technical Seminar Tour 2006 - Page 14MachXO / XP / Overview
MachXO Key Features
Non-Volatile Solution– Single chip, instant-on, high security
TransFR™ (TFR) Technology – Simplifies in-field logic updates
High Performance– 3.5n pin-to-pin*
LUT Based Flexibility– 256 to 2,280 (LUT4s)– 2K to 8K bits distributed memory
I/O Intensive– 78 to 271 I/O
Flexible sysIOTM Buffers– LVCMOS 33/25/18/15/12, LVDS**, PCI**
sysMEMTM Block Memory **– Up to 28K bits of memory
sysCLOCKTM PLLs**
On Board Oscillator ~20MHz
1.2/1.8/2.5/3.3V Power Supply Options
– Low standby power (2mA @ 640 LUTs)
LUT Flexibility
Embedded Memory
Non-volatility
Performance
Technical Seminar Tour 2006 - Page 15MachXO / XP / Overview
MachXO Block Diagram (1200 and 2280)
sysMEM Block RAM 9kbit Dual Port
sysCLOCK PLLsFrequency Synthesis
& Clock Alignment
sysIO Buffers Support LVCMOS/LVTTL,
LVDS and PCI
Programmable Function Units (PFUs)
(with RAM)
Flexible RoutingOptimized for Speed, Cost
and Routability
Programmable Function Units (PFFs)
(without RAM)
JTAG Port
Technical Seminar Tour 2006 - Page 16MachXO / XP / Overview
MachXO Block Diagram (640 and 256)
Flexible RoutingOptimized for Speed, Cost and Routability
JTAG Port
Four banks of sysIO Buffers Support LVCMOS/LVTTL
Programmable Function Units (PFUs)
(with RAM)
Programmable Function Units (PFFs)
(without RAM)
MachXO 640
Two banks of sysIO Buffers Support LVCMOS/LVTTL
MachXO 256
Technical Seminar Tour 2006 - Page 17MachXO / XP / Overview
MachXO Configuration Options
• Flash Configures Logic, Interconnect and Block RAM for User PROMs
• TransFR (TFR) Technology Simplifies In-Field Logic Updates
SR
AM
Co
nfi
g.
Bit
s (
Co
ntr
ol
De
vic
e O
p.)
FLASH MEMORY
Control Logic
JTAGPort
Massively Parallel Wide Data Transfer
ProvidesFast SRAM Configuration from FLASH “Instant-on”
On Chip FLASH Single Chip Solution
Excellent Security
Infinitely Reconfigure SRAM Through JTAG
Reprogram FLASH Through JTAG Port
MachXO
Technical Seminar Tour 2006 - Page 18MachXO / XP / Overview
MachXO Simplifies In-Field Logic Updates
Requirement
Embedded Programming
Minimum Downtime
I/O States Preserved
Device State Controlled
MachXO withTransFR (TFR)
Technology
ispVM Embedded
Background Program
Update SRAM <1mS
XFLASH TransFRispVM CommandControls I/O& Device State
Transparent Field Reconfiguration (TransFR)
Technical Seminar Tour 2006 - Page 19MachXO / XP / Overview
sysIO Interfaces
sysIO Buffer Supports Multiple I/O Standards
– LVTTL, LVCMOS 33/25/18/15/12
– PCI*
– LVDS*, BLVDS**, LVPECL**
Up to 8 I/O Banks For Flexibility in I/O Placement
Hotsocketing – Input leakage less than 1mA
during power-up/power-down
– Power supplies can be sequenced in any order
Programmable Slew Rate
Programmable Drive Strength– 4 to 20mA (3.3-volts)
– 4 to 20mA (2.5-volts)
– 4 to 16mA (1.8-volts)
– 4 to 8mA (1.5-volts)
– 2 to 6mA (1.2-volts)
Programmable Pull-up, Pull-down, Bus-friendly
Programmable Open Drain
PAD
TO
Programmable delay element
Inputdata signal
Output data
Fast output data signal
GOE
DO
OE
Output data
* MachXO 1200 and 2280** MachXO 1200 and 2280 with external resistors
Technical Seminar Tour 2006 - Page 20MachXO / XP / Overview
sysMEM Block RAM
Configurable Width and Depth
Single Port, Dual Port , Pseudo-dual Port, FIFO and ROM Modes
FIFO Logic Included in EBR
EBRAD[12:0]
CLKCE
DO[35:0]
EBR
AD[12:0]
DI[35:0]CLKRSTWE
CS[2:0]
DO[35:0] EBR
ADA[12:0]DIA[17:0]
CLKARSTAWEA
CSA[2:0]DOA[17:0]
ADB[12:0]DIB[17:0]CLKBRSTBWEBCSB[2:0]DOB[17:0]
EBRRAD[12:0]RD[35:0]RCERCLK
WAD[12:0]
WD[35:0]WCLKWCE
WERST
ROM
RAM(Single Port)
RAM(Dual Port)
RAM(Pseudo Dual Port)
Provides 9,216 Bit Blocks
275MHz Operation
Efficient Implementation of Buffers
Single Port Dual PortPseudo Dual Port
FIFO
8,192 X 1 8,192 X 1 8,192 X 1 8,192 X 14,096 X 2 4,096 X 2 4,096 X 2 4,096 X 22,048 X 4 2,048 X 4 2,048 X 4 2,048 X 41024 X 9 1024 X 9 1024 X 9 1024 X 9512 X 18 512 X 18 512 X 18 512 X 18256 X 36 256 X 36 256 X 36
EBR
DI[35:0]
CLKWRSTA
WECEW
CLKRRSTBRERCE
DO[35:0]
FFAFEFAE
FIFO
Technical Seminar Tour 2006 - Page 21MachXO / XP / Overview
sysCLOCK PLL
• Frequency: 25MHz - 420 MHz– VCO Frequency 420-840 MHz
• Low Output Period Jitter: ~ +-120ps• Programmable Phase /Duty Cycle (45 Degree Steps)• Dynamic Delay Adjust
– Increments of 250ps with a total of 2ns lead or 2ns lag
Divider (1-12)
PLLDivider
(2,4, , 24)
Divider (1-12)
Phase & Duty SelectAdjust
DelayCLOCK IN
(From pin or routing)
CLOCK OUT
CLOCK OUT
LOCK
CLOCK OUT
Dynamic Delay Adjust
0.25ns Steps+/- 2ns Range
Feedback(From post scalar
divider, clock net or external pin)
Divider (2,4, ,128)
Technical Seminar Tour 2006 - Page 22MachXO / XP / Overview
Multiple Power Supply Options
Use C Version to Access Latest Technology Without Adding New Power Supplies to Board
– Improve performance and power consumption
– Allows single supply operation from 3.3-volts
Use E Version to Minimize Power Consumption– 64% lower power than operation at 3.3-volts
Lower Voltage (E) Version
VCCVCCP VCCAUX VCCJ
VCCIO
1.2 to 3.3V forChosen I/O Std.1.2 Volts 3.3 Volts
Upper Voltage (C) Version
VCCVCCP VCCAUX VCCJ
VCCIO
1.2 to 3.3V forChosen I/O Std.3.3/2.5/1.8 Volts 3.3 Volts
Internal logic operates at 1.2-volts Internal logic operates at 1.2-volts
MachXO MachXO
Technical Seminar Tour 2006 - Page 23MachXO / XP / Overview
Sleep Mode Reduces Power by Factor of 1000
Mode
Characteristic Normal Off Sleep
SLEEPN Pin High X Low
Static Icc Typical <100mA 0 Typical <100uA
Power Supplies Normal Range Off Normal Range
Logic Operation User Defined Non Operational Non Operational
I/O Operation User Defined Tri-State Tri-State
LatticeXOSLEEPN
Pin
DeviceState
Normal Sleep Mode Normal
Typical 100nS Typical 1mS
Note: Sleep Mode is only available on 1.8/2.5/3.3V “C” version
Technical Seminar Tour 2006 - Page 24MachXO / XP / Overview
MachXO Benefits
Self-Configuration in Under A Millisecond• Instant-On ideal for system “heartbeat” control logic• Supports configuration “scrubbing” for SEU control• Supports rapid power cycling
High Security• Security bits prevent readback• No exposed power-up bitstream
Single Chip• Simplify design• Reduced PCB footprint• Save boot PROM costs
SRAM + FLASH• TransFR (TFR) technology
enables in field updates while system operates
On-Chip Regulation• Support legacy applications
with latest technology- Reduce costs- Improve performance
3 . 3 , 2 . 5 , 1 . 8 o r 1 . 2 V
3 . 3 , 2 . 5 , 1 . 8 o r 1 . 2 V
Technical Seminar Tour 2006 - Page 25MachXO / XP / Overview
MachXO Family Members
Device LCMXO 256 LCMXO 640 LCMXO 1200 LCMXO 2280LUTs 256 640 1200 2280Distributed RAM (KBits) 2 6.1 6.4 7.7
EBR SRAM (KBits) 0 0 9.2 27.6# EBR SRAM Blocks (9Kb) 0 0 1 3VCC Voltage
Number of PLLs 0 0 1 2Max I/O 78 159 211 271Packages: 100-TQ (14X14) 78 74 73 73 144-TQ (20X20) 113 113 113 csBGA 100 (8X8) 78 74 csBGA 132 (8X8) 101 101 101 fpBGA 256 (17X17) 159 211 211 fpBGA 324 (19X19) 271
1.2/1.8/2.5/3.3V
Technical Seminar Tour 2006 - Page 26MachXO / XP / Overview
LUTs
sysMEM Blocks (9Kbits)sysMEM EBR RAM (bits)Distributed RAM (k bits)
sysCLOCK PLLsGlobal Clocks
I/O Type
Pb-Free Packages / IO100 TQFP144 TQFP256 ftBGA324 ftBGA
Availability(E = 1.2V)
(C = 3.3/2.5/1.8V)
LAMXO
256LAMXO
1200LAMXO
640LAMXO
2280
640
00
6.1
04
LVCMOS
74113159
256
00
2.0
04
LVCMOS
78
LA-MachXO Family
1200
192166.4
24
LVCMOSPCI
LVDS
73113211
No Plan1
2280
327648
7.7
24
LVCMOSPCI
LVDS
73113211271
No Plan1
1. Due to thermal consideration.
Technical Seminar Tour 2006 - Page 27MachXO / XP / Overview
MachXO Summary
MachXO Offers a Unique Combination of Flash and SRAM Technology to Deliver Non-Volatile, In-System Reconfigurable Logic
MachXO Offers an Extremely Cost-Effective Alternative to High-End CPLDs and Low-End FPGAs with the Best Features of Both
Applications for MachXO Span All Market Segments and Electronic Systems
The Combination of LatticeEC/ECP/XP FPGAs and MachXO Gives Lattice the Broadest Portfolio of Low-Cost FPGAs Available
Technical Seminar Tour 2006 - Page 28MachXO / XP / Overview
XP - non volatile FPGA Family
100
1000
10000
100 1000 10000 100000
I/O
Registers
LatticeXPFPGAMachXO
CrossoverispMACHCPLD
Technical Seminar Tour 2006 - Page 29MachXO / XP / Overview
ispXPispXP
ReconfigurableReconfigurable
Non-VolatileNon-Volatile
FLASHFLASH
SRAMSRAM
Bringing the BestTogether
FPGAswithoutCompromise
Technical Seminar Tour 2006 - Page 30MachXO / XP / Overview
Fujitsu Technology PartnershipG
eo
me
try
Time
130nmLogic
130nmFlash +Logic
Proven 130nm and 90nm Industry Leading 130nm Flash 300mm Fab for Lower Costs 65nm Development Underway
90nmLogic
65nmLogic
Fujitsu & Lattice Bringing the Best
Together
1.2-volt core 1.2-volt core
Technical Seminar Tour 2006 - Page 31MachXO / XP / Overview
LatticeXP FPGA Key Features
Non-Volatile Reconfigurable
Low Cost Solution – Optimized architecture– 0.13um Flash process
Wide Density & I/O Selection– 3k to 20k LUTs– 62 to 340 I/Os
Embedded & Distributed Memory– 12kbits to 79kbits distributed in LUTs– 54kbits to 414kbits embedded block
High Performance (225MHz+)
sysIO™ Interface Support – LVCMOS, LVTTL, PCI, LVDS, SSTL,
HSTL
333Mbps DDR Memory Interfaces
sysCLOCK™ PLLs
Two Core Power Supply Versions– C = 1.8, 2.5, 3.3V Support– E = 1.2V Support
Non-Volatile
Flexible LUT-Based
Reconfigurable
“No Compromise”
Technical Seminar Tour 2006 - Page 32MachXO / XP / Overview
ispXP FLASH MemoryInstant-on, Secure and
Single-chip
LatticeXP: Added Non-Volatility
JTAG
sysMEMTM Block RAM9kbit Dual Port
Optimized sysIOTM Buffers Support Mainstream I/O: LVCMOS/LVTTL, LVDS,
SSTL, HSTL, DDR Memory Interfaces
sysCLOCKTM PLLsFrequency Synthesis &
Clock Alignment
Optimized Programmable Function Units (PFUs)
25% – Logic + RAM75% – Logic Only
Flexible RoutingOptimized for Speed, Cost
and Routability
Technical Seminar Tour 2006 - Page 33MachXO / XP / Overview
LatticeXP Configuration OptionsS
RA
M C
on
fig
ura
tio
n B
its
(Co
ntr
ol
De
vic
e O
pe
rati
on
)
FLASH MEMORY
FLASH MEMORY
Control Logic
Control Logic
sysCONFIGPort
JTAGPort
Parallel sysCONFIG™ to Configure SRAM or
Program FLASH
Serial JTAG Port(IEEE 1532/1149.1)
to Configure SRAM or Program FLASH
On Chip Non-Volatile Single Chip Solution
Excellent Security
Massively Parallel Data Transfer & Multiple Blocks Provide Secure and Fast
SRAM Configuration “Instant-on”
Flash Configures Logic, Interconnect and Block RAM for User PROMs
Background Flash Programming Support- Upgrade system remotely
Leave-Alone I/O- Control I/O state while refreshing
Technical Seminar Tour 2006 - Page 34MachXO / XP / Overview
Background Programming With LatticeXP
Background Programming of Flash Occurs While the Device is in Normal Operation
Power Cycle or Apply a Refresh Command
New/Updated Configuration Takes Control
Logic operatesbased on
SRAM configuration
#1FL
AS
H (
#1
#2)
FLASH ProgrammingDuring Device Operation
Program configuration #2
to FLASH via sysCONFIG or
JTAG ports
Logic operatesbased on
SRAM configuration
#2
FL
AS
H (
#2)
Reload SRAM at Power-up or User Command
Technical Seminar Tour 2006 - Page 35MachXO / XP / Overview
XP10 Programming Times
SRAM Configuration– From FLASH 2ms
– Via sysCONFIG 11ms
– Via JTAG 100mS
FLASH Programming* – Via JTAG 2 Seconds
– Via sysCONFIG 2 Seconds
ispXPispXP
ReconfigurableReconfigurable
Non-VolatileNon-Volatile
* Programming time. Erase approximately 10 seconds
Technical Seminar Tour 2006 - Page 36MachXO / XP / Overview
LatticeXP Wake-up Time
LatticeXP Logic is Available 1mS After Power Good -- Supports “Instant-on” Application Requirements --
XP
Ad
van
tag
eAltera
Lattice0
20
40
60
80
100
120
140
EP1C12 XC3S1000 XP10
Wa
ke
-up
Tim
e (
mS
)
Fastest serial configuration
Xilinx
Technical Seminar Tour 2006 - Page 37MachXO / XP / Overview
LatticeXP Integrates Multiple Components
FPGAData Pathfunction
Microprocessor
CPLDPower up logic
FPGA boot logic and bus decode
Pro
cessor A
dd
ress and
Da
ta Bu
sses
Microprocessor
Pro
cessor A
dd
ress and
Da
ta Bu
sses
Voltage Regulator
Technical Seminar Tour 2006 - Page 38MachXO / XP / Overview
LatticeXP FPGAs Secure Your Design
FPGA Security Important Due To Multiple Threats
– Reverse engineering– Cloning– Overbuilding– Theft of service
LatticeXP Security Scheme Allows Devices To Be Locked
– Secures SRAM and FLASH– Erasing memory is only
allowable operation– 0.13um technology and 8
metal layers makes probing next to impossible
Specify Secure Mode in ispLEVER or ispVM
0110110100111010010101
0110
1101
001
0100101
SRAM FPGAs Expose Your Intellectual Property At Power Up
LatticeXP FPGAs Secure Your Design
Technical Seminar Tour 2006 - Page 39MachXO / XP / Overview
Optimized PFU Logic Block
Industry-standard 4-input LUT Structure– Combine multiple LUTs for larger functions
– Carry Chain for arithmetic speed
SLICE 0LUT4
LUT4
FF
FF
SLICE 1LUT4
LUT4
FF
FF
SLICE 2LUT4
LUT4
FF
FFFrom
RoutingTo
Routing
SLICE 3LUT4
LUT4
FF
Carry Chain
Carry Chain
Logic Block (PFU)
LUTs Used As Distributed MemoryF
req
ue
nc
y o
f U
sa
ge
(>2
50
De
sig
ns
)
0% 50%
Spartan3 50% Distributed
Memory Incurs Unnecessary Die
Cost
Cyclone 0% Distributed
Memory ImpactsLogic Efficiency
Optimized LatticeXP
Devices Support 25% Distributed
Memory
10% LUTs Needed for Distributed Memory
on Average
Optimized Architecture Delivers Uncommon Value
FF
Technical Seminar Tour 2006 - Page 40MachXO / XP / Overview
sysMEM Block RAM
Single Port Dual PortPseudo-
Dual Port
8,192 X 1 8,192 X 1 8,192 X 1
4,096 X 2 4,096 X 2 4,096 X 2
2,048 X 4 2,048 X 4 2,048 X 4
1,024 X 9 1,024 X 9 1,024 X 9
512 X 18 512 X 18 512 X 18
256 X 36 256 X 36
Configurable Width and Depth
Single Port, Dual Port , Pseudo-dual Port and ROM Modes
Port Width Matching
FIFO with surrounding logicEBRAD[12:0]
CLKCE
DO[35:0]
EBR
AD[12:0]
DI[35:0]CLKRSTWE
CS[2:0]
DO[35:0] EBR
ADA[12:0]DIA[17:0]
CLKARSTAWEA
CSA[2:0]DOA[17:0]
ADB[12:0]DIB[17:0]CLKBRSTBWEBCSB[2:0]DOB[17:0]
EBRRAD[12:0]RD[35:0]RCERCLK
WAD[12:0]
WD[35:0]WCLKWCE
WERST
ROM
RAM(Single Port)
RAM(Dual Port)
RAM(Pseudo Dual Port)
Provides 9,216 Bit Blocks
250MHz Operation
Multiple Blocks per Device
Technical Seminar Tour 2006 - Page 41MachXO / XP / Overview
sysCLOCK PLL
Frequency Range 25 to 375MHz VCO range 420 to 750MHz
Analog PLL Technology Low Output Period Jitter (+/- 125ps) Programmable Phase / Duty Cycle (45 degree steps) Programmable Dividers Internal and External Feedback
Feedback Divider
(CLKFB)
PLL
Post Scalar Divider
(CLKOP)
Input Clock Divider (CLKI)
Phase & Duty Select
Secondary Clock
Divider (CLKOK)
AdjustDelay
CLOCK IN(From pin or
routing)CLOCK OUT
CLOCK OUT
LOCK
CLOCK OUT
Dynamic Delay Adjust
0.25ns Steps+/- 2ns Range
Feedback(From post scalar
divider, clock net or external pin)
Technical Seminar Tour 2006 - Page 42MachXO / XP / Overview
DQS Delay and Transition Detect*
PIO A
Tri-stateRegister Block(2 Flip/flops)
Input
PIC
PIC
High performance sysIO Buffer(700 Mbps)
2-FF Output & Tri-state Structure
Allows Easy DDR Implementation
Dedicated Circuitry Simplifies DDR
Memory Implementations(up to 333Mbps)
8 I/O Banks Allows Flexible I/O
Implementation
OutputRegister Block(2 Flip/flops)
InputRegister Block(5 Flip/flops)
ControlSelect
PIO B (Detail Not Shown)
5-Flip Flop Input Structure Allows
Easy DDR Implementation (Including clock domain transfer)
* Selected blocks
Technical Seminar Tour 2006 - Page 43MachXO / XP / Overview
I/O Banking Scheme
Eight I/O Banks Per Device
Output Standard Support Dependent on VCCIO
Referenced Inputs Dependent on VREF
LVCMOS Inputs– 12, 25 & 33 independent of
VCCIO
– 15 & 18 dependent on VCCIO
Multiple Compatible I/O Standards In A Bank
VREF1(2)
GND
Ba
nk
2
VCCIO2
VREF2(2)
VREF1(3)
GND
Ba
nk
3
VCCIO3
VREF2(3)
VREF1(7)
GND
Ba
nk
7
VCCIO7
VREF2(7)
VREF1(6)
GND
Ba
nk
6
VCCIO6
VREF2(6)
VR
EF
1(5)
GN
D
Bank 5
V CC
IO5
VR
EF
2(5)
V RE
F1(
4)
GN
D
Bank 4
VC
CIO
4
VR
EF
2(4)
VR
EF
1(0)
GN
D
Bank 0
VC
CIO
0
VR
EF
2(0)
VR
EF
1(1)
GN
D
Bank 1
VC
CIO
1
VR
EF
2(1)
Technical Seminar Tour 2006 - Page 44MachXO / XP / Overview
DDR Memory Interfaces
DDR DRAM is the Low-Cost Memory of Choice
– >50% of 2004 Total DRAM Bits
DDR Memory Interface Issues– Bi-directional DQ & DQS
– Tight timing specifications
– Clock domain transfers
– Muxing/de-muxing data
LatticeXP Pre-Engineered DDR Interfaces
Precision DQS Delay Control (Temp. & Voltage-Compensated)
Dedicated DDR Registers (Fast Muxing/Demuxing) Automatic DQS to System Clock Domain Transfer
Half Clock Transfer High-Performance 166MHz
333Mbps
Exceptional DDR Performance
Automatic Clock Transfer Circuitry Simplifies Design & Ensures Robust
Operation
DDR to SDRDe-mux
Half Clock Transfer
DLL Calibrated DQS to DQ Alignment
DQS
Data
DQS
Clock
DDRCLKPOL
DQS Delay Block*
Clock Polarity Select*
Input Logic Block
* Selected Input Logic Blocks
Technical Seminar Tour 2006 - Page 45MachXO / XP / Overview
Multiple Power Supply Options
Use C Version to Access Latest Technology Without Adding New Power Supplies to Board
– Improve performance and power consumption
– Allows single supply operation from 3.3-volts
Use E Version to Minimize Power Consumption– 64% lower power than operation at 3.3-volts
Lower Voltage (E) Version
VCCVCCP VCCAUX VCCJ
VCCIO
1.2 to 3.3V forChosen I/O Std.1.2 Volts 3.3 Volts
Upper Voltage (C) Version
VCCVCCP VCCAUX VCCJ
VCCIO
1.2 to 3.3V forChosen I/O Std.3.3/2.5/1.8 Volts 3.3 Volts
Internal logic operates at 1.2-volts Internal logic operates at 1.2-volts
Technical Seminar Tour 2006 - Page 46MachXO / XP / Overview
Sleep Mode Reduces Power by Factor of 1000
Mode
Characteristic Normal Off Sleep
SLEEPN Pin High X Low
Static Icc Typical <100mA 0 Typical <100uA
Power Supplies Normal Range Off Normal Range
Logic Operation User Defined Non Operational Non Operational
I/O Operation User Defined Tri-State Tri-State
LatticeXP
SLEEPN Pin
DeviceState
Normal Sleep Mode Normal
Typical 100nS Typical 2mS
Note: Sleep Mode is only available on 1.8/2.5/3.3V “C” version
Technical Seminar Tour 2006 - Page 48MachXO / XP / Overview
LatticeXP Benefits
Self-Configuration in Under A Millisecond• Ideal for system “heartbeat” control logic• Supports configuration “scrubbing” for SEU control• Supports rapid power cycling
High Security• Security bits prevent readback• No exposed power-up bitstream
Single Chip• Simplify design• Reduced PCB footprint• Save boot PROM costs
SRAM + FLASH• Real time programming of
device during operation
On-Chip Regulation• Support legacy applications
with latest technology- Reduce costs- Improve performance
3 . 3 , 2 . 5 , 1 . 8 o r 1 . 2 V
3 . 3 , 2 . 5 , 1 . 8 o r 1 . 2 V
Technical Seminar Tour 2006 - Page 49MachXO / XP / Overview
LatticeXP Family
Device XP3 XP6 XP10 XP15 XP20LUTs (K) 3.1 5.8 9.7 15.4 19.7
sysMEM Blocks 6 10 24 32 46
sysMEM (Kbits) 54 90 216 288 414
Distributed RAM (Kbits) 12 23 39 61 79
Voltage (V) 1.2/1.8/2.5/3.3V
PLLs 2 2 4 4 4
Package I/O Combinations
100-pin TQFP (14x14mm) 62
144-pin TQFP (20x20mm) 100 100
208-pin PQFP (28x28mm) 136 142
256-ball fpBGA (17x17mm) 188 188 188 188
388-ball fpBGA (23x23mm) 244 268 268
484-ball fpBGA (23x23mm) 300 340
Technical Seminar Tour 2006 - Page 50MachXO / XP / Overview
LatticeXP Value Proposition
Non-Volatile FPGA– Single Chip– High Security– Instant-On
Mainstream LUT-based Architecture
Optimized Device Provides Low Cost Solution– Manufacturable 130nm silicon process
Best DDR Memory Support– Easy design of 333Mbps interfaces
Popular Packaging Options– TQFP, PQFP, fpBGA– RoHS / Lead-Free available
Combines the Best of Non-Volatile & SRAM -- No Compromise FPGA!
Technical Seminar Tour 2006 - Page 51MachXO / XP / Overview
Lattice Product Families
Density
100
1000
10000
100 1000 10000 100000
I/O
LatticeECP/2/XP/FPGAMachXO
CrossoverispMACHCPLD
LatticeSCSystem Chip
Technical Seminar Tour 2006 - Page 52MachXO / XP / Overview
Technical Seminar Tour 2006 - Page 53MachXO / XP / Overview
LatticeSC Architecture
High Performance FPGA Fabric 4 to 32 SERDES
(Up to 3.4Gbps) with
Physical Coding Sublayer
(PCS)
15K to 115K LUT4s
System-Level
Features:
Embedded
System Bus /
Dedicated
Microprocessor
Interface / SPI
Flash
Configuration
2Gbps PURESPEED I/O
Up to 7.8 Mbits of Embedded
Memory Blocks
MACO: Embedded Structured ASIC
Blocks
(LatticeSCM
Devices) 8 Analog PLLs /
12 DLLs per Device
1.0V-1.2V Operating
Voltage
Technical Seminar Tour 2006 - Page 54MachXO / XP / Overview
Masked Array for Cost Optimization
Multiple 90nm Embedded 50K ASIC Blocks
Ample FPGA-to-ASIC Signal Connectivity
Ample ASIC-to-IO Connectivity
High-speed Clock Connectivity
Technical Seminar Tour 2006 - Page 55MachXO / XP / Overview
MACO: Standard Offerings
LatticeSCM25
EMBC
D
EMBA B
PLC Array
EMBE
EMBMACO MACOSE
RD
ES
Qu
ad
SE
RD
ES
Qu
ad
SE
RD
ES
Qu
ad
SE
RD
ES
Qu
ad
F
A A
B B
C C C
Block IP Type
KLUTs forSoft IP
KLUTs for MACODesign
Blocks on
SCM15
Blocks on
SCM25
Blocks on
SCM40
Blocks on
SCM80
Blocks on
SCM115flexiMAC 1GbE 2.7 0flexiMAC 10GbE 6 0flexiMAC PCIe 11 4 to 7Memory Controller DDR1/2
2 0
Memory Controller QDR2
2 0
Memory Controller RLDRAM
3 0
C SPI4.2 6 0.8 1 2 2 2 2
A
B
1
1
2
2
2
2
2
2
4
2
Technical Seminar Tour 2006 - Page 56MachXO / XP / Overview
LatticeSC(M) Family
Device SC15 SC25 SC40 SC80 SC115
LUTs (K) 15.2 25.4 40.4 80.1 115.2
sysMEM Blocks (18Kb) 56 104 216 308 424
Embedded Memory (Mbits) 1.03 1.92 3.98 5.68 7.8
Distributed Memory (Mbits) 0.24 0.41 0.65 1.28 1.84
3.4Gbps SERDES 8 16 16 32 32
PLLs / DLLs 8 / 12 8 / 12 8 / 12 8 / 12 8 / 12
MACO Blocks* 4 6 10 10 12
Package I/O + SERDES Combinations (1mm Ball Pitch)
256-ball fpBGA (17x17) 139+4
900-ball fpBGA (31x31) 300+8 378+8
1020-ball ffBGA (33x33) 484+16 562+16
1152-ball fcBGA (35x35) 660+16 660+16
1704-ball fcBGA (42.5x42.5) 904+32 942+32
*Maximum Number of 50K Gate MACO Blocks. MACO Enabled Only on LatticeSCM Family
Technical Seminar Tour 2006 - Page 57MachXO / XP / Overview
ispLEVER® Design Tools
OEM Tools integrated:
•Mentor Graphics Precision•Synplicity Synplify•Model Technologie ModelSim
Technical Seminar Tour 2006 - Page 59MachXO / XP / Overview
ispLEVER Configuration Options
Device Support Synthesis Support
Simulation License Type
ispLEVER - Stand-Alone Compiler
All Lattice Programmable Logic: All Devices n/a n/a Floating (UNIX/LINUX)Node Locked or Floating (PC)
Includes Lattice device libraries to work with 3rd party EDA environments. (PC, UNIX)
ispLEVER Base HDL All Devices Mentor Precision
2005b Synplicity Synplify 8.2h
ModelSim 6.1a
Lattice Functional Simulator
Node Locked or Floating
ispLEVER Starter New / Focus CPLD,MachXO, XPGA,GDXEC, ECP, XP3-XP6
Mentor Precision
2005b Synplicity Synplify 8.2h
Lattice Functional Simulator
Node Locked: 6-Month Trial
Intended for evaluation, and student users, ispLEVER Starter is a complete solution that can take your design from concept through device programming. (PC)
Free SW
Für SeminarTeilnehmer:
295€
Technical Seminar Tour 2006 - Page 60MachXO / XP / Overview
ispTRACY Debugging Environment
isp
LA
isp
LA
isp
JTA
G
usercircuity
ispTRACY Logic Analyzersoftware tool
running on host PC
isp Cable
FPGA
User Target Board with one or morethan one FPGA in the JTAG chain
Technical Seminar Tour 2006 - Page 61MachXO / XP / Overview
Lattice IP Support
PCI
DDR I
1GB Ethernet MAC
10/100 Ethernet MAC
QDR II
SDRAM
DMA
I2C
….. and more see
www.latticesemi.com
Evaluation Board Allows Many IPs to Be Checked Out In The Lab
Technical Seminar Tour 2006 - Page 62MachXO / XP / Overview
JumpIn2Practice by eVision Systems
Get your ideas into the market, FAST
- FPGA relevant Training content
- All tutorials based on ispLEVER
- Support you with BASIC and ADVANCED Course
- Training Material that will become your day to day working book for the future
YOUR SUCCESS IS OUR MISSION
Technical Seminar Tour 2006 - Page 63MachXO / XP / Overview
JumpIn2Practice
About eVision Systems- independent EDA Company based in the Munich area
- VHDL, Verilog and SystemC Tools
- RFIC & MICROWAVE Design Tools
- Technical Support Team
- Training Services
- Own HDL Design Experience
www.evision-systems.de
www.jumpin2practice.de