Technical Reference Manual - Farnell element14 · CC13xx, CC26xx SimpleLink™ Wireless MCU...

CC13xx, CC26xx SimpleLink™ Wireless MCU

Technical Reference Manual

Literature Number: SWCU117DFebruary 2015–Revised September 2015

Contents

Revision History: SWCU117D ....................................................................................................... 10Revision History: SWCU117C ....................................................................................................... 10Revision History: SWCU117B ....................................................................................................... 10Revision History: SWCU117A ....................................................................................................... 11Preface....................................................................................................................................... 121 Architectural Overview........................................................................................................ 14

1.1 Target Applications......................................................................................................... 151.2 Overview..................................................................................................................... 151.3 Functional Overview ....................................................................................................... 17

1.3.1 ARM Cortex-M3 ................................................................................................... 171.3.2 On-chip Memory................................................................................................... 181.3.3 Radio................................................................................................................ 191.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key Support ................................. 191.3.5 General-Purpose Timers ......................................................................................... 201.3.6 Direct Memory Access............................................................................................ 201.3.7 System Control and Clock ....................................................................................... 211.3.8 Serial Communication Peripherals .............................................................................. 211.3.9 Programmable I/Os ............................................................................................... 241.3.10 Sensor Controller ................................................................................................ 241.3.11 Random Number Generator .................................................................................... 251.3.12 cJTAG and JTAG ................................................................................................ 251.3.13 Power Supply System ........................................................................................... 26

2 The Cortex-M3 Processor .................................................................................................... 282.1 The Cortex-M3 Processor Introduction .................................................................................. 292.2 Block Diagram .............................................................................................................. 292.3 Overview..................................................................................................................... 30

2.3.1 System-level Interface ............................................................................................ 302.3.2 Integrated Configurable Debug.................................................................................. 302.3.3 Trace Port Interface Unit ......................................................................................... 312.3.4 Cortex-M3 System Component Details......................................................................... 31

2.4 Programming Model ....................................................................................................... 312.4.1 Processor Mode and Privilege Levels for Software Execution .............................................. 322.4.2 Stacks............................................................................................................... 322.4.3 Exceptions and Interrupts ........................................................................................ 322.4.4 Data Types ......................................................................................................... 32

2.5 Cortex-M3 Core Registers ................................................................................................ 332.5.1 Core Register Map ................................................................................................ 342.5.2 Core Register Descriptions ...................................................................................... 34

2.6 Instruction Set Summary .................................................................................................. 472.7 Cortex-M3 Processor Registers .......................................................................................... 51

2.7.1 CPU_DWT Registers ............................................................................................. 512.7.2 CPU_FPB Registers .............................................................................................. 772.7.3 CPU_ITM Registers............................................................................................... 882.7.4 CPU_SCS Registers ............................................................................................ 128

2 Contents SWCU117D–February 2015–Revised September 2015Submit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SWCU117D

www.ti.com

2.7.5 CPU_TPIU Registers............................................................................................ 2073 Cortex-M3 Peripherals ....................................................................................................... 220

3.1 Cortex-M3 Peripherals Introduction .................................................................................... 2213.2 Functional Description.................................................................................................... 221

3.2.1 SysTick ............................................................................................................ 2223.2.2 NVIC............................................................................................................... 2223.2.3 SCB................................................................................................................ 2233.2.4 ITM................................................................................................................. 2243.2.5 FPB ................................................................................................................ 2243.2.6 TPIU ............................................................................................................... 2243.2.7 DWT ............................................................................................................... 2253.2.8 Cortex-M3 Memory .............................................................................................. 226

4 Interrupts and Events ........................................................................................................ 2284.1 Exception Model .......................................................................................................... 229

4.1.1 Exception States ................................................................................................. 2294.1.2 Exception Types ................................................................................................. 2294.1.3 Exception Handlers .............................................................................................. 2324.1.4 Vector Table ...................................................................................................... 2324.1.5 Exception Priorities .............................................................................................. 2334.1.6 Interrupt Priority Grouping ...................................................................................... 2334.1.7 Exception Entry and Return .................................................................................... 234

4.2 Fault Handling............................................................................................................. 2364.2.1 Fault Types ....................................................................................................... 2364.2.2 Fault Escalation and Hard Faults .............................................................................. 2374.2.3 Fault Status Registers and Fault Address Registers........................................................ 2374.2.4 Lockup............................................................................................................. 237

4.3 Event Fabric ............................................................................................................... 2384.3.1 Introduction ....................................................................................................... 2384.3.2 Event Fabric Overview .......................................................................................... 239

4.4 AON Event Fabric ........................................................................................................ 2394.4.1 Common Input Event List....................................................................................... 2404.4.2 Event Subscribers ............................................................................................... 240

4.5 MCU Event Fabric ........................................................................................................ 2414.5.1 Common Input Event List....................................................................................... 2414.5.2 Event Subscribers ............................................................................................... 245

4.6 Memory Map .............................................................................................................. 2464.7 Interrupts and Events Registers ........................................................................................ 247

4.7.1 AON_EVENT Registers......................................................................................... 2474.7.2 EVENT Registers ................................................................................................ 270

5 JTAG Interface ................................................................................................................. 3895.1 Top Level Debug System................................................................................................ 3905.2 cJTAG ...................................................................................................................... 393

5.2.1 JTAG Commands................................................................................................ 3955.2.2 Programming Sequences....................................................................................... 397

5.3 ICEPick..................................................................................................................... 3985.3.1 Secondary TAPs ................................................................................................. 3985.3.2 ICEPick Registers ............................................................................................... 4005.3.3 ROUTER Scan Chain ........................................................................................... 4035.3.4 TAP Routing Registers ......................................................................................... 404

5.4 ICEMelter .................................................................................................................. 4085.5 Serial Wire Viewer (SWV) ............................................................................................... 4085.6 Halt In Boot (HIB) ......................................................................................................... 4095.7 Debug and Shutdown .................................................................................................... 409

3SWCU117D–February 2015–Revised September 2015 ContentsSubmit Documentation Feedback


http://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SWCU117D

www.ti.com

5.8 Debug Features Supported Through WUC TAP ..................................................................... 4105.9 Profiler Register ........................................................................................................... 411

6 Power, Reset, and Clock Management................................................................................. 4126.1 Introduction ................................................................................................................ 4136.2 System CPU Mode ....................................................................................................... 4146.3 Supply System ............................................................................................................ 415

6.3.1 Internal DC-DC Converter and Global LDO .................................................................. 4166.3.2 External Regulator Mode ....................................................................................... 416

6.4 Digital Power Partitioning ................................................................................................ 4176.4.1 MCU_VD .......................................................................................................... 4186.4.2 AON_VD .......................................................................................................... 418

6.5 Clock Management ....................................................................................................... 4186.5.1 System Clocks ................................................................................................... 4186.5.2 Clocks in MCU_VD .............................................................................................. 4216.5.3 Clocks in AON_VD .............................................................................................. 423

6.6 Power Modes.............................................................................................................. 4246.6.1 Startup State ..................................................................................................... 4256.6.2 Active Mode ...................................................................................................... 4256.6.3 Idle Mode ......................................................................................................... 4266.6.4 Standby Mode .................................................................................................... 4266.6.5 Shutdown Mode.................................................................................................. 428

6.7 Reset ....................................................................................................................... 4286.7.1 System Resets ................................................................................................... 4286.7.2 Warm Reset ...................................................................................................... 4296.7.3 Software-Initiated Reset of MCU_VD ......................................................................... 4296.7.4 Reset of the MCU_VD Power Domains and Modules ...................................................... 4296.7.5 Reset of AON_VD ............................................................................................... 4296.7.6 Reset of AUX_PD................................................................................................ 430

6.8 PRCM Registers .......................................................................................................... 4316.8.1 DDI_0_OSC Registers .......................................................................................... 4316.8.2 AON_SYSCTL Registers ....................................................................................... 4516.8.3 AON_WUC Registers ........................................................................................... 4576.8.4 PRCM Registers ................................................................................................. 473

7 Versatile Instruction Memory System (VIMS)........................................................................ 5327.1 VIMS Configurations ..................................................................................................... 534

7.1.1 VIMS Modes...................................................................................................... 5347.1.2 VIMS Flash Line Buffering...................................................................................... 5377.1.3 VIMS Arbitration.................................................................................................. 5377.1.4 VIMS Cache TAG Prefetch ..................................................................................... 537

7.2 VIMS Software Remarks................................................................................................. 5387.2.1 Flash Program or Update ....................................................................................... 5387.2.2 VIMS Retention .................................................................................................. 538

7.3 ROM ........................................................................................................................ 5397.4 FLASH...................................................................................................................... 539

7.4.1 FLASH Memory Protection ..................................................................................... 5397.4.2 Memory Programming .......................................................................................... 5407.4.3 FLASH Memory Programming ................................................................................. 540

7.5 Power Management Requirements .................................................................................... 5407.6 ROM Functions ........................................................................................................... 5427.7 SRAM ...................................................................................................................... 5437.8 VIMS Registers ........................................................................................................... 544

7.8.1 FLASH Registers ................................................................................................ 5447.8.2 VIMS Registers .................................................................................................. 670




www.ti.com

8 Bootloader ....................................................................................................................... 6738.1 Bootloader Functionality ................................................................................................. 674

8.1.1 Bootloader Disabling ............................................................................................ 6748.1.2 Bootloader Backdoor ............................................................................................ 674

8.2 Bootloader Interfaces..................................................................................................... 6748.2.1 Packet Handling.................................................................................................. 6758.2.2 Transport Layer .................................................................................................. 6768.2.3 Serial Bus Commands .......................................................................................... 678

9 Device Configuration......................................................................................................... 6879.1 Customer Configuration (CCFG) ....................................................................................... 688

9.1.1 CCFG Registers ................................................................................................. 6899.2 Factory Configuration (FCFG) .......................................................................................... 717

9.2.1 FCFG1 Registers ................................................................................................ 71810 Cryptography ................................................................................................................... 800

10.1 AES Cryptoprocessor Overview ........................................................................................ 80110.1.1 Functional Description ......................................................................................... 80110.1.2 Power Management and Sleep Modes ...................................................................... 80210.1.3 Hardware Description .......................................................................................... 80210.1.4 Module Description ............................................................................................. 80310.1.5 Performance..................................................................................................... 81410.1.6 Programming Guidelines ...................................................................................... 81510.1.7 Conventions and Compliances ............................................................................... 826

10.2 Cryptography Registers .................................................................................................. 82810.2.1 CRYPTO Registers............................................................................................. 828

11 I/O Control ....................................................................................................................... 87211.1 Introduction ................................................................................................................ 87311.2 IOC Overview ............................................................................................................. 87311.3 I/O Mapping and Configuration ......................................................................................... 874

11.3.1 Basic I/O Mapping .............................................................................................. 87411.3.2 MAP AUXIO From the Sensor Controller to DIO Pin ...................................................... 87411.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN ......................................................... 875

11.4 Edge Detection on Pin (DIO) ............................................................................................ 87511.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT ............................... 875

11.5 AON IOC State Latching When Powering Off the MCU Domain .................................................. 87511.6 Unused I/O Pins........................................................................................................... 87611.7 GPIO........................................................................................................................ 87611.8 I/O Pin Mapping........................................................................................................... 87711.9 Peripheral PORTIDs...................................................................................................... 87811.10 I/O Pin...................................................................................................................... 878

11.10.1 Physical Pin .................................................................................................... 87811.10.2 Pin Configuration .............................................................................................. 879

11.11 I/O Control Registers..................................................................................................... 88011.11.1 AON_IOC Registers .......................................................................................... 88011.11.2 GPIO Registers................................................................................................ 88611.11.3 IOC Registers.................................................................................................. 909

12 Micro Direct Memory Access (µDMA) ................................................................................ 103812.1 μDMA Introduction ...................................................................................................... 103912.2 Block Diagram ........................................................................................................... 104012.3 Functional Description .................................................................................................. 1040

12.3.1 Channel Assignments ........................................................................................ 104112.3.2 Priority .......................................................................................................... 104212.3.3 Arbitration Size ................................................................................................ 1042




www.ti.com

12.3.4 Request Types ................................................................................................ 104212.3.5 Channel Configuration........................................................................................ 104312.3.6 Transfer Modes................................................................................................ 104512.3.7 Transfer Size and Increments ............................................................................... 105212.3.8 Peripheral Interface ........................................................................................... 105212.3.9 Software Request ............................................................................................. 105212.3.10 Interrupts and Errors ........................................................................................ 1053

12.4 Initialization and Configuration......................................................................................... 105312.4.1 Module Initialization ........................................................................................... 105312.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 1054

12.5 µDMA Registers ......................................................................................................... 105512.5.1 UDMA Registers............................................................................................... 1055

13 Timers ........................................................................................................................... 107613.1 General-purpose Timers ............................................................................................... 107713.2 Block Diagram ........................................................................................................... 107813.3 Functional Description .................................................................................................. 1078

13.3.1 GPTM Reset Conditions ..................................................................................... 107913.3.2 Timer Modes ................................................................................................... 107913.3.3 Wait-for-Trigger Mode ........................................................................................ 108613.3.4 Synchronizing GPT Blocks................................................................................... 108713.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values ...................................... 1087

13.4 Initialization and Configuration......................................................................................... 108813.4.1 One-shot and Periodic Timer Modes ....................................................................... 108813.4.2 Input Edge-count Mode....................................................................................... 108913.4.3 Input Edge-timing Mode ...................................................................................... 108913.4.4 PWM Mode..................................................................................................... 109013.4.5 Producing DMA Trigger Events ............................................................................. 1090

13.5 General-purpose Timer Registers..................................................................................... 109113.5.1 GPT Registers ................................................................................................. 1091

14 Real-Time Clock.............................................................................................................. 112614.1 Introduction............................................................................................................... 112714.2 Functional Specifications ............................................................................................... 1127

14.2.1 Functional Overview .......................................................................................... 112714.2.2 Free-Running Counter........................................................................................ 112714.2.3 Channels ....................................................................................................... 112714.2.4 Events .......................................................................................................... 1128

14.3 RTC Registers ........................................................................................................... 112814.3.1 Register Access ............................................................................................... 112814.3.2 Entering Sleep and Wake Up From Sleep ................................................................ 112914.3.3 AON_RTC:SYNC Register................................................................................... 1129

14.4 Real-Time Clock Registers............................................................................................. 113014.4.1 AON_RTC Registers.......................................................................................... 1130

15 Watchdog Timer.............................................................................................................. 114415.1 WDT Introduction........................................................................................................ 114515.2 WDT Functional Description ........................................................................................... 114515.3 WDT Initialization and Configuration.................................................................................. 114615.4 Watchdog Timer Registers............................................................................................. 1147

15.4.1 WDT Registers ................................................................................................ 114716 Random Number Generator.............................................................................................. 1157

16.1 Overview.................................................................................................................. 115816.2 Block Diagram ........................................................................................................... 115816.3 TRNG Software Reset .................................................................................................. 1159




www.ti.com

16.4 Interrupt Requests....................................................................................................... 115916.5 TRNG Operation Description .......................................................................................... 1160

16.5.1 TRNG Shutdown .............................................................................................. 116016.5.2 TRNG Alarms .................................................................................................. 116116.5.3 TRNG Entropy ................................................................................................. 1161

16.6 TRNG Low-level Programing Guide .................................................................................. 116216.6.1 Initialization..................................................................................................... 1162

16.7 Random Number Generator Registers ............................................................................... 116516.7.1 TRNG Registers ............................................................................................... 1165

17 AUX – Sensor Controller with Digital and Analog Peripherals .............................................. 118817.1 Introduction............................................................................................................... 1189

17.1.1 AUX Hardware Overview..................................................................................... 119017.2 Memory Mapping ........................................................................................................ 1191

17.2.1 Alias of Commonly Used Registers......................................................................... 119117.3 I/O Mapping .............................................................................................................. 119317.4 Modules................................................................................................................... 1194

17.4.1 Sensor Controller.............................................................................................. 119417.4.2 GPIO Control .................................................................................................. 120517.4.3 AUX Timers .................................................................................................... 120717.4.4 Time-to-Digital Converter..................................................................................... 120717.4.5 Semaphores ................................................................................................... 120917.4.6 Oscillator Configuration Interface (DDI) .................................................................... 120917.4.7 Analog MUX ................................................................................................... 121017.4.8 ADC ............................................................................................................. 1210

17.5 Power Management..................................................................................................... 121317.5.1 Start-up ......................................................................................................... 121317.5.2 Power Mode Management ................................................................................... 121317.5.3 Wake-up Events ............................................................................................... 121517.5.4 MCU Bus Connection......................................................................................... 1216

17.6 Clock Management ..................................................................................................... 121617.6.1 System Clocks................................................................................................. 121617.6.2 Sensor Controller Clock ...................................................................................... 121717.6.3 Peripheral Clocks ............................................................................................. 1217

17.7 AUX – Sensor Controller Registers ................................................................................... 121817.7.1 ADI_4_AUX Registers ........................................................................................ 121817.7.2 AUX_AIODIO Registers ...................................................................................... 123017.7.3 AUX_EVCTL Registers....................................................................................... 123917.7.4 AUX_SMPH Registers........................................................................................ 126117.7.5 AUX_TDC Registers .......................................................................................... 127117.7.6 AUX_TIMER Registers ....................................................................................... 128517.7.7 AUX_WUC Registers ......................................................................................... 129417.7.8 AUX_ANAIF Registers ....................................................................................... 1315

18 Battery Monitor and Temperature Sensor........................................................................... 132218.1 Introduction............................................................................................................... 132318.2 Functional Description .................................................................................................. 132318.3 BATMON Registers ..................................................................................................... 1324

18.3.1 AON_BATMON Registers.................................................................................... 132419 Universal Asynchronous Receivers and Transmitters (UARTS) ............................................ 1338

19.1 Universal Asynchronous Receiver/Transmitter...................................................................... 133919.2 Block Diagram ........................................................................................................... 134019.3 Signal Description ....................................................................................................... 134019.4 Functional Description ................................................................................................. 1340

19.4.1 Transmit and Receive Logic ................................................................................. 13417SWCU117D–February 2015–Revised September 2015 Contents

Submit Documentation FeedbackCopyright © 2015, Texas Instruments Incorporated


www.ti.com

19.4.2 Baud-rate Generation......................................................................................... 134119.4.3 Data Transmission ............................................................................................ 134119.4.4 Modem Handshake Support ................................................................................. 134219.4.5 FIFO Operation ................................................................................................ 134319.4.6 Interrupts ....................................................................................................... 134319.4.7 Loopback Operation .......................................................................................... 1344

19.5 Interface to DMA ........................................................................................................ 134419.6 Initialization and Configuration......................................................................................... 134519.7 UARTS Registers ....................................................................................................... 1347

19.7.1 UART Registers ............................................................................................... 134720 Synchronous Serial Interface (SSI).................................................................................... 1368

20.1 Synchronous Serial Interface .......................................................................................... 136920.2 Block Diagram ........................................................................................................... 137020.3 Signal Description ....................................................................................................... 137120.4 Functional Description .................................................................................................. 1371

20.4.1 Bit Rate Generation ........................................................................................... 137120.4.2 FIFO Operation ................................................................................................ 137120.4.3 Interrupts ....................................................................................................... 137220.4.4 Frame Formats ................................................................................................ 1373

20.5 DMA Operation .......................................................................................................... 138020.6 Initialization and Configuration......................................................................................... 138020.7 SSI Registers ............................................................................................................ 1382

20.7.1 SSI Registers .................................................................................................. 138221 Inter-Integrated Circuit (I2C) Interface ................................................................................ 1394

21.1 Inter-Integrated Circuit Interface....................................................................................... 139521.2 Block Diagram ........................................................................................................... 139521.3 Functional Description .................................................................................................. 1396

21.3.1 I2C Bus Functional Overview ................................................................................ 139621.3.2 Available Speed Modes ...................................................................................... 139821.3.3 Interrupts ....................................................................................................... 139921.3.4 Loopback Operation .......................................................................................... 139921.3.5 Command Sequence Flow Charts .......................................................................... 1399

21.4 Initialization and Configuration......................................................................................... 140721.5 I2C Registers ............................................................................................................. 1408

21.5.1 I2C Registers .................................................................................................. 140822 Integrated Interchip Sound (I2S) Module ............................................................................ 1428

22.1 Introduction .............................................................................................................. 142922.2 Digital Audio Interface .................................................................................................. 142922.3 Frame Configuration .................................................................................................... 143022.4 Pin Configuration ........................................................................................................ 143022.5 Clock Configuration ..................................................................................................... 1430

22.5.1 WCLK, BCLK, and MCLK Division Ratio................................................................... 143122.6 Serial Interface Formats ................................................................................................ 1431

22.6.1 I2S............................................................................................................... 143122.6.2 Left Justified (LJF) ............................................................................................ 143222.6.3 Right Justified (RJF) .......................................................................................... 143222.6.4 DSP ............................................................................................................. 1433

22.7 Memory Interface........................................................................................................ 143422.7.1 Word Lengths .................................................................................................. 143422.7.2 Audio Channels................................................................................................ 143422.7.3 Memory Buffers and Pointers................................................................................ 1435

22.8 Samplestamp Generator ............................................................................................... 1435




www.ti.com

22.8.1 Counters and Registers ...................................................................................... 143622.8.2 Starting Input and Output Pins .............................................................................. 143722.8.3 Samplestamp Capturing...................................................................................... 1437

22.9 Usage ..................................................................................................................... 143822.9.1 Start-up Sequence ............................................................................................ 143822.9.2 Termination Sequence ....................................................................................... 1439

22.10 I2S Registers ............................................................................................................ 144022.10.1 I2S Registers ................................................................................................. 1440

23 Radio............................................................................................................................. 147123.1 RF Core................................................................................................................... 1472

23.1.1 High-level Description and Overview ....................................................................... 147223.2 Radio Doorbell ........................................................................................................... 1473

23.2.1 Command and Status Register and Events ............................................................... 147423.2.2 RF Core Interrupts ............................................................................................ 147423.2.3 Radio Timer .................................................................................................... 1475

23.3 RF Core HAL ............................................................................................................ 147723.3.1 Hardware Support............................................................................................. 147723.3.2 Firmware Support ............................................................................................. 147723.3.3 Command Definitions ......................................................................................... 149023.3.4 Protocol-Independent Direct and Immediate Commands................................................ 150423.3.5 Immediate Commands for Data Queue Manipulation .................................................... 1512

23.4 Data Queue Usage...................................................................................................... 151523.4.1 Operations on Data Queues Only Available for Internal Radio CPU Operations..................... 151523.4.2 Radio CPU Usage Model .................................................................................... 1518

23.5 IEEE 802.15.4 ........................................................................................................... 151923.5.1 IEEE 802.15.4 Commands................................................................................... 151923.5.2 Interrupts ....................................................................................................... 152723.5.3 Data Handling.................................................................................................. 152723.5.4 Radio Operation Commands ................................................................................ 152823.5.5 Immediate Commands ....................................................................................... 1540

23.6 Bluetooth Low Energy .................................................................................................. 154223.6.1 Bluetooth Low Energy Commands......................................................................... 154223.6.2 Interrupts ....................................................................................................... 155123.6.3 Data Handling.................................................................................................. 155223.6.4 Radio Operation Command Descriptions .................................................................. 155323.6.5 Immediate Commands ....................................................................................... 1574

23.7 Proprietary Radio........................................................................................................ 157523.7.1 Packet Formats................................................................................................ 157523.7.2 Commands ..................................................................................................... 157523.7.3 Interrupts ....................................................................................................... 158223.7.4 Data Handling.................................................................................................. 158323.7.5 Radio Operation Command Descriptions .................................................................. 158423.7.6 Immediate Commands ....................................................................................... 1595

23.8 Radio Registers.......................................................................................................... 159623.8.1 RFC_RAT Registers .......................................................................................... 159623.8.2 RFC_DBELL Registers ....................................................................................... 160623.8.3 RFC_PWR Registers ......................................................................................... 1622




Revision History: SWCU117D www.ti.com

Revision History: SWCU117D

Changes from September 4, 2015 to September 30, 2015 ............................................................................................. Page

• Changed register names in the Timers chapter .................................................................................. 1077• Changed Radio chapter.............................................................................................................. 1472

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Revision History: SWCU117C

Changes from June 10, 2015 to September 4, 2015 ....................................................................................................... Page

• Added CC13xx part number to the block diagram .................................................................................. 15• Changed Radio chapter.............................................................................................................. 1474• Added Proprietary Radio section ................................................................................................... 1575


Revision History: SWCU117B

Changes from March 6, 2015 to June 9, 2015 ................................................................................................................. Page

• Changed Architectural Overview chapter............................................................................................. 15• Changed register names in the Architectural Overview chapter .................................................................. 27• Updated links in Cortex-M3 Processor chapter...................................................................................... 29• Changed CPU Block Diagram ......................................................................................................... 30• Changed TPIU Block Diagram ......................................................................................................... 31• Changed Cortex-M3 Processor registers ............................................................................................. 51• Changed Cortex-M3 Peripherals chapter ........................................................................................... 221• Added Cortex-M3 Memory Map ...................................................................................................... 226• Changed register names in the Interrupts and Events chapter .................................................................. 229• Changed Interrupts and Events registers ........................................................................................... 247• Changed register names in the Power, Reset, and Clock Management chapter ............................................. 413• Changed PRCM registers ............................................................................................................. 431• Changed register names in the Versatile Instruction Memory System (VIMS) chapter....................................... 534• Added the Power Management Requirements section ........................................................................... 540• Deleted FLASHMEM register subsection ........................................................................................... 544• Changed VIMS registers .............................................................................................................. 544• Changed register names in the Device Configuration chapter ................................................................... 688• Changed Device Configuration registers............................................................................................ 688• Changed register names in the Cryptography chapter ............................................................................ 801• Changed DMA Controller and Integration diagram ................................................................................ 805• Changed values in the Performance Table for DMA-Based Operations........................................................ 815• Changed register names in the I/O Control chapter ............................................................................... 873• Changed IOC Overview section...................................................................................................... 873• Changed I/O Control registers........................................................................................................ 880• Changed register names in the Micro Direct Memory Access (µDMA) chapter. ............................................. 1039• Changed µDMA registers............................................................................................................ 1055• Changed General-purpose Timer registers ....................................................................................... 1091• Changed register names in the Real-Time Clock chapter....................................................................... 1127• Changed RTC registers .............................................................................................................. 1130• Changed register names in the Watchdog Timer chapter....................................................................... 1145• Changed Watchdog registers ....................................................................................................... 1147

10 Revision History SWCU117D–February 2015–Revised September 2015Submit Documentation Feedback



www.ti.com Revision History: SWCU117A

• Changed Random Number Generator registers.................................................................................. 1165• Changed the AUX – Sensor Controller with Digital and Analog Peripherals chapter........................................ 1188• Changed AUX – Sensor Controller registers...................................................................................... 1218• Changed register names in the Battery Monitor and Temperature Sensor chapter ......................................... 1323• Changed BATMON registers ........................................................................................................ 1324• Changed register names in the UARTS chapter ................................................................................. 1339• Changed UARTS registers .......................................................................................................... 1347• Changed register names in the SSI chapter ...................................................................................... 1369• Changed SSI registers ............................................................................................................... 1382• Changed register names in the Inter-Integrated Circuit (I2C) Interface chapter .............................................. 1395• Changed I2C registers ................................................................................................................ 1408• Changed register names in the I2S chapter ...................................................................................... 1429• Changed I2S registers ............................................................................................................... 1440• Changed register names in the Radio chapter ................................................................................... 1472• Changed CMD_UPDATE_FS Command Format table.......................................................................... 1511• Changed Radio registers ............................................................................................................ 1596


Revision History: SWCU117A

Changes from February 21, 2015 to March 5, 2015 ........................................................................................................ Page

• Changed Cortex-M3 Processor registers ............................................................................................. 51• Changed Interrupts and Events registers ........................................................................................... 247• Changed PRCM registers ............................................................................................................. 431• Changed VIMS registers .............................................................................................................. 544• Changed Device Configuration registers............................................................................................ 688• Changed Detailed Memory Map table ............................................................................................... 803• Changed Cryptography registers..................................................................................................... 828• Changed I/O Control registers........................................................................................................ 880• Updated image. ....................................................................................................................... 1046• Changed µDMA registers............................................................................................................ 1055• Changed General-purpose Timer registers ....................................................................................... 1091• Changed RTC registers .............................................................................................................. 1130• Changed Watchdog registers ....................................................................................................... 1147• Changed Random Number Generator registers.................................................................................. 1165• Changed AUX – Sensor Controller registers...................................................................................... 1218• Changed BATMON registers ........................................................................................................ 1324• Changed UART feature list .......................................................................................................... 1339• Changed Signals for UART table ................................................................................................... 1340• Changed Functional Description section .......................................................................................... 1340• Changed Initialization and Configurations section................................................................................ 1345• Changed UARTS registers .......................................................................................................... 1347• Changed SSI Signals table .......................................................................................................... 1371• Changed SSI registers ............................................................................................................... 1382• Changed I2C registers ................................................................................................................ 1408• Changed I2S registers ............................................................................................................... 1440• Changed Radio registers ............................................................................................................ 1596


11SWCU117D–February 2015–Revised September 2015 Revision HistorySubmit Documentation Feedback



PrefaceSWCU117D–February 2015–Revised September 2015

Read This First

TrademarksSimpleLink is a trademark of Texas Instruments. ARM7, ARM® CoreSight are trademarks of ARM Limited.ARM, Cortex, Thumb, AMBA, ARM PrimeCell are registered trademarks of ARM Limited.

About This DocumentThis technical reference manual provides information on how to use the CC26xx and the CC13xxSimpleLink™ ultra-low power wireless microcontroller devices. The CC26xx and the CC13xx familiesshare the same MCU architecture and most of the peripherals, but the CC13xx radio is designed for usein the sub-1 GHz frequency bands while the CC26xx radio operates in the 2.4-GHz ISM frequency band.This document covers the whole family of devices, so please see the individual device data sheet forsupported modules and features.

AudienceThis manual is intended for system software developers, hardware designers, and application developers.

About This ManualThis document is organized into sections that correspond to each major feature. It explains the featuresand functionality of each module, and explains how to use them. For each feature, references are given tothe corresponding operating systems driver documentation. This document does not contain performancecharacteristics of the device or modules. These are gathered in the corresponding device data sheet.

Related DocumentsThe following related documents are available on the CC26xx product pages at www.ti.com:• CC2620 Data Sheet and Errata (CC2620 Technical Documents)• CC2630 Data Sheet and Errata (CC2630 Technical Documents)• CC2640 Data Sheet and Errata (CC2640 Technical Documents)• CC2650 Data Sheet and Errata (CC2650 Technical Documents)• CC1310 Data Sheet and Errata (CC1310 Technical Documents)

This list of documents was current as of publication date. Check the web site for additional documentation,including application notes and white papers.

DevicesThe CC26xx and the CC13xx family of devices includes both 2.4-GHz and Sub-1 GHz radios and a varietyof different memory sizes, peripherals and package options. All devices are centered around an ARM®Cortex®-M series processor that handles the application layer and protocol stack, as well as anautonomous radio core centered around an ARM Cortex-M0 processor that handles all the low-level radiocontrol and processing. Network processor options are available.

The availability of several a wide range of different radio and MCU system combination makes thesefamilies very well suited for almost any low-power RF node implementation.

12 Read This First SWCU117D–February 2015–Revised September 2015Submit Documentation Feedback


http://www.ti.com/lit/pdf/www.ti.comhttp://www.ti.com/lit/pdf/http://www.ti.com/product/CC2620/technicaldocumentshttp://www.ti.com/lit/pdf/http://www.ti.com/product/CC2630/technicaldocumentshttp://www.ti.com/lit/pdf/http://www.ti.com/product/CC2640/technicaldocumentshttp://www.ti.com/lit/pdf/http://www.ti.com/product/CC2650/technicaldocumentshttp://www.ti.com/lit/pdf/http://www.ti.com/product/CC1310/technicaldocumentshttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SWCU117D

www.ti.com Related Documents

FeedbackHelp us meet your expectations:We are always exploring ways to develop our service and improve our quality to fit your needs. Pleasecontact your TI representative and take a few minutes to provide general suggestions, give documentfeedback, or submit an error.

Thank you.

Community ResourcesAll technical support is channeled through the TI Product Information Centers (PIC) - www.ti.com/support.To send an E-mail request, please enter your contact information, along with your request at the followinglink – PIC request form.

The following link connects to TI community resources. Linked contents are provided "AS IS" by therespective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;see TI's Terms of Use.

TI Embedded Processors Wiki – Texas Instruments Embedded Processors Wiki

TI BLE Wiki – Texas Instruments Bluetooth Smart Wiki

Established to assist developers using the many Embedded Processors from TI to get started, help eachother innovate, and foster the growth of general knowledge about the hardware and software surroundingthese devices.

Register, Field, and Bit Calls

The naming convention applied for a call consists of:• For a register call: .; for example: UART.UASR• For a bit field call:

– .[End:Start] field; for example, UART.UASR[4:0]SPEED bit field

– field .[End:Start]; for example, SPEED bit fieldUART.UASR[4:0]

• For a bit call:– .[pos] bit; for example, UART.UASR[5]

BIT_BY_CHAR bit– bit .[pos]; for example, BIT_BY_CHAR bit

UART.UASR[5]

13SWCU117D–February 2015–Revised September 2015 Read This FirstSubmit Documentation Feedback


http://www.ti.comhttp://www.ti.com/supporthttp://www-k.ext.ti.com/sc/technical-support/email-tech-support.asp?AAPhttp://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://processors.wiki.ti.com/index.php?title=Main_Pagehttp://processors.wiki.ti.com/index.php/Category:BluetoothLE?DCMP=blestackamp;HQS=ble-wikihttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SWCU117D

Chapter 1SWCU117D–February 2015–Revised September 2015

Architectural Overview

The CC26xx and CC13xx SimpleLink™ ultra-low power wireless MCU platforms provide solutions for awide range of applications. To help the user develop these applications, this user's guide focuses on theuse of the different building blocks of the devices. For detailed device descriptions, complete feature lists,and performance numbers, see the data sheet. To provide easy access to relevant information, thefollowing subsections guide the reader to the different chapters in this guide.

The CC26xx and CC13xx SimpleLink ultra-low power wireless MCU platform system-on-chips (SoCs) areoptimized for ultra low power, while providing fast and capable MCU systems to enable short processingtimes and high integration. The combination of an ARM® Cortex®-M3 processing core of up to 48 MHz,flash memory, and a wide selection of peripherals makes the CC26xx and CC13xx device families idealfor single-chip implementation or network processor implementations of lower power RF nodes.

Topic ........................................................................................................................... Page

1.1 Target Applications ............................................................................................ 151.2 Overview ........................................................................................................... 151.3 Functional Overview ........................................................................................... 17

14 Architectural Overview SWCU117D–February 2015–Revised September 2015Submit Documentation Feedback


http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SWCU117D

www.ti.com Target Applications

1.1 Target ApplicationsThe CC26xx and CC13xx SimpleLink ultra-low power wireless MCU platforms are positioned for low-power wireless applications such as:

• Consumer Electronics• Mobile Phone Accessories• Sports and Fitness Equipment• HID Applications• Home and Building Automation• Lighting Control• Alarm and Security• Electronic Shelf Labeling• Proximity Tags• Medical• Remote Controls• Wireless Sensor Networks

1.2 OverviewFigure 1-1 shows the building blocks of the CC26xx and CC13xx devices.

Figure 1-1. CC26xx and CC13xx Block Diagram

15SWCU117D–February 2015–Revised September 2015 Architectural OverviewSubmit Documentation Feedback



Overview www.ti.com

The CC26xx and CC13xx devices have the following features:

• ARM Cortex-M3 processor core– 48-MHz RC oscillator and 24-MHz xtal oscillator with internal doubler– 32-kHz xtal oscillator, 32-kHz RC oscillator or low-power 24-MHz xtal derivate clock for timing

maintenance while in low-power modes– ARM Cortex SysTick timer– Nested vectored interrupt controller (NVIC)

• On-chip memory– Flash with 8KB of 4-way set-associative cache RAM for speed and low power– System RAM with configurable retention in 4-KB blocks

• Power management– Wide supply voltage range– Efficient on-chip DC-DC converter for reduced power consumption– High granularity clock gating and power gating of device parts– Flexible frequency of operation

• Flexible low-power modes allowing low energy consumption in duty cycled applications• Sensor interface

– Autonomous, intelligent sensor interface that can wake up independently of the main CPU systemto perform sensor readings, collect data, and determine if the main CPU must be woken

– 12-bit analog-to-digital converter (ADC) with eight analog input channels– Low-power analog comparator– SPI or I2C master bit-banged

• Advanced serial integration– Universal asynchronous receiver and transmitter (UART)– Inter-integrated circuit (I2C) module– Synchronous serial interface modules (SSIs)– Audio interface I2S module

• System integration– Direct memory access (DMA) controller– Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and

synchronization– 32-kHz real-time clock (RTC)– Watchdog timer– On-chip temperature and supply voltage sensing– GPIO with normal or high-drive capabilities– GPIOs with analog capability for ADC and comparator– Fully flexible digital pin muxing allows use as GPIO or any peripheral function

• IEEE 1149.7 compliant 2-pin cJTAG with legacy 1149.1 JTAG support• 4-mm × 4-mm, 5-mm × 5-mm, and 7-mm × 7-mm QFN packages

For applications requiring extreme conservation of power, the CC26xx and CC13xx devices feature apower-management system to efficiently power down the CC26xx or CC13xx devices to a low-power stateduring extended periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (a real-time clock [RTC]), with interrupt and 20KB of RAM with retention in all power modes positions the CC26xxand CC13xx microcontroller perfectly for battery applications.




www.ti.com Functional Overview

In addition, the CC26xx and CC13xx microcontroller offers the advantages of the widely availabledevelopment tools of ARM, SoC infrastructure IP applications, and a large user community. Additionally,the microcontroller uses ARMThumb®-compatible Thumb-2 instruction set to reduce memory requirementsand, thereby, cost.

TI offers a complete solution to get to market quickly, with evaluation and development boards, whitepapers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, anddistributor network.

1.3 Functional OverviewThe following subsections provide an overview of the features of the CC26xx and CC13xx microcontroller.

1.3.1 ARM Cortex-M3The following subsections provide an overview of the ARM Cortex-M3 processor core and instruction set,the integrated system timer (SysTick), and the NVIC.

1.3.1.1 Processor CoreThe CC26xx and CC13xx devices are designed around an ARM Cortex-M3 processor core. The ARMCortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs ofminimal memory implementation, reduced pin count, and low power consumption, while deliveringoutstanding computational performance and exceptional system response to interrupts.

The following are features of the processor core:• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications• Outstanding processing performance combined with fast interrupt handling• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM

core in a compact memory size, usually associated with 8- and 16-bit devices, typically in the range ofa few kilobytes of memory for microcontroller-class applications– Single-cycle multiply instruction and hardware divide– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral

control– Unaligned data access, enabling efficient packing of data into memory

• Fast code execution permits slower processor clock or increases sleep mode time• Harvard architecture characterized by separate buses for instruction and data• Efficient processor core, system, and memories• Hardware division and fast multiplier• Deterministic, high-performance interrupt handling for time-critical applications• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes• Compact JTAG interface reduces the number of pins required for debugging• Ultra-low power consumption with integrated sleep modes• Up to 48-MHz operation




Functional Overview www.ti.com

1.3.1.2 System Timer (SysTick)ARM Cortex-M3 includes an integrated system timer (SysTick). SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be usedin several different ways; for example:• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick

routine• A high-speed alarm timer using system clock 11• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and

the dynamic range of the counter• A simple counter used to measure time to completion and time used• An internal clock-source control based on missing or meeting durations

1.3.1.3 Nested Vector Interrupt Controller (NVIC)The CC26xx and CC13xx device controller includes the ARM NVIC. The NVIC and Cortex-M3 prioritizeand handle all exceptions in handler mode. The processor state is automatically stored to the stack on anexception and automatically restored from the stack at the end of the interrupt service routine (ISR). Theinterrupt vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processorsupports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of statesaving and restoration. Software can set eight priority levels on seven exceptions (system handlers) andcan set CC26xx and CC13xx device interrupts.

Features of the NVIC are as follows:• Deterministic, fast interrupt processing

– Always 12 cycles, or just 6 cycles with tail-chaining• External nonmaskable interrupt (NMI) signal available for immediate execution of NMI handler for

safety-critical applications• Dynamically reprioritizable interrupts• Exceptional interrupt handling through hardware implementation of required register manipulations

1.3.1.4 System Control BlockThe system control block (SCB) provides system implementation information and system control(configuration, control, and reporting of system exceptions).

1.3.2 On-chip MemoryThe following subsections describe the on-chip memory modules.

1.3.2.1 SRAMThe CC26xx and CC13xx devices provide low leakage on-chip SRAM with optional retention in all powermodes. Retention can be configured per block, and the device contains two blocks of 6KB and two blocksof 4KB. Additionally, the flash cache RAM can be reconfigured to operate as normal system RAM.Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-bandingtechnology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memorymap (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomicoperation.

Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.





1.3.2.2 Flash MemoryThe flash block provides an in-circuit, programmable, nonvolatile program memory for the device. Theflash memory is organized as a set of 4-KB pages that can be individually erased. Erasing a block causesthe entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-onlyblocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Inaddition to holding program code and constants, the nonvolatile memory allows the application to savedata that must be preserved so that it is available after restarting the device. Using this feature lets theuser use saved network-specific data to avoid the need for a full start-up and network find-and-joinprocess.

1.3.2.3 ROMThe ROM is preprogrammed with a boot sequence, device driver functions, low-level protocol stackcomponents, and a serial bootloader (SPI or UART).

1.3.3 RadioThe CC26xx and CC13xx device family provides a highly integrated low-power 2.4-GHz radio transceiverwith support for multiple modulations and packet formats. The CC13xx provides similar functionalityoptimized for the sub-1 GHz bands and also allows limited operation in the 2.4-GHz band. The radiosubsystem provides an interface between the MCU and the radio, which makes it possible to issuecommands, read status, and automate and sequence radio events.

1.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key SupportThe security core of the CC26xx and CC13xx devices features an AES module with 128-bit key support,local key storage, and DMA capability.

Features of the AES engine are as follows:• CCM, CTR, CBC-MAC, and ECB modes of operation• 118-Mbps throughput• Secure key storage memory• Low latency




Functional Overview www.ti.com

1.3.5 General-Purpose TimersGeneral-purpose timers can be used to count or time external events that drive the timer-input pins. Each16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operateindependently as timers or event counters, or configured to operate as one 32-bit timer.

The general-purpose timer module (GPTM) contains four 16- or 32-bit GPTM blocks with the followingfunctional options:• 16- or 32-bit operating modes:

– 16- or 32-bit programmable one-shot timer– 16- or 32-bit programmable periodic timer– 16-bit general-purpose timer with an 8-bit prescaler– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM

signal• Count up or down• Four 32-bit counters or up to eight 16-bit counters• Up to eight capture/compare pins• Up to four PWM pins (one PWM pin per 32-bit timer)• Daisy-chaining of timer modules allows a single timer to initiate multiple timing events• Timer synchronization allows selected timers to start counting on the same clock cycle• User-enabled stalling when the microcontroller asserts CPU halt flag during debug• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the

interrupt service routine• Efficient transfers using the µDMA controller

1.3.5.1 Watchdog TimerThe watchdog timer is used to regain control when the system fails because of a software error or anexternal device fails to respond properly. The watchdog timer can generate an interrupt or a reset when apredefined time-out value is reached.

1.3.5.2 Always-on DomainThe AON domain contains circuitry that is always enabled, except for the shutdown mode (where thedigital supply is off). This domain includes the following:• The RTC can be used to wake the CC26xx and CC13xx devices from any state where it is active. The

RTC contains three match registers and one compare register. With software support, the RTC can beused for clock and calendar operation. The RTC is clocked from the 32-kHz RC oscillator or the32-kHz crystal oscillator.

• The battery monitor and temperature sensors are accessible by software. The battery monitor andtemperature sensors provide continuous monitoring of battery state as well as coarse temperature.

1.3.6 Direct Memory AccessThe CC26xx and CC13xx microcontroller includes a DMA controller, known as μDMA. The μDMAcontroller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing moreefficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfersbetween memory and peripherals. Channels in the μDMA are dedicated for each supported on-chipmodule and can be programmed to automatically perform transfers between peripherals and memory, asthe peripheral is ready to transfer more data.





1.3.7 System Control and ClockSystem control determines the overall operation of the CC26xx and CC13xx devices. System controlprovides information about the CC26xx and CC13xx devices, controls power-saving features, controls theclocking of the CC26xx and CC13xx devices and individual peripherals, and handles reset detection andreporting.• Power control:

– On-chip fixed DC-DC converter and low drop-out (LDO) voltage regulators– Handles the power-up sequencing, power-down sequencing, and control for the core digital-logic

and analog circuits– Low-power options for the CC26xx microcontroller– Low-power options for on-chip modules:

• Software controls shutdown of individual peripherals and memory• 20KB of RAM and configuration registers are retained in all power modes

– Control-pin option for control of external DC-DC regulator– Configurable wake up from sleep timer or any GPIO interrupt– Voltage supervision circuitry

• Multiple clock sources for microcontroller system clock:– RC oscillator (HSRCOSC):

• On-chip resource providing a 48-MHz frequency• The 24-MHz crystal os

Technical Reference Manual - Farnell element14 · CC13xx, CC26xx SimpleLink™ Wireless MCU...

Documents

Transcript of Technical Reference Manual - Farnell element14 · CC13xx, CC26xx SimpleLink™ Wireless MCU...