TEAM LLAMP

04/19/23 1 Department of Electrical & Computer Engineering

Nadja Memic

Steve Karcher

Sri Teja Basava

Francis Yi

LED Lattice Associative Multi-touch Product

Critical Design Review

TEAM LLAMP


CDR Outline

• System Drawing

• Outline of Approach

• Frame

• Tx & Rx Subassembly

• PCB Layout

• UIA Bus Definition

• Demo & Test Results

• Frame Fabrication• IPB Subassembly• Parts List• Revised Timeline• Updated Division of

Labor• Milestone/Expo

Deliverables• Questions?


System Drawing


Outline of Approach

Frame Input Processing Box

Software Application (Drawing Tool)

Driver

Computer

FPGA w/ Supporting HardwareTouch Input

8

5

5

3

Ribbon CableControl Signals & Data

Mouse CoordinatesScreen Output

Serial Mouse Coordinates


Frame

Tx

Rx

5

3

Board Select

Tx Select

5Board Select

Selected Tx On

8 Selected Rx Status


Tx Subassembly


Frame

Tx

Rx

5

3

Board Select

Tx Select

5Board Select

Selected Tx On

8 Selected Rx Status


Rx Subassembly


PCB Layout Revision 1


Pin Name Description Default Level1 VDD6 +6V DC supply for logic chip +6V DC2 VDD18 +18V DC supply as noise contingency +18V DC

3 GND0 System ground 0V DC4 GND1 System ground 0V DC5 TX7 Board ID 5 [●○○○ ○---] CMOS LOW6 TX6 Board ID 4 [○●○○ ○---] CMOS LOW7 TX5 Board ID 3 [○○●○ ○---] CMOS LOW8 TX4 Board ID 2 [○○○● ○---] CMOS LOW9 TX3 Board ID 1 [○○○○ ●---] CMOS LOW10 TX2 Transmitter ID 3 [---- -●○○] CMOS LOW11 TX1 Transmitter ID 2 [---- -○●○] CMOS LOW12 TX0 Transmitter ID 1 [---- -○○●] CMOS LOW13 RX4 Board ID 5 [●○○○○] CMOS LOW14 RX3 Board ID 4 [○●○○○] CMOS LOW15 RX2 Board ID 3 [○○●○○] CMOS LOW16 RX1 Board ID 2 [○○○●○] CMOS LOW17 RX0 Board ID 1 [○○○○●] CMOS LOW18 D7 Data transmit bit 8 [●○○○ ○○○○] CMOS LOW19 D6 Data transmit bit 7 [○●○○ ○○○○] CMOS LOW20 D5 Data transmit bit 6 [○○●○ ○○○○] CMOS LOW21 D4 Data transmit bit 5 [○○○● ○○○○] CMOS LOW22 D3 Data transmit bit 4 [○○○○ ●○○○] CMOS LOW23 D2 Data transmit bit 3 [○○○○ ○●○○] CMOS LOW24 D1 Data transmit bit 2 [○○○○ ○○●○] CMOS LOW25 D0 Data transmit bit 1 [○○○○ ○○○●] CMOS LOW26 GND2 System ground 0V DC

UIA Bus Definition Revision 1


PCB Revision 1

Original board select algorithm – decode address on each board

3500mil x 3400mil = 11.9 inches2

10 Address bits

3 Tx ID bits

8 Data bits

10 DIPs

Fewer wires, generic solution


PCB Layout Revision 2


UIA Bus Definition Revision 2Pin Name Description Default Level

1 VCC Positive power supply +6V DC2 GND System Ground 0V DC3 Ena01 Enable Board 1 CMOS LOW4 Ena02 Enable Board 2 CMOS LOW5 Ena03 Enable Board 3 CMOS LOW6 Ena04 Enable Board 4 CMOS LOW7 Ena05 Enable Board 5 CMOS LOW8 Ena06 Enable Board 6 CMOS LOW9 Ena07 Enable Board 7 CMOS LOW10 Ena08 Enable Board 8 CMOS LOW11 Ena09 Enable Board 9 CMOS LOW12 Ena10 Enable Board 10 CMOS LOW13 Ena11 Enable Board 11 CMOS LOW14 Ena12 Enable Board 12 CMOS LOW15 Ena13 Enable Board 13 CMOS LOW16 Ena14 Enable Board 14 CMOS LOW17 TxID1 Transmitter ID 1 MSB[○○●]LSB CMOS LOW18 TxID2 Transmitter ID 2 MSB[○●○]LSB CMOS LOW19 TxID3 Transmitter ID 3 MSB[●○○]LSB CMOS LOW20 Cntrl Behavior Identifier Tx LOW Rx HI

21 Data1 Data bit 1 MSB[○○○○ ○○○●]LSB CMOS LOW22 Data2 Data bit 2 MSB[○○○○ ○○●○]LSB CMOS LOW23 Data3 Data bit 3 MSB[○○○○ ○●○○]LSB CMOS LOW24 Data4 Data bit 4 MSB[○○○○ ●○○○]LSB CMOS LOW25 Data5 Data bit 5 MSB[○○○● ○○○○]LSB CMOS LOW26 Data6 Data bit 6 MSB[○○●○ ○○○○]LSB CMOS LOW27 Data7 Data bit 7 MSB[○●○○ ○○○○]LSB CMOS LOW28 Data8 Data bit 8 MSB[●○○○ ○○○○]LSB CMOS LOW29 NC1 Reserved for future use NC30 NC2 Reserved for future use NC


PCB Revision 2

Revised board select algorithm – one enable line per board

2000mil x 3850mil = 7.7inches2

1 Enable/board – 14 total 3 Tx ID bits8 Data 5 SOIC, SOT353

Fewer parts, no loading, less expensive


Demo


Test Results

Digital signals D[15:11] measure the board select, while the transmitter ID is on D[10:8]. The trigger fires when the board is manually selected (changed from 01000 to 01010), and the delay time between board select and transmitter response is measured to be 788 ns.


Test Results

Digital signals D[15:11] measure the board select, while the transmitter ID is on D[10:8]. The trigger fires when the board is manually de-selected (changed from 01010 to 00010), and the delay time between board de-select and transmitter response is measured to be 1046 ns.


Test Results

Digital signal D3 triggers when the board is selected. Between the trigger and D7, the measured response time is 191 ns. This is the response of the receive circuit independent of the transmit circuit.


Test Results

D[2:0] are the transmitter select signals. When transmitter 000 is selected, we observe the voltage driving the transmitter (violet) and the voltage indication on the photo-transistor (yellow). The digital signal representing the response is measured on D7 to be 2121 ns from the stimulus.


Frame Fabrication

• Dimensions: Front/Back Image


Frame Fabrication

• Dimensions: Side Image


Frame Fabrication


IPB Subassembly


Transmitting Part 1…


Are any data bits set?

Reading Part 1…


Isolating…


Parts ListPart (Quantity) Part Number Unit Price Package

Driver (28) MIC2981/82 $2.27 18 SOIC

3:8 Decoder (28) M74HC238 $0.48 16 SOIC

Quad OpAmp (56) TLV2374 $1.55 14 SOIC

NAND gate chip (28) 74HC1G00 $0.29 SOT353

3 State Latch (28) MM74HC373 $0.43 20 SOIC

Capacitors (168) 0.1 uF free 805

Resistors (672) 47, 10, 10k $0.06 603

Resistor (28) 10k $0.06 Center-tap

Header 2H (140)

Header 14 x 2 (28)

Header 15 x 2 (28)

Photodiode (224) SFH313FA $0.36

LED (224) SFH4550 $0.60

Frame Material (1) $120.00


Revised Timeline


Updated Division of Labor and Responsibilities

1. Frame:

- Fabrication

- PCB/Soldering

- Assembly

2. Input Processing Box:

- Loading Nios II onto FPGA

- Logic algorithm development

- Creating a board for FPGA

3. Driver Development:

- Updating, averaging, proximity & toggling

4. Software Application:

- Implementation of painting ftn

Nadja & Francis

Entire Team

Steve, Teja, & Francis

Francis & Teja

Nadja & Steve

Steve & Nadja

Teja & Francis

Steve, Teja, & Nadja


Milestone/Expo DeliverablesMilestone 1 (Nov 1)

• PCB complete

– Pick and place both revisions

– Test both revisions for speed and robustness

– Order board set and driver circuitry

• Boards mounted

– Machine acrylic

– Countersink mounting hardware

– Mount PCBs to UIA

• Cabling and set IDs

– Measure and place cable taps

– Set board IDs

– Test for uniqueness with a FPGA routine

Milestone 2 (Nov 29)

• Cyclone support – Develop support circuitry– Layout PCB

• IPB Algorithms– Develop – Implement in C and logic gates

• RS-232 Interface– Research– Interface with NIOS II

• Testing and Debugging

Open-Lab Expo (Dec 13)

• Application– Develop front and back end– Quality Assurance


Questions?

Thank You!?

TEAM LLAMP

Documents

Transcript of TEAM LLAMP