Tea 6420

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September 2003 1/7 TEA6420 BUS-CONTROLLED AUDIO MATRIX SWITCH 5 Stereo Inputs 4 Stereo Ouputs Gain Control 0/2/4/6dB/Mute for each Output cascadable (2 different addresses) Serial Bus Controlled Very low Noise Very low Distorsion DESCRIPTION The TEA6420 switches 5 stereo audio inputs on 4stereo outputs. All the switching possibilities are changed through the I 2 C bus. Figure 1. PIN CONNECTIONS SO28 (Plastic Micropackage) ORDER CODE: TEA6420D SHRINK DIP 24 (Plastic Package) ORDER CODE: TEA6420 6420-01.eps - 6420-02.eps 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 24 23 22 21 11 12 GND CAPACITANCE L1 L2 L3 L4 L5 LOUT1 ROUT1 LOUT2 ROUT2 SDA SCL ADDR R1 R2 R3 R4 R5 ROUT4 LOUT4 ROUT3 LOUT3 V S GND CAPACITANCE L1 L2 L3 L4 L5 LOUT1 ROUT1 LOUT2 ROUT2 SDA SCL ADDR R1 R2 R3 R4 R5 ROUT4 LOUT4 ROUT3 LOUT3 V S 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 24 23 22 21 11 12 25 13 14 28 27 26 NC NC NC NC 1

Transcript of Tea 6420

Page 1: Tea 6420

September 2003 1/7

TEA6420

BUS-CONTROLLED AUDIO MATRIX SWITCH

5 Stereo Inputs 4 Stereo Ouputs Gain Control 0/2/4/6dB/Mute for each Output cascadable (2 different addresses) Serial Bus Controlled Very low Noise Very low Distorsion

DESCRIPTION

The TEA6420 switches 5 stereo audio inputs on4stereo outputs.

All the switching possibilities are changed throughthe I2C bus.

Figure 1. PIN CONNECTIONS

SO28(Plastic Micropackage)

ORDER CODE: TEA6420D

SHRINK DIP 24(Plastic Package)

ORDER CODE: TEA6420

6420

-01.

eps

- 642

0-02

.eps

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

24

23

22

21

11

12

GND

CAPACITANCE

L1

L2

L3

L4

L5

LOUT1

ROUT1

LOUT2

ROUT2

SDA

SCL

ADDR

R1

R2

R3

R4

R5

ROUT4

LOUT4

ROUT3

LOUT3

VS

GND

CAPACITANCE

L1

L2

L3

L4

L5

LOUT1

ROUT1

LOUT2

ROUT2

SDA

SCL

ADDR

R1

R2

R3

R4

R5

ROUT4

LOUT4

ROUT3

LOUT3

VS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

24

23

22

21

11

12

25

13

14

28

27

26

NC

NC

NC

NC

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Figure 2. BLOCK DIAGRAM

6420

-03.

eps

SUPPLY BUS DECODER

RIGHTOUTPUTS

LEFTOUTPUTS

SDA

SCL

ADDR

RIGHT INPUTS

GAIN = 0/2/4/6dB

GAIN = 0/2/4/6dB

VS

C

GND

LEFT INPUTS

TEA6420

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ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

ELECTRICAL CHARACTERISTICS TA = 25oC, VS = 10V, RL = 10kΩ, RG = 600Ω, f = 1kHz (unless otherwise specified)

Symbol Parameter Value UnitVCC Supply Voltage (Pin 9) 12 V

TOPER Operating Ambient Temperature Range 0 to +70 oC

Tstg Storage Temperature Range -20 to +150 oC

Symbol Parameter+ Value Unit

Rth(j-a)Junction-Ambient Thermal Resistance SDIP24

SO287575

oC/W

Symbol Parameter Test Conditions Min. Typ. Max. UnitSUPPLY

VSSupply Voltage 8 9 10.2 V

ISSupply Current 5 8 mA

SVR Ripple Rejection VIN = 500mVRMS, BW = 20 - 20kHz 70 80 dB

MATRIX

VINInput DC Level 4.5 5 5.5 V

RIInput Resistance 30 50 100 kΩ

CSChannel Separation VIN = 2VRMS Gain = 0dB

f = 1kHz Gain = 6dB8070

9082

dBdB

OUTPUT BUFFER

VOUTOutput DC Level 4.5 5 5.5 V

ROUTOutput Resistance 70 200 W

eNI Input Noise BW = 20 - 20kHz, flat 3 µV

S/N Signal to Noise Ratio VIN = VOUT = 1VRMS 110 dB

GminMin. Gain -1 0 + 1 dB

GmaxMax. Gain 5 6 7 dB

d Distortion VIN = VOUT = 1VRMS 0.01 0.05 %

VCL Clipping Level d = 0.3% 2 2.5 VRMS

RLOutput Load Resistance 2 kΩ

BUS INPUT

VILInput Low Voltage 1.5 V

VINInput High Voltage 3 V

IIInput Current - 10 10 µA

VO Output Voltage IO = 3mA ; SDA Acknowledge pin 0.4 V

Rpu ADDR Pullup Resistor Note 40 50 kΩ

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SOFTWARE SPECIFICATION

1. Chip address

2. Data bytes

X = don’t care - MSB is transmitted firstExample : 010XX100 connects outputs 3 with input 5 at a gain of 4dBThe following are selected after power-on reset : input 5 selected for all outputs ; gain = 0dB.

Address HEX ADDR1001 1000 98 0

1001 1010 9A 1

Output select

X 0011

0101

G1 G0 I2 I1 I0 Output 1Output 2Output 3Output 4

Input select

X Q1 Q0 G1 G0 000011

001100

010101

Input 1Input 2Input 3Input 4Input 5Mute

Gain select

X Q1 Q0 0011

0101

I2 I1 I0 Gain = 6 dBGain = 4 dBGain = 2 dBGain = 0 dB

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TYPICAL APPLICATION

Figure 3.

6420

-08.

04

1

2

3

4

5

6

7

8

9

10

11

12 13

14

15

16

17

18

19

20

21

22

23

24

µ22 F

100nFC1

C2

C3

C4

C5

C11

C12

C13

C14

CH2Output

L

R

L

R

CH1Output

LeftInputs

C15

C16

C

C

17

18

C10

C

C

9

8

C

C

7

6

SW

R

L

CH3Output

R

L

CH4Output

RightInputs

Bus InputsSCL

SDA

TEA6420

+9V

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PACKAGE MECHANICAL DATA

24 PINS - PLASTIC DIP

Figure 4. 24-Pin Package

28 PINS - PLASTIC SO

Figure 5. 28-Pin Package

Stand-off

A1

B eB1

D

13

12

24

1

F

LA

e1

A2

c

E1

E

e2

Gage Plane

.015

0,38

e2

e3

E

SDIP24

1

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

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