TDC in ACTEL FPGA Tom Sluijk Hans Verkooijen Albert Zwart Fabian Jansen.

TDC in ACTEL FPGATDC in ACTEL FPGATDC in ACTEL FPGATDC in ACTEL FPGA

Tom Sluijk

Hans Verkooijen

Albert Zwart

Fabian Jansen

OT FE Overview

• Amplify analog signals from anode wires (ASDBLR)• Digital conversion (ASDBLR)• Drift Time measurement (OTIS)• Data Serialization and on optical link (GOL)

OT FEE Data (Now)

Bit 31…0 39…32 47…40 … 287…280

Data Header Drift Time Channel 0

Drift Time Channel 1 …

Drift Time Channel 31

In Single-Hit Mode (currently used):

Hit Position

Drift Time Encoding

No Hit 1 1 b6 b5 b4 b3 b2 b1

Hit in 1st BX 0 0 b6 b5 b4 b3 b2 b1

Hit in 2nd BX 0 1 b6 b5 b4 b3 b2 b1

Hit in 3rd BX 1 0 b6 b5 b4 b3 b2 b1

• 6 bits drift-time (25 ns / 64 TDC channels) • 2 bits : 3=Invalid, 0=1st-BX, 1=2nd-BX, 2=3rd-BX

32 channels8 bits / ch

32 bits HDR

At 1.1 MHz288 × 1.1 × 106 b/s

= 0.3168 Gb/s

1.2672 Gb/s(80% of 1.6 Gb/s)

PER FEE

PER OTIS

Bit 31…0 38…32 45…39 … 255…249

Data Header Drift Time Channel 0

Drift Time Channel 1 …

Drift Time Channel 31

Assuming Single-Hit Mode Raw Data:

Hit Position Drift Time Encoding

No Hit 1 b6 b5 b4 b3 b2 b1

Hit 0 b6 b5 b4 b3 b2 b1

• 6 bits drift-time (25 ns / 64 TDC channels) • 1 bits : 1=Invalid, 0=Valid

OT FEE Data (Future)

32 channels7 bits / ch

32 bits HDR

PER FEE

PER OTISAt 40 MHz

256 × 40 × 106 b/s= 10.24 Gb/s

40.96 Gb/s(30.72 Gb/s if 4 bits drift-time)

Zero-Suppression Scheme

Bit

31…0 36…32 41…37 47…42 52…48 58…53 … … … …

Data

Header

OTIS0

No of Hits

OTIS0

Addr. 1st Hit OTIS0

DriftTime 1st Hit OTIS0

Addr. 2nd Hit OTIS0

DriftTime 2nd Hit OTIS0

…Heade

r OTIS1

No of Hits

OTIS1…

Assuming Zero-Suppressed Data:

• 32 bits OTIS Header• 5 bits for hits counter (max no of hits = 32)• 5 bits (0-31) OTIS channel address • 6 bits drift-time (25 ns / 64 TDC channels)

OTIS Sub-Block Data Size = 32 bits + 5 bits + Occupancy 32 11 bits

Total OT FE Data Size = 4 (37 bits + Occupancy 32 11 bits)

N.B. We assume that the data receiver can identify to which of the 4 OTIS the data belong, either because they are serialized in “fixed-OTIS-order” or because the OTIS header contains such ID info. Otherwise, we need to add 2 bits to each “OTIS-sub-block”.

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

50.00

55.00

60.00

65.00

70.00

0 10 20 30 40 50 60 70 80 90 100 110

Occupancy (%)

OT

FE B

andw

idth

(Gb/s

)

40 MHz - 6 bits

40 MHz - 4 bits

FEE Output BandwidthTotal OT FE Data Size = 4 (37 bits + Occupancy 32 11 bits)

6-bits RAW Data

Bandwidth around 60% Occupancy

E.g. 25% Occupancy 20 Gb/s seems a reasonable cutoff for

“truncation”

4-bits RAW Data

Bandwidth around 52% Occupancy

Upgrade LHCb Upgrade LHCb

Upgrade of LHCb has no L0-Trigger.

Need a TDC that can make a time stamp every Bx.

Radiation environment.

At least 32 channels.

April 21, 2023 Outer Tracker Upgrade 7

TDC in Actel FPGATDC in Actel FPGA

ACTEL ProASIC Plus type APA075TQ100

CLK distribution and phase shift TTC broadcasts decoding TSTPLS I2C interface to internal registers

• built with triple-voting• SEU counter

We have experience with ACTEL FPGAs: already used in present OT

FEE(A. Zwart, OT CTRLBox, 2 / C-

Frame)


TDC in Actel FPGA (cont’d)TDC in Actel FPGA (cont’d)

Design of TDC in ACTEL Proasic3E FPGA because of the radiation properties. Design based on the Muonlab TDC; 2 channel TDC in Xilinx FPGA resolution of 500 ps, see: http://www.nikhef.nl/~hansvk/muonlab/

First approach;3 PLLs used to generate phase shifted 320 MHz signals of 0º, 45º, 90º and 135º bins of 780 ps. 8 ch TDC was simulated, this design was hard to fit. The Actel Starter Kit has only 2 PLLs, so this design can not be used for tests.

Second approach;1 PLL at 320 MHz used to generate 8 phase shifted 40 MHz signals bins of 1570 ps A 4 ch TDC is designed.

http://www.nikhef.nl/~hansvk/muonlab/


TDC (second approach)TDC (second approach)

PLL320MHz

BxClock

1 TDC ChannelPhaseShifter Hit

Register

TimeEncode

r

Outputregiste

r

Hit

1 TDC ChannelPhaseShifter Hit

Register

TimeEncode

r

Outputregiste

r

Hit


Timing DiagramTiming Diagram

Chip layoutChip layout

This part is used for the 4 channels


Test ProceduresTest Procedures

The design is fitted in an A3PE1500 208 PQFP and programmed in the Actel Starter Kit.

The first test to determine the DNL:

The onboard 40 MHz xtal oscillator is used as Bx Clock.

An asynchronous pulse generator of 10 MHz generates a Hit signal with a flat distribution.

Second test is a delay scan to determine the linearity:

Pulse generator of 40 MHz supplies the Bx Clock.

This signal is also delayed with a switchable NIM delay with steps of 0.5 ns to get the Hit signal.


Test SetupTest Setup


Hit DistributionHit Distribution


“flat” input timing distribution

artifact of counting

both rising and falling

edges

TDC SpectrumTDC Spectrum


TDC Response to “flat” input timing distribution

|MAX(+)DNL| + |MAX(-)

DNL| 0.77

LinearityLinearity


……

Multi-ChannelsMulti-Channels


Also checked channel relations on event-by-event basis

Outlook Outlook


Complete present checkso linearity checkso long-term stabilityo channel-to-channel variationso …

4 bits or more ?? control and readout logic

o zero-suppression Perform radiation hardness tests

o what’s our goal??o Present LUMI or 25??

TDC in ACTEL FPGA Tom Sluijk Hans Verkooijen Albert Zwart Fabian Jansen.

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