TB-FMCH-3GSDI Referencedesign 1.00...3G/HD/SD-SDI Reference Design Manual Rev.1.00 7 3. Design...

3G/HD/SD-SDI Reference Design Manual

1 Rev.1.00

3G/HD/SD-SDI

Reference Design Manual Rev.1.00


2 Rev.1.00

Revision History

Version Date Description Publisher

Rev.1.00 2011/07/04 Initial release Yoshioka

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3 Rev.1.00

Table of Contents

1. Overview ...................................................................................................................................... 5

2. Board Configuration ..................................................................................................................... 6

3. Design Environment .................................................................................................................... 7

3.1. Device ........................................................................................................................................ 7

3.2. Board .......................................................................................................................................... 7

3.3. Development Environment......................................................................................................... 7

3.4. Development Language ............................................................................................................. 7

3.5. Related Documentation ............................................................................................................. 7

4. Clock Distribution ......................................................................................................................... 8

5. DIP/Push Switch Setting and LED Display ................................................................................ 10

5.1. DIP Switch [SW8] Setting ........................................................................................................ 10

5.2. Push Switch Setting ................................................................................................................. 10

5.3. LED Display ............................................................................................................................. 10

6. Board Operation Confirmation Method ...................................................................................... 11

6.1. Board Setting ........................................................................................................................... 11

6.2. Internal Test Pattern Generation .............................................................................................. 12

6.3. Pass-Through Pattern .............................................................................................................. 15


4 Rev.1.00

List of Figures

Figure 1-1 Entire Board Configuration ................................................................................................ 5

Figure 2-1 Entire Board Configuration ................................................................................................ 6

Figure 5-1 Clock Distribution .............................................................................................................. 8

Figure 5-2 REFCLK Select Switch ..................................................................................................... 9

Figure 6-1 DIP Switch & Status LED ................................................................................................ 10

Figure 7-1 TB-6S-LX150T-IMG2 Jumper Position ........................................................................... 11

Figure 7-2 Block diagram of Internal Test Pattern Generation ......................................................... 12

Figure 7-3 SW4 and SW5 setting for Internal Test Pattern Generation ........................................... 12

Figure 7-4 SW7 setting for Internal Test Pattern Generation ........................................................... 13

Figure 7-5 SW8 setting for Internal Test Pattern Generation ........................................................... 13

Figure 7-6 Error Status ..................................................................................................................... 13

Figure 7-7 Mode Status .................................................................................................................... 14

Figure 7-8 Block diagram of path through pattern ............................................................................ 15

Figure 7-9 SW4 and SW5 setting for pass through pattern .............................................................. 16

Figure 7-10 SW7 setting for pass through pattern ........................................................................... 16

Figure 7-11 Error Status.................................................................................................................... 17

Figure 7-12 Mode Status .................................................................................................................. 17

List of Tables

Table 5-1 REFCLK Select DIP Switch SW7 Setting ........................................................................... 9

Table 6-1 DIP Switch SW8 Setting ................................................................................................... 10

Table 6-2 Push Switch Setting .......................................................................................................... 10

Table 6-3 LED Display ...................................................................................................................... 10

Table 7-1 TB-6S-LX150T-IMG2 Setting ............................................................................................ 11


5 Rev.1.00

1. Overview

This document describes the 3G/HD/SD-SDI input/output reference design specification of FPGA on

TB-6S-LX150T-IMG2 board.

It has been designed to be used in combination with TB-6S-LX150T-IMG2 carrier board,

TB-FMCH-3GSDI FMC board with 3G/HD/SD-SDI input/output circuit and TB-FMCL-AUDIO board

with Audio(AES3) input/output circuit.

(Note that TB-FMCL-AUDIO is used only when audio output is needed.

Figure 1-1 shows a photograph of this reference design consisting of these boards.

Figure 1-1 Entire Board Configuration


6 Rev.1.00

FM

C_H

PC

2. Board Configuration

Figure 2-1 shows the data flow of this reference design in the board configuration shown in Figure1-1.

Figure 2-1 Entire Board Configuration

■ SDI Data Flow

3G/HD/SD-SDI test pattern generated in the FPGA is output through CH0 of TB-FMCH-3GSDI.

3G/HD/SD-SDI input data received through CH1 of TB-FMCH-3GSDI is processed as follows:

1. The received data is passed through to CH2 of TB-FMCH-3GSDI.

2. Received data format (3G/HD/SD) and CRC error detection is performed and its result is

displayed on the corresponding LED.

3. Audio data (AES) is derived from the receive data and output through TX0 of

TB-FMCL-AUDIO.

■ Clock Source

The following two reference clock sources (REFCLK for GTP) are available.

1. ICS810001 on TB-6S-LX150T-IMG2

2. LMH1983 on TB-FMCH-3GSDI


7 Rev.1.00

3. Design Environment

3.1. Device

Device: XC6SLX150T (Spartan6)

Speed Grade: -3

Package: FFG900

3.2. Board

TB-6S-LX150T-IMG2

TB-FMCH-3GSDI

TB-FMCL-AUDIO

3.3. Development Environment

ISE13.1 (Windows7)

3.4. Development Language

Verilog-HDL

3.5. Related Documentation

TB-FMCH-3GSDI Hardware User Manual

TB-LX150T-IMG2 Hardware User Manual

Implementing Triple-Rate SDI with Spartan™-6 GTP Transceivers (Version 1.0 December 15,

2010)


8 Rev.1.00

4. Clock Distribution

Figure 4-1 Clock Distribution

As a reference clock source (REFCLK for GTP), either one of ICS810001 (IDT) Video PLL on

TB-6S-LX150T-IMG2 or LMH1983 (National Semiconductor) Video PLL on TB-FMCH-3GSDI is used

(DIP switch selectable).

The functionality of each block inside the FPGA (see Figure 5-1) is as follows:

GTP101_TX: send 3G/HD/SD-SDI test pattern generated inside the FPGA.

GTP101_RX: receive 3G/HD/SD-SDI data from an external device.

GTP123_TX: send data received by GTP101_RX via pass through.

TX-0 Logic: Generate SDI signals that conform to specific specification (DIP switch selection).

RX Logic: Detect 3G/HD/SD-SDI data from GTP101_RX and store it into FIFO

TX-1 Logic: Send data stored in FIFO to GTP123_TX.

TB-FMCH-3GSDI TB-6S-LX150T-IMG2

XC6SLX150T-2FFG900 FPGA

[Xilinx]

GTP Bank 123GTP Bank101

LVDS

FMC HPC

148.5MHz

148.5MHz

74.25MHz

TX-1 Logic

Pass Through

RX Logic

Pass

Through

TX-0Logic TestData

Gen

FIFO

Read clockWrite clock

BUFG

MUX

ICS8545 (Clock Buffer)

(IDT)

LVDS

148.5MHz / 148.35MHz

SN 65LVDS 250( Closs Point Switch)

[TI]

LVDS LVDS

ICS810001

[IDT]

CDCLVC1102 (Clock Buffer)

[TI]

CDCLVD 2102 (Clock Buffer )

[TI]

LMH1981 (Video Sync Separator)

[NS]

74.25MHz .Oscillator

[Tama Device]

LMP7711 (Amp) [NS]

357LB3I027M

[CTS]

F/V/H Sync out

F/V/H Sync in

SN65LVDS250 (Closs Point Switch)

[TI]

LMH1983( Video PLL )

[NS]

148.35MHz

(VCXO) (Video PLL)

148.35MHz

[SW8] bit-1074.25MHz S L

[SW7] S20 S21R FCL S L

[SW7] S10 S11R FCL S L


9 Rev.1.00

The REFCLK for GTP101 and GTP123 tiles can be selected using a DIP switch [SW7] on the

TB-6S-LX150T-IMG2 board. The TB-FMCH-3GSDI board has also a DIP switch to select the output

clock from the LMH1983.

For details, refer to TB-6S-LX150T-IMG2 and TB-FMCH-3GSDI board specifications.

Figure 4-2 REFCLK Select Switch

Table 4-1 REFCLK Select DIP Switch SW7 Setting

Bit No. Silk Name Comment

1 S10 REFCLK selection for GTP123

2 S11 [S10:S11] “00”= ICS810001, “10”= LMH1983

3 S20 REFCLK selection for GTP101

4 S21 [S20:S21] “00”= ICS810001, “10”= LMH1983

5 - 8 S30,S31,S40,S41 Not Used


10 Rev.1.00

5. DIP/Push Switch Setting and LED Display

This section describes other switch settings.

Figure 5-1 DIP Switch & Status LED

5.1. DIP Switch [SW8] Setting

Table 5-1 DIP Switch SW8 Setting

Silk Name Bit No. Comment

SW8

1 Output format selection

2 [1:2] HD=“OFF,OFF”, 3G=“ON,OFF”, SD=“OFF,ON”

3 - 8 Not Used

9 FPGA internal reset (FIFO Reset) ON: Reset

10

Clock selection for ICS810001

‘ON’=74.25MHz onboard oscillator

‘OFF’=GTP101 recovery clock

5.2. Push Switch Setting

Table 5-2 Push Switch Setting

Silk Name Comment

PSW1 SDI test pattern switchover

PSW2 Clearing receive CRC error

PSW3 SDI specification (Line Standard) switchover

PSW4 Not Used

5.3. LED Display

Table 5-3 LED Display

Silk Name Signal Name Comment

LED26 LED1 Not Used

LED27 LED2 Output format display [LED2:LED3]

LED28 LED3 HD=“OFF,OFF”, SD=“ON,OFF”, 3G=“OFF,ON”

LED29 LED4 Receive CRC error: Light On

LED30 LED5 Receive PLL Lock: Light On

LED31 LED6 Full flag of FPGA’s internal FIFO: Light On

LED32 LED7 Empty flag of FPGA’s internal FIFO: Light On

LED33 LED8 Not Used


11 Rev.1.00

6. Board Operation Confirmation Method

6.1. Board Setting

Make sure that all jumper pins on the TB-6S-LX150T-IMG2 board are set to default settings.

Figure 6-1 TB-6S-LX150T-IMG2 Jumper Position

Table 6-1 TB-6S-LX150T-IMG2 Setting

JP # Setting Details

JP2 1-2 Bank0 voltage setting (2.5V)



JP4,5 1-2 FMC_LPC1 VADJ voltage setting (2.5V)

JP6,7 1-2 FMC_LPC2 VADJ voltage setting (2.5V)

JP8,9 1-2 FMC_HPC VADJ voltage setting (2.5V)

JP22 1-2 SUSPEND mode setting (reserved)

P22

P8 9P1

P6 7

P3

P4 5

P2


12 Rev.1.00

6.2. Internal Test Pattern Generation

First, please download a design into FPGA on the board. Then perform the following operations.

1. Before power-on, make sure that the board and the cables are properly connected as shown

in the figure below.

Figure 6-2 Block diagram of Internal Test Pattern Generation

2. Make sure that the onboard DIP switches of TB-6S-LX150T-IMG2 are set as shown in the

figure below.

The onboard ICS810001 can be set using SW4 and SW5.

With the following settings, input frequency is set to 74.25MHz and output frequency to 148.5MHz.

Figure 6-3 SW4 and SW5 setting for Internal Test Pattern Generation


13 Rev.1.00

[SW7] All OFF

A reference clock can be selected using SW7.

Setting all switches to OFF will select a jitter cleaned clock by the onboard ICS810001.

Figure 6-4 SW7 setting for Internal Test Pattern Generation

SDI mode and feedback clock selecting can be selected using SW8.

When setting bit10 is ON, feedback clock of ICS810001 is onboard oscillator output.

Also, other bits are setting to all OFF will select HD-SDI Mode.

Figure 6-5 SW8 setting for Internal Test Pattern Generation

3. Turn the power on. When FPGA configuration is successfully completed, LED15 will light

on.

If the LEDs are turned on and the LED29 goes “OFF” when PSW2 is pressed as shown in the

figure below, data Transmitting and receiving is being performed without CRC errors.

Figure 6-6 Error Status

ICS810001


14 Rev.1.00

[SW8] bit-1 ON 3G-SDI mode[L D28] goes ON 3G-SDI

[SW8] bit-2 ON SD-SDI mode[L D27] goes ON SD-SDI

SDI mode can be changed using SW8.

If the LEDs are turned on and the LED29 goes “OFF” when PSW2 is pressed as shown in

the figure below. When 3G-SDI mode, LED28 and LED30 will light on, When SD-SDI mode,

LED27 and LED30 will light on.

Figure 6-7 Mode Status

4. Check video format by monitor or waveform monitor.


15 Rev.1.00

TBTBTBTB----6666SSSS----LXLXLXLX 150150150150 TTTT----IMGIMGIMGIMG2222FMC _LPC

FMC_LPC2

CHCHCHCH2222

LMHLMHLMHLMH0387038703870387

LMHLMHLMHLMH0387038703870387

LMHLMHLMHLMH

0387038703870387

LMHLMHLMHLMH

0387038703870387

CHCHCHCH1111

FMC_LPC1

FPGAFPGAFPGAFPGASpartanSpartanSpartanSpartan6 LX150T6 LX150T6 LX150T6 LX150T

TXTXTXTX0000

Trans

TBTBTBTB----FMCLFMCLFMCLFMCL____AUDIOAUDIOAUDIOAUDIO

TBTBTBTB----FMCHFMCHFMCHFMCH____ 3333GSDIGSDIGSDIGSDI

VCXOVCXOVCXOVCXO

PLLPLLPLLPLL

Audio(AES) &

Status(ChipScope)

Test Pattern

Feedback

Trans Trans Trans

FMC_

1981198119811981

LMHLMHLMHLMH

HPC

LMHLMHLMHLMH

1983198319831983

6.3. Pass-Through Pattern

This section describes an operation confirmation method in a case where data is input from a signal

generator or other external sources.

1. Before power-on, make sure that the board and the cables are connected properly as shown

in the figure below.

Figure 6-8 Block diagram of path through pattern

2. Start the signal generator (or any HD-SDI source equipment).

Following explain is based on HD-SDI(1080p 60 Frame) format.


16 Rev.1.00

[SW7] All OFF

3. Make sure that the onboard DIP switches of TB-6S-LX150T-IMG2 are set as shown in the

figure below.

ICS810001 setting by SW4 and SW5. This setting is generated 148.5MHz from 74.25MHz

input.

Figure 6-9 SW4 and SW5 setting for pass through pattern

SW7 is selecting for GTP reference clock of FPGA. Since all SW7 switches are set to OFF,

the jitter cleaning operation is performed by the ICS810001 on TB-6S-LX150T-IMG2.

Figure 6-10 SW7 setting for pass through pattern

SW8 is feedback clock selecting to ICS810001 and SDI mode selecting.

When setting bit10 is OFF, feedback clock of ICS810001 is recovery clock form GTP.

Also, other bits are setting to all OFF will select HD-SDI Mode.


17 Rev.1.00

[SW8] bit-1 ON 3G-SDI mode[L D28] goes ON 3G-SDI

[SW8] bit-2 ON SD-SDI mode[L D27] goes ON SD-SDI

4. Turn the power on. When FPGA configuration is successfully completed, LED15 will

light on.

If the LEDs are turned on and the LED29 goes “OFF” when PSW2 is pressed as shown in the

figure below, data transmitting and receiving is being performed without CRC errors.

Figure 6-11 Error Status

SDI mode can be changed using SW8.

If the LEDs are turned on and the LED29 goes “OFF” when PSW2 is pressed as shown in

the figure below. When 3G-SDI mode, LED28 and LED30 will light on, When SD-SDI mode,

LED27 and LED30 will light on.

Figure 6-12 Mode Status

5. Check video format by monitor or waveform monitor.

6. De-embedded AES3id audio signal output from TB-FMCL-AUDIO. Check audio output by

AES3id D/A convertor and speaker.


18 Rev.1.00

PLD Solution Division URL: http://www.inrevium.jp/eng/x-fpga-board/ E-mail: [email protected] HEADQUARTERS : Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City,

Kanagawa, Japan 221-0056 TEL:+81-45-443-4016 FAX:+81-45-443-4058

TB-FMCH-3GSDI Referencedesign 1.00...3G/HD/SD-SDI Reference Design Manual Rev.1.00 7 3. Design...

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