Tapping on HVDC lines using DC transformers

Dragan Jovcic

Visiting professor,

Electrical and Computer Engineering,

McGill University,

3480 University Street,

Montreal H3A 2A7, Canada,

Tel +1 514 398 7522

Email: d.jovcic@abdn.ac.uk

Boon Teck Ooi,

Professor,

Electrical and Computer Engineering,

McGill University,

3480 University Street,

Montreal H3A 2A7, Canada,

Tel +1 514 398 7133

Email: boon-teck.ooi@mcgill.ca

Permanent address for correspondence:

Dragan Jovcic

School of Engineering,

University of Aberdeen,

Aberdeen, Scotland, AB23 3UE,

Tel +44 1224 272 336,

Fax: +44 1224 272 497

Email: d.jovcic@abdn.ac.uk

Abstract

This paper investigates a new topology for tap terminals on HVDC transmission, which is based on high-

power DC/DC converters. The use of DC transformers brings benefits in terms of better resilience from tap

system faults, more flexibility in power reversal, an additional control channel and lower costs for main AC/DC

converter and transformer. The paper studies both options: using line commutated and voltage source

converters as the main AC/DC tap converters. PSCAD simulation results are given for a 0.025pu. bidirectional

tap on the 1000MW CIGRE HVDC benchmark system. The simulation responses with a line commutated

converter indicate ability to operate the tap terminal at neutral reactive power exchange over wide range of

power levels and also excellent resilience to disturbances on the tap AC grid. The simulations with voltage source

AC/DC converter also show excellent responses for wide range of inputs but the DC/DC converter becomes more

complex. It is concluded that the proposed topology may provide means for wider access to the existing HVDC

transmission links.

Index Terms: High Voltage DC transmission, DC-DC power conversion, thyristor converters.

I. INTRODUCTION

There is a high number of installed HVDC links worldwide, and they all operate as two-terminal systems for point-

to-point transmission. There are two HVDC installations which have operated as multiterminal systems for a limited

time: 1) Italy-Corsica-Sardinia link [1] and 2) Quebec-New England Multiterminal HVDC [2,3]. Although technically

feasible and field-proven concept, multiterminal HVDC has not been widely accepted as a cost effective transmission

topology.

It is well documented that there is great demand and incentive for developing technologies for tapping on HVDC

lines and in general case for multiterminal HVDC [3-5]. A small, isolated community in northern Canada located close

to major HVDC routes, may gain significant benefits from connecting to the national transmission grid [4]. Studies have

shown that there is demand for up to 7 tap stations in power ratings around 20MW, along the Brazilian main HVDC

lines [4]. Multiterminal topologies would increase flexibility of HVDC, improve overall reliability and expand the

application areas. The recently developed HVDC light [6] is being promoted as a suitable interconnection solution for

(off shore) renewable power parks. Because of distributed nature of renewable power sources, the multiterminal HVDC

topology offers significant benefits for power collection and it is being widely studied [7].

This paper studies a new topology for an HVDC tap, where a tap HVDC terminal is defined as a terminal of

sufficiently small rating that it will not significantly affect operation of the main HVDC link. If the rating of tap

terminal is somewhat below the current margin value, which is typically around 10%, then there is no need for a

communication link with the tap terminal and there is no modification in main HVDC [3,4]. The paper explores both

options, of using a Line Commutated Converter (LCC) and using a Voltage Source Converter (VSC) as the AC/DC tap

converter, on a large LCC HVDC system.

There are numerous technical options and challenges in developing a tap terminal on HVDC and they are studied

elsewhere [3-5]. Some of the most significant techno-economic issues are summarized:

• The impact on reliability of the main HVDC link. With parallel (VSC or LCC) taps, a disturbance on tap AC grid

will cause a fault (commutation failure) on the main HVDC system. The tap AC grid is usually very weak.

• The cost of tapping terminal which is determined by high insulation requirements of the main HVDC. Both the tap

converter (VSC or LCC) and AC transformer should be rated for HVDC voltage.

• With LCC taps, the inability to reverse tap power and the need for tap converter operation with high firing angles

implying high harmonics and variable reactive power demand.

• With series taps, the need for higher rating of the tap converter and complex insulation and protection.

Since the power of a tap terminal is small, there will be need for high-ratio voltage stepping, which is typically done

with an AC transformer. The goal of this research is to study if an HVDC tap could be realized with voltage stepping on

the DC side. Such topology may have several important advantages:

• Only one component, the DC transformer, need to be rated for full HVDC voltage,

• The DC transformer reduces impact of tap system disturbances on main HVDC line. Also it may provide additional

means for control of fault current on DC side.

• An AC transformer may not be required,

• The DC transformer introduces additional control channel which may be utilized for controlling another variable

(tap AC system reactive power), enable power reversal, and improving stability.

The DC voltage stepping with high gain and at high power levels (tens of MW) has not been utilized in industry

because of various techno-economic reasons. Recently, a new DC/DC converter has been proposed [8], which is

capable of achieving theoretically unlimited stepping ratio and efficiently transferring powers in MW range. The main

objective is to examine suitability of converter topologies [8], for connecting to HVDC lines and for interfacing with

main HVDC AC/DC converters. The control, performance and reliability issues are primarily addressed, using detailed

modelling on a commercial digital simulator.

II. BIDIRECTIONAL HIGH POWER DC-DC CONVERTER

A. DC-DC converter description

The DC-DC converter plays a central role in the proposed tap topology and it will be reviewed firstly.

Figure 1 shows the topology for the high-power bidirectional DC-DC converter of type 1 [8]. This converter achieves

power direction change by changing current polarity in high-voltage circuit (I2s) and voltage polarity in low voltage

circuit (Vdct1).

The converter operates by sequentially firing T1 and T2 thyristor pairs at 50% duty ratio and at fs switching frequency.

The inductor L1 creates a resonance with Cr which enables Vc voltage ramping and zero-current turn off of T1-T2. All the

switches should have reverse blocking capability but circuit topology provides current commutation (switch turn off)

and therefore thyristors are suitable as switches. The high voltage circuit also operates as a resonant circuit (L1-Cr-L2

resonance) and enables all zero-current switchings of T5-T8.

The principal converter design equation is [8]:

,)(

21

122sr fC

VV

VVI=

− (1)

where I2, V1 and V2 are the average values of the corresponding variables in Figure 1. From (1) we conclude that the

switching frequency and the capacitor size determine power transfer, and therefore fs is used as the control input.

Assuming operation at the border of continuous and discontinuous mode, the inductor L1 can be determined:

( )rs CfL 22

1 /4 π= (2)

Using (1) and (2) we conclude that as the power transfer increases, Cr increases, but L1 reduces. The high voltage

circuit is synchronized to operate at same frequency fs, but there is freedom in choosing firing angle for T5-T8. The high

voltage circuit inductor L2 is much smaller than L1 and less critical for the operation. The value for L2 and the firing

angle for thyristors T5-T8 (which remains constant) can be determined using the design procedure in [8].

Figure 2 shows the bidirectional DC-DC converter which achieves power reversal by changing current direction in

high-voltage (I2s) and in low voltage circuit (I1s). It is similar as the converter in Figure 1, but in step-down mode

thyristors T3-T4 are fired, and voltage V1dct retains same polarity.

Cr

Vc

T2

T2 T1

Ic

T1

Low voltage circuit High voltage circuit

T7

T8

T5

T6 T7

T8

T5

T6L1

Vdct1

It2L2

Vdct2

It1

L1 L2

Cr

Figure 1. DC-DC converter with voltage polarity change on Vdct1 and current polarity change on Vdct2, Vdct1<Vdct2, (Type

1).

Cr

Vc

T2

T2 T1

Ic

T1

Low voltage circuit High voltage circuit

T7

T8

T5

T6 T7

T8

T5

T6T3

T3

T4

T4

L1

Vdct1

It2L2

Vdct2

It1

L1 L2

Cr

Figure 2. DC-DC converter with current polarity change on Vdct1 and Vdct2, Vdct1<Vdct2, (Type 2).

The main advantages of the above converters are:

• Ability to achieve very high voltage stepping ratio (gain), since gain is not dependent on the control input (fs).

• Minimal switch stresses and losses because of soft switchings. The efficiencies of over 95% are expected [8].

• Bidirectional power transfer with fast control capability.

• The ability to operate at high power (MW range) because of use of thyristors, small losses and simplicity,

B. Converter under fault conditions

The operating principles of the above converters have been studied in [8] but the operation under fault conditions is

not well understood. The fault conditions are of great importance in the HVDC tap applications, because of the

reliability issues.

The particularly difficult and important scenario for fault studies is the fault on Vdct1 in step down operation, since this

fault could propagate to Vdct2 and cause outage of main HVDC circuit. The analytical model is used to study converter

under such fault. The voltage Vdct1 is progressively reduced, and iteration methods are used for each voltage level to

examine if a new stable operating point exists. It is assumed that there is no controller action (fs=const.), in order to

examine inherent converter properties under fast transients.

Figure 3 shows the steady-state values for converter currents on low voltage side and high voltage side, under Vdct1

variation. It is seen that current It1 (at the faulted terminal) remains almost constant, whereas current It2 linearly reduces.

This constant-current characteristic is very important for high-power applications. In practical terms it indicates that,

under severe faults on low-voltage side, the converter inherently becomes open circuit on the high-voltage side.

It is noted that Figure 3 shows the balanced steady-state behaviour, whereas under sudden variations in Vdct1 the

dynamic responses will depend on many other factors which cannot be predicted without detailed transient simulation.

0

10

20

30

40

50

60

0 10 20 30 40Voltage Vdct1 [kV]

Current It2 [A]

560

580

600

620

640

660

680

Current It1 [A]

It1It2

Figure 3. Steady-state DC/DC converter variables for voltage Vdct1 reduction.

C. DC/DC converter losses

The DC/DC converter losses will include a range of conduction and switching loss components which are known

from converter loss theory. However this DC/DC converter will have poor switch utilisation factor when the ratio

Vdct2/Vdct1 is increasing and this property will have dominant impact on the magnitude of conduction losses. The

switches in both the high-voltage circuit and low voltage circuit should be rated for high voltage Vdct2, regardless of the

actual magnitude of low-voltage Vdct1. The relative efficiency will therefore reduce as Vdct1 reduces, since the actual

power will depend on the value of Vdct1.

In order to study impact of stepping ratio on efficiency, we assume that the high-voltage is fixed at Vdct2n and power

transfer is fixed at Pn. If the stepping ratio N=Vdct2n/Vdct1 is varied, then the current and voltage on low voltage side are:

NVVVNPI ndctdctndctnt /,/ 2121 == (3)

Assuming a constant current density in silicon dye, then the on-state resistance Ron is proportional to current rating:

,/,/ 2211 tcontcon IRRIRR == (4)

Where Rc is a specific resistance of switches (assumed same for low and high voltage switches). Using (3) and (4)

the on-state losses for low voltage circuit Plon1 and high-voltage circuit Plon2 are:

,/,/ 22

2

2221

2

11 ndctncontlonndctncontlon VPRRIPVPNRRIP ==== (5)

Clearly the low voltage circuit losses will be increasing as the stepping ratio is increasing. If the base case power

loss is taken for stepping ratio N=1 (Plnom), then the increase in total losses is Plon/Plnom=(N+1)/2, which is illustrated in

Figure 4. The detailed calculation of loss components indicates that it can be safely assumed that losses Plnon will be

similar to losses of a back-to-back HVDC system of the same rating. Depending on the size, a back-to-back HVDC can

have total losses in range 0.7-1.5%. Therefore if the stepping ratio is not high (say N<10) we can expect that the total

DC/DC converter losses will be below 3.5-7.5%. It is assumed in this study that such loss would be acceptable for a

small HVDC tap.

0 2 4 6 8 101

2

3

4

5

6

Stepping ratio (N)

Power loss increase Plon/Plnom

Figure 4. Increase in DC/DC converter losses as the function of stepping ratio.

III. DEVELOPING A TAP TERMINAL FOR HVDC TRANSMISSION

A. Line Commutated Converter

Figure 5 shows the proposed topology for the HVDC tap with a line commutated converter. The main HVDC link is

not given in full details, since it is identical to the CIGRE HVDC Benchmark system [9] and the PSCAD tutorial model.

However, the CIGRE benchmark model is converted from a +500kV monopolar to a ±250kV bipolar system to facilitate

tapping using DC transformer. The converters in Figures 1 and 2 can only have central point common for high and low

voltage circuits. In practice, majority of HVDC links will be bipolar. A bidirectional 25MW tap is studied on the

1000MW main HVDC line, which would correspond to connection with grid of a small remote town along the HVDC

route, perhaps with excess intermittent (renewable) power generation. The tap system has a 33kV AC grid (SCR=18,

X/R=13). All system parameters are given in Table A.1 in the Appendix.

The DC-DC converter of type 1, Figure 1, is used, with 43kV/500kV stepping ratio, and 25MW rating. Assuming that

typical phase-control 6kV thyristors are used, the turn off time is 500µs and the nominal switching frequency of

fsn=600Hz (frequency seen on DC side) is chosen [8]. Since the inductor L1 is crucial component in the DC/DC

converter, in terms of size and losses, a preliminary design is undertaken and the calculated parameters are given in

Table A.2. The weight for L1 is around 5ton which is considerably smaller than a comparable 25MW 33kV/500kV AC

transformer. Furthermore, if tap power is increased, the physical size of L1 remains similar since inductance L1 would

reduce (from (2) and (1)), but current I1 would increase.

The AC/DC LCC tap converter is rated 25MW but the voltage rating is only 33kV (AC). This converter is a standard

thyristor-based 6-pulse bridge. There is no need for AC transformer but a small reactor (Ltap) is required to enable

synchronization with the AC grid. This reactor has small inductance and can be of air core design with low weight and

small size. A standard filtering circuit is developed with 5th

, 7th

, 11th, 13

th, 23

rd and high pass filters. The filters also

provide reactive power (around 6.5MVar) to fully compensate the reactive power demand from AC/DC converter at

rated power.

Figure 6 shows the top-level controller for the DC/DC converter. The PI controller regulates the DC power transfer in

feedback manner using frequency input. There is also a control function for reducing the power reference (Pdct1ref) under

depressions in DC terminal voltages (Vdct1 and Vdct2), which helps in fault recoveries.

Figure 7 shows the proposed controller for AC/DC tap converter. This controller includes a PI controller for keeping

extinction angle (γdct) at safe level to prevent commutation failure [10], which is only active in inversion mode. Also

there is a new PI controller for regulating reactive power exchange, which is active in both rectifier and inverter mode.

The latter PI controller may alternatively regulate tap terminal AC voltage (Vact).

DC/DC type 1-250kV

+250kV+22kV

-22kV

33kV

33kV

25MW

+250kV

-250kV

1000MW

345kV

345kV

230kV

230kV

Lf1

Lf1Cf1

Cf1Cf2

Cf2

Rf2

Rf2

Ltap

Lact

Ract

L5

L7

L11

Lhp C

hpRhp

C11

C7

C5

Vdct1 V

dct2

Idct2

Idct1

Pact,Qact

Vdc

Idcr Idci

CIGRE benchmark 1000MW HVDC

Y Y

YY

Y Y

fs

Rg

dctα

∆ ∆

25MW

Qactc

Vact

Vactc

dcrecα

dcrecα

dcinvα

dcinvα

α - Firing angle,f - operating frequency

It1

It2

L13 C

13

L23 C

23

Figure 5. Line commutated HVDC tap with DC transformer connected to CIGRE HVDC Benchmark system.

kp+ki/s

PI controllerPdct1ref- fs

XIdct1

Vdct1

nn ως ,filtering

minVdct1

Vdct2

Pdct1

Figure 6. Controller for DC/DC converter.

kp+k

i/s

PI controller-

nn ως ,

+

filtering

10=dctrefγ

dctγ

γα

min

kp+k

i/s

PI controller-

nn ως ,

+

filtering

Qactref

=0

Qact

Qα

dctα

+

+

90

X

recinv

0

−=

inverter

rectifierrecinv

1

1

α - Firing angle,γ - Extinction angle

Figure 7. Controller for line commutated AC/DC converter

Considering the tap system (DC/DC and AC/DC converters) as a multivariable control system, we have two control

inputs (αdct, and fs) and two outputs (Pdct1 and Qact). In order to analyse the control strategy and controllability of this

system the following LCC converter steady-state equations [10] are used:

101

3cos

23dcttapdctactcdct ILVV ω

πα

π−= (6)

≈ actcdctdct VV

πθ

23/cos 1 (7)

111 dctdctdct VIP = (8)

dctdctactc PQ θtan1= (9)

where θdct is the tap converter power factor angle, and all other variables are defined in Figures 5-7.

Using (6)-(9), and also (1), the steady-state output variables can be calculated as the function of control signals, as

shown in Figures 8 and 9. Figure 8 studies the active power control channel, assuming that the reactive power controller

maintains Qact=0MVar (Qactc=6.5MVar). The target power level is given on the abscissa and the required values for

control signals are shown on the ordinate axes. The tap power is regulated by changing DC transformer operating

frequency fs, but it is seen that the fs curve becomes non-linear and control gain approaches infinity at powers below

0.05p.u. This may not be issue since HVDC converters are rarely operated below 0.1-0.2p.u power, (because of

problems with discontinuous current). Since αdct varies significantly in this figure, it is concluded that there is unwanted

cross-coupling between the two control channels. It is concluded that a high-performance controller would need

decoupling loops and some gain scheduling. However, simple PI controllers have proven to give reasonable responses.

Figure 9 shows the steady-state curves for controlling tap reactive power. Clearly, reactive power can be controlled

with the AC/DC converter firing angle (αdct), and a 40deg angle range enables approximately 20MVAr variation. The

above study demonstrates that the proposed tap terminal can independently control active and reactive power. The

ability to control reactive power brings significant advantage with HVDC converters since the maintenance costs with

switchable capacitor banks are reduced and stability improves.

Figure 10 shows the PQ operating range for the tap terminal where the operating point can be anywhere within the

area. If the reactive power from filters is employed, then the whole diagram slides down and shifts the operating range

into negative reactive power. Note that the reactive power control is achieved using DC voltage variation.

100

200

300

400

500

600

0 5 10 15 20 25

Power [MW]

Frequency [Hz]

0

20

40

60

80

100

Tap angle [deg]

dctα

sf

maxsf

Figure 8. Active power control using fs (assuming Qactc=6.5MVar).

400

500

600

700

800

900

0 5 10 15 20 25

Reactive Power [MVar]

Frequency [Hz]

0

10

20

30

40

50

Tap angle [deg]

dctα

sfmaxsf

Figure 9. Reactive power control (assuming Pdct1=25MW).

-30 -20 -10 0 10 20 300

5

10

15

20

25

Power Pdct1 [MW]

Reactive Power Qactc [MVar]

Limit fsm

ax

Lim

it f sm

ax

Inverter Rectifier

minαLimit

Lim

it P

min

Lim

it P

min

Figure 10. Controllable operating range for the tests system

B. Voltage source converter

A voltage source converter is also studied as a tap AC/DC converter, as shown in Figure 11. A VSC converter would

bring advantages of lower harmonics, the ability to supply dead networks and wider reactive power exchange.

Since a VSC converter can only reverse current direction, the DC/DC converter of type 2, as shown in Figure 2, is

employed. The nominal voltage level (Vdct1) is different from that in Figure 5 and the DC/DC converter will have

different parameters. The VSC converter is rated to 25MW, 56kV (DC). The filters are tuned to 31th

, 35th

and 61

st

frequencies with an additional high pass filter, considering that PWM modulation ratio is 33. The VSC converter

controller is shown in Figure 12. This is a typical 2-channel cascade and decoupled controller which enables regulation

of DC voltage and reactive power [11]. The controller for DC/DC converter is same as in Figure 6.

-250kV

+250kV+28kV

-28kV

33kV

33kV

25MWCf1

Cf1

Cf2

Cf2

Rf2

Rf2

Ltap

LactR

act

L31

L35

Lhp C

hp

Rhp

C35

C31

Vdct1 V

dct2

Idct2I

dct1

Pact,Qact

fs

Rg

xM yM

25MW

DC/DC type 2

\ \

Vact

- Control signal x-component

- Control signal y-component

It1

It2

xMyM

L61 C

61

Figure 11. HVDC tap with VSC converter and DC transformer.

IACxref

My

Mx

+-

+-

IACy

Iacyref

+

+-

1

-1

Vdct1ref

Vdct1

sKd1/(T

ds+1)

++-

1

-1

+

sKd1/(T

ds+1)

kp1+kI1/s +

+

Qactcref

Qactc

IACx

+-

)( tapACt LL +ω

-

kp3+kI3/s

kp2+kI2/s k

p1+kI1/s

)( tapACt LL +ω

Figure 12. Controller for VSC HVDC tap

C. Comparison with conventional HVDC taps

Figure 13 shows a conventional HVDC tap that would be used based on the existing technology. A similar topology

is used for Corsica tap and for all terminals on Quebec-New England HVDC, however with unidirectional valves [3].

The tap converter is rated to 25MW/500kV, and it uses bidirectional thyristor valves [12]. The bidirectional valves

enable fast tap power reversal without affecting voltage polarity on the main HVDC line. The control system can be a

conventional HVDC controller. Table 1 compares the main components required for taps in Figures 5, 11 and 13. The

main cost penalties with conventional taps (Figure 13) are associated with the two components (AC transformer and

AC/DC converter) which must be rated for high-voltage. In addition, the conventional tap has the following operational

and performance issues:

• In inversion mode, the tap converter is vulnerable to commutation failure. This is a significant issue with tap

terminals since the tap AC grid is typically weak. A commutation failure on tap converter shorts DC voltage on the

main HVDC link, and causes a major fault.

• The tap active control is possible but the converter must operate at large firing angles. This implies large reactive

power demand and large commutation overlap caused by high transformer impedance. Typically, on parallel taps,

reactive power demand would be similar to the active power transfer [4], ie 25MVAr. This has cost implications

and causes stability problems.

• The reactive power demand is highly variable, as the tap active power changes. Switchable capacitor banks are

needed and frequent switchings will be experienced. This implies operating cost increase for circuit breakers, and

power quality issues. The AC transformer should have on-load tap changer.

It is noted that a conventional tap may be based on a VSC converter and AC transformer (VSC instead of LCC

converter in Figure 13). Such topology would eliminate the above issues 2 and 3 (reactive power related). However, the

cost of 500kV VSC converter would be very high and the most important issue, with fault propagation to the main

HVDC link, remains an open problem.

Comparing the losses for considered tap cases, it can be conservatively assumed that the 25MW AC/DC converter

will have similar losses in each topology (regardless of the voltage level). Consequently, losses of the DC/DC converter

should be weighted against the AC transformer losses. Considering results in Figure 4, clearly the conventional tap will

have lowest losses. Therefore careful further trade off analysis between performance, costs and losses is required.

-250kV

33kV25MW

Lf1

Lf1

Ltap

Idct1

dctα

+250kV

Y ∆33kV/384kV

33kV LactRact

L5

L7

L11

LhpChp

Rhp

C11

C7

C5

Pact,Qact

Vact

Figure 13. Conventional line commutated tap with AC transformer

1) LCC tap with DC/DC

converter (Figure 5)

2) VSC tap with DC/DC

converter (Figure 11)

3) LCC tap with AC

transformer (Figure 13)

Number Voltage Current Number Voltage Current Number Voltage Current

DC/DC converter

T1-T2 4 500kV 295A 8 500kV 230A - - -

T5-T8 8 500kV 25A 8 500kV 25A - - -

L1 2(135mH) 500kV 590A 2(200mH) 500kV 460A - - -

AC/DC converter

Thyr/IGBT 6 (Thyr) 26.9kV 440A 6 (IGBT) 26.9kV 440A 12 (Thyr) 313 38A

Ltap 3 (18mH) 26.9kV 440A 3 (10mH) 26.9kV 440A - - -

AC transformer

- - - - - - 1 384/33kV 38/440A TABLE 1 COMPONENT RATING COMPARISONS FOR TAPS IN FIGURES 4, 10 AND 12.

IV. SIMULATION RESULTS

A. Test system

A full test system model is developed on PSCAD/EMTDC simulator [13] for the topology with LCC tap in Figure 5

and for VSC tap in Figure 11. The converter switches are modelled in detail based on Silicon Power components with

5µs step, and all the test system parameters are given in the Appendix. The system is tested for tap power ramping,

power reversal, single and three phase faults on the tap AC system.

B. Tap with line commutated converter

Figure 14 shows PSCAD simulation for LCC tap in version mode. At 0.1s a full tap power reversal (-25MW ->

25MW) is applied and at 0.4s the tap power is reversed to -25MW. At 1s, a 0.1s zero-impedance 3-phase fault is applied

at converter station bus Vact of LCC tap, and at 1.5s a zero-impedance single-phase fault is applied at the same place.

In Figure 14a) we observe that the tap power follows the power reference and power reversal is fast. In Figures

14b),c) and d) the inner converter variables are depicted where it can be seen that the tap DC voltage Vdct1 changes

polarity when the power reverses. Figure 14e) proves that the proposed control enables reactive power regulation in

either rectification or inversion mode.

It is important to study the extinction angle (γdct) in Figure 14f) and the tap DC voltage Vdct1 in Figure 14d) during the

faults. As it is expected, during the faults there are commutation failures on tap AC/DC converter as seen by zero

extinction angle and DC voltage. However these faults are not propagated to the main HVDC system because of the

appropriate response of DC/DC converter. The DC/DC converter naturally reduces the power and it acts like open

circuit on high-voltage side, for voltage depressions on low voltage side. This can be confirmed by observing DC

voltage and current of the main HVDC in Figures 14g) and h). The main HVDC system experiences only small

disturbances during the 50MW power swings and the severe faults on tap system.

It is concluded that even extreme faults on the tap AC system can not disturb operation of the main HVDC line. This

resilience to disturbances on tap AC systems is a major advantage of the proposed topology, and it opens possibility for

multiple small taps without reducing reliability of the main HVDC line. The authors have tested a range of similar faults

for different values of circuit parameters (including Cf and Ltap) and very good resilience to faults is typically observed,

except for some extreme parameters. The tap operation in rectifier mode is less difficult and tests show satisfactory

responses.

It can be readily deduced that the tap terminal can maintain constant power even if the main HVDC reverses power

(by reversing DC voltage), which is not shown.

-30

-20

-10

0

10

20

30

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Power [MW]

0

100

200

300

400

500

600

700

800

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Frequency [Hz]

-0.5

0

0.5

1

1.5

2

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

DC current [kA]

-50-40-30-20-1001020304050

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Voltage [kV]

-15

-10

-5

0

5

10

15

20

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Reac. Power [MVar]

0

20

40

60

80

100

120

140

160

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Angle [deg]

1.5

2.0

2.5

3.0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

DC current [kA]

300

400

500

600

DC Voltage [kV]

0

20

40

60

80

100

120

140

160

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Angle [deg]

a) DC/DC converter power b) DC/DC converter frequency

c) DC/DC converter currents d) LCC tap converter DC and AC voltage

e) LCC tap converter reactive power f) LCC tap converter angles

g) HVDC DC voltage and current h) HVDC operating angles

Pdc1

Pdc1ref

It1

It2

Qact

Qactref

Vdc

IdcrI

dcrref

αdcrec

αdcinv

γdct

γdctref

αdct

Vdct1

Vact

fs

Figure 14. Simulation results with LCC tap. At 0.1s Power reversal -25MW->25MW->-25MW, at 1.0s a 0.1s, 3-phase

fault on Vact, and at 1.5s at 0.1s, single phase fault on Vact.

C. Tap with a Voltage Source Converter

Figure 15 show PSCAD simulation with the VSC tap. The same sequence of external disturbances is applied as with

LCC tap in Figure 14. The initial power reversal indicates good control coordination. It is noted that DC voltage Vdct1

does not change polarity for power reversal with VSC converters, but current Idct1 does. The low-impedance AC system

faults at 1.0s and 1.5s cause significant disturbance on AC/DC converter and the DC voltage (Vdct1) experiences large

swings. Evidently, these faults would cause significant disturbance on the main HVDC line if DC/DC converter is not

used. The DC/DC converter shields the main HVDC line from faults on tap AC system. Note that 75kV surge arrester

are used on Vdct1 with VSC converters (as it is normal practice with HVDC light) to prevent damaging DC voltages

during fault recoveries.

It is important to study the tap system harmonics across different operating points because of the use of frequency

controlled DC/DC converter. As the power transfer is reduced the dominant harmonics from DC/DC converter move to

lower frequencies which can be challenging to compensate with conventional tuned filters. Table 2 shows the Total

Harmonic Distortion (THD) on the tap AC terminal voltage (Vact) considering up to 63rd

harmonic, for variations in tap

power. It is evident that the THD is below the standard limit of 1.5% even for power reduction to 0.12p.u. At low

powers the current pollution will increase relative to the current magnitude, but because of the lower fundamental

current, the final effect is that terminal voltage has similar harmonic pollution at all power levels. These simulations

confirm that the use of DC/DC converters does somewhat increase the harmonics but it is feasible to design the system

with conventional passive filters to operate within the standard harmonic pollution.

It is noted that the tap system is optimised for low costs considering the use of 6-pulse thyristor bridge and no

transformers. Such system may not be able to meet harmonic standards for different AC grids (as an example with low

SCR). With weak AC systems a 12-pulse AC/DC converter may be required in which case a Y/∆ (33/33kV) tap

transformer is necessary.

The DC/DC converter may also increase the harmonics on DC side which may exacerbate electro-magnetic

interference, however these effects are not considered in our study.

0

100

200

300

400

500

600

700

800

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Frequency [Hz]

0

10

20

30

40

50

60

70

80

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Voltage [kV]

-30

-20

-10

0

10

20

30

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Power [MW]

-0.5

0

0.5

1

1.5

2

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

DC current [kA]

-1-0.8-0.6-0.4-0.20

0.20.40.60.81

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

VSC control Mx,My

-15

-10

-5

0

5

10

15

20

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Reac. Power [MVar]

0

20

40

60

80

100

120

140

160

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

Angle [deg]

1.5

2.0

2.5

3.0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time [s]

DC current [kA]

300

400

500

600

DC Voltage [kV]

a) DC/DC converter power b) DC/DC converter frequency

c) DC/DC converter currents d) LCC tap converter DC and AC voltage

e) VSC tap converter reactive power f) VSC tap control signals

g) HVDC DC voltage and current h) HVDC operating angles

Pdc1

Pdc1ref

It1

It2

Qact

Qactref

Vdc

IdcrI

dcrref

αdcrec

αdcinv

My

Vdct1

Vact

fs

Mx

Figure 15. Simulation results with VSC tap. At 0.1s Power reversal -25MW->25MW->-25MW, at 1.0s a 0.1s, 3-phase

fault on Vact, and at 1.5s at 0.1s, single phase fault on Vact.

Tap power

[MW]

LCC tap THD

[%]

VSC tap THD

[%]

25 0.7 0.8

20 1.2 0.8

15 1.4 0.7

10 1.5 0.8

5 1.5 1.1

3 1.5 1.3

TABLE 2. THD ON VACT OVER POWER TRANSFER RANGE

V. CONCLUSIONS

This paper proposes a new topology for tap terminals on HVDC transmission, based on DC/DC converters. Because

of the voltage stepping on DC side it is concluded that the new topology may offer numerous advantages like immunity

from disturbances on tap AC grid, control of reactive power and possibly lower costs by eliminating AC transformers.

The presented topology can be readily applied to taps based on Line Commutated or Voltage Source tap converters.

The PSCAD simulation results demonstrate that a 25MW tap can operate on a 1000MW CIGRE Benchmark system

in wide range of power transfer levels. The detailed simulation results conclude that even most severe disturbances on

the tap grid will not cause operating problems on the main HVDC link.

VI. APPENDIX TESTS SYSTEM

parameter LCC tap VSC tap

DC-DC converter

fs [Hz] 600 600

V1 [kV] 43 56

V2 [kV] 500 500

I1av [A] 590 460

I2av [A] 50 50

Cr [µF] 1.9 1.45

L1 [mH] 135 160

L2 [mH] 1.5 1.5

α2up [deg] 180 180

α2down [deg] 127 134

Toff [µs] (T1-T8) 500 500

Tap AC grid

Lact [mH] 7 7

Ract [Ω] 0.4 0.4

Vact [kV] 33 33

Tap AC/DC converter

Ltap [mH] 18 10

Cf1 [µF] 200 500

Lf1 [mH] 50 0

Cf2 [µF] 200 200

Rf2 [mΩ] 6 6

Rg [Ω] 50000 50000

[µF] C5=7 C31=1

[mH] L5=57.9 L31=10.5

[µF] C7=5 C35=1

[mH] L7=41.4 L35=8.3

[µF] C11=4 C61=2

[mH] L11=20.9 L61=1.4

[µF] C13=3 -

[mH] L13=20 -

[µF] C23=1 -

[mH] L23=19.2 -

[µF] Chp=8 Chp=2

[mH] Lhp=28 Lhp=10

[Ω] Rhp=180 Rhp=200

TABLE A.1 TEST SYSTEM PARAMETERS

L1 (LCC) L1 (VSC) L2

Inductance L [mH] 135 200 4

Average current [A] 590 460 50

Core size, R1 [m] 0.6 0.6 0.2

Core size, R2 [m] 0.35 0.35 0.13

Wire radius Rc [mm] 7.6 6.9 3.6

Total resistance [mΩ] 310 454 121

Number of turns 1437 1549 510

Copper mass [kg] 5237 5365 107

Total loss [kW] 132 118 0.37

TABLE A.2 INDUCTOR DATA

R1

R2

Rc

Fig. A.1 Toroidal air-core inductor dimensions.

VII. ACKNOWLEDGEMENTS

The authors are thankful for the financial support from the Royal Academy UK, and National Research Council

Canada.

VIII. REFERENCES

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Power Delivery, Vol. 4, No. 1, Jan. 1989, pp: 794-9.

[2] Donahue, J.A.; Fisher, D.A.; Raling, B.D.; Tatro, P.J.; “Performance testing of the Sandy Pond HVDC

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[3] Long, W.F.; Reeve, J.; McNichol, J.R.; Holland, M.S.; Taisne, J.P.; LeMay, J.; Lorden, D.J.; “Application

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1990 pp: 2084 - 2098

[4] Bahram, M.; Baker, M.; Bowles, J.; Bunch, R.; Lemay, J.; Long, W.; McConnach, J.; Menzies, R.; Reeve, J.;

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[5] J. Reeve, "Multiterminal HVDC Power Systems," IEEE Transactions on Power Apparatus and Systems, Vol. 99,

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[6] Kjell Ericsson "Operational Experience of HVDC Light" Seventh International Conference on AC-DC Power

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[7] W.Lu, B.T. Ooi, “Optimal Acquisition of Offshore Wind Power by Multi-Terminal Voltage –Source HVDC,

IEEE Transactions on Power Delivery, Vol 18, No. 1, January 2003, pp: 201-206.

[8] D.Jovcic, “Bidirectional high power DC transformer” IEEE Transactions on P.D. Vol. 24, issue 4, October

2009, pp 2276-2283.

[9] M. Szechman, T. Wess and C.V. Thio, "First Benchmark model for HVDC control studies", Electra No. 135,

April 1991, pp 54-73.

[10] Kundur,P “Power System Stability and Control” McGraw Hill, Inc 1994.

[11] D.Jovcic and N Strachan “Offshore Wind farm with centralised power Conversion and DC Interconnection” IET

Generation, Transmission and Distribution, Vol 3, issue 6, June 2009 pp 586-595.

[12] Barthold, L.O, “Technical and Economic Aspects of Tripole HVDC.” International conference on Power System

Technology, Powercon 2006, Chongqing, pp:1-6

[13] Manitoba HVDC Research Center “PSCAD/EMTDC users manual,” Winnipeg 2003.