Synthesizable VHDL LC-2Created By:

Eric Frohnhoefer&

Ron Feliciano

Under the Direction of:Professor Frank Vahid

Introduction

Introduction

Synthesizable LC-2 Model

•Introduction into VHDL (5 min)

•LC-2 overview (5 min)

•Demonstration of fetch cycle (15 min)

•Researching (5 min)

•Question and Answer (remaining time)

Introduction into VHDL

VHDL = (Very High Speed Integrated Circuit) Hardware Description Language

VHDL is a programming language used for verification and synthesis of digital designs.

What is VHDL??

What do we use VHDL for??

Features of VHDL

•High level language

•Allows for rapid development of digital designs

•Syntactically similar to C++

•Various methods of hardware description

•High level system verification

VHDL code C++ code

Introduction into VHDL

if ( condition ){ expression; }

if ( condition ) then expression;end if;

case ( variable ) is when condition => Expression;end case;

switch ( variable ) {case condition : expression;break;}

Operators= comparison:= assignment<= assignment/= not equal

Operators= assignment== comparison!= not equal

Introduction into VHDL

LC-2 ALU VHDL Codelibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;--LC-2 ALU---------------------------------------entity LC2_ALU is port( A: in std_logic_vector (15 downto 0); B: in std_logic_vector (15 downto 0); S: in std_logic_vector (1 downto 0); O: out std_logic_vector (15 downto 0));end LC2_ALU;

architecture bhv of LC2_ALU isbegin process(A, B, S)begin

case S is when "00" => O <= A+B; when "01" => O <= A and B; when "10" => O <= A; when "11" => O <= not A; when others => null; end case;

end process;end bhv;

Standard VHDL Libraries

Overall structure of component (input and outputs)

Start of behavioral code

Code that describes actual process

LC-2 Logic Components

Basic Logic Components

Register/Register Bank

Arithmetic Logic Unit (ALU)

Data 3:3

Data 2:2

Data 1:1

Data 0:0

System Bus

enable

OUT

A B

Sel ALU

Tri-State buffer

enable

IN

OUT

Sel(0:1) Sel(1:1) Out

0 0 A + B

0 1 A and B

1 0 A

1 1 not A

IN En OUT

1 1 1

0 0 Z

1 0 Z

0 1 0

WriteEnable

ADDR (0-2)

DataIn (0-15)

DataOut (0-15)

Reg Bank

LC-2 Overview

Instruction Cycle

•Fetch - Fetch next instruction from main memory as indicated by the Program Counter (PC)

•Decode - Decodes the instruction returned by the fetch cycle.

•Address Evaluation - Calculate address of data and load into Memory Address Register (MAR).

•Operand Fetch - Load data into Memory Data Register (MDR).

•Execute - Perform given operation.

•Store Result - Store result into memory.

Addressing modes

•Immediate Mode (LEA) - DR = PC[15:9] @ pgoffset9

•Direct Mode (LD) - DR = mem[PC[15:9] @ pgoffset9]

•Indirect Mode (LDI) - DR = mem[mem[PC[15:9] @ pgoffset9]]

•Base+Offset Mode (LDR) - DR = mem[BaseR + ZEXT(index6)]

PC_Gate <= ‘1’MAR_ld <= ‘1’

LC-2 Fetch Cycle

PC_gate <= ‘0‘MAR_ld <= ‘0’Read_Write <= ‘1’MIO_enable <= ‘1’

LC-2 Fetch Cycle cont’d

MIO_enable <= ‘0’MDR_ld <= ‘1‘

LC-2 Fetch Cycle cont’d

MDR_ld <= ‘0’ MDR_gate <= ‘1’IR_ld <= ‘1’PC_mux <= "00"PC_ld <= ‘1’

LC-2 Fetch Cycle cont’d

IR_ld <= ‘0’ PC_ld <= ‘0’MDR_gate <= ‘0’

LC-2 Fetch Cycle cont’d

LC-2 Stats

component I/O Ports

Combinational Area (gates)

Sequential Area (gates)

Critical Path

(ns)

Max Clock speed (MHz)

Synthesis Time (sec)

LC2_ctrl 55 577 545 1.31 763 52

LC2_alu 50 242 0 20.3 49 16

LC2_reg_bank

59 766 1504 1.37 730 33

LC2_all 2 2781 4886 20.3 49 190

Here are some of the statistics we obtained by synthesizing the LC-2 model down to gate level, using the Synopsys Design Compiler with medium mapping effort. We left the ram_modules in behavioral level code since they would normally not be synthesized into logic but rather loaded into a memory.

•www.cs.ucr.edu/~efrohnho

•www.cs.ucr.edu/~rfelicia

•http://www.cs.ucr.edu/~vahid/sproj/lc2/index.html

Eric’s Webpage

Ron’s Webpage

LC-2 Webpage

Tips for finding interesting research opportunities:

•Find something that interests you.•Take relevant course work.•Do well in your classes.•Get to know your professors.•Don’t be afraid to ask.

What to expect:

•Work hard.•Work independently or with a small group.•Not to be paid.

Benefits of doing research:

•Looks good on resume.•Give you a chance to explore your field.•Make you more competitive in the work force.

Researching