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SynthesisQuick Reference

Version 2002.05, June 2002

Copyright Notice and Proprietary InformationCopyright 2002 Synopsys, Inc. All rights reserved. This software and documentationcontain confidential and proprietary information that is the property of Synopsys, Inc. Thesoftware and documentation are furnished under a license agreement and may be used orcopied only in accordance with the terms of the license agreement. No part of the softwareand documentation may be reproduced, transmitted, or translated, in any form or by anymeans, electronic, mechanical, manual, optical, or otherwise, without prior writtenpermission of Synopsys, Inc., or as expressly provided by the license agreement.Right to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of thedocumentation for its internal use only. Each copy shall include all copyrights,trademarks, service marks, and proprietary rights notices, if any. Licensee mustassign sequential numbers to all copies. These copies shall contain the followinglegend on the cover page:

“This document is duplicated with the permission of Synopsys,Inc., for the exclusive use of__________________________________________ and itsemployees. This is copy number __________.”

Destination Control StatementAll technical data contained in this publication is subject to the export control lawsof the United States of America. Disclosure to nationals of other countriescontrary to United States law is prohibited. It is the reader’s responsibility todetermine the applicable regulations and to comply with them.DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANYKIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OFMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.Registered Trademarks (®)Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, CoCentric,COSSAP, CSim, DelayMill, DesignPower, DesignSource, DesignWare, Eaglei,EPIC, Formality, in-Sync, LEDA, ModelAccess, ModelTools, PathBlazer, PathMill,PowerArc,PowerMill,PrimeTime,RailMill,SmartLogic,SmartModel,SmartModels,SNUG, Solv-It, SolvNet, Stream Driven Simulator, System Compiler, TestBenchManager, TetraMAX, TimeMill, and VERA are registered trademarks of Synopsys,Inc.Trademarks (™)BCView, Behavioral Compiler, BOA, BRT, Cedar, ClockTree Compiler, DC Expert,DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, DesignAnalyzer, Design Compiler, DesignSphere, DesignTime, Direct RTL, Direct SiliconAccess, DW8051, DWPCI, ECL Compiler, ECO Compiler, ExpressModel, FloorplanManager, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, HDLAdvisor, HDL Compiler, Integrator, Interactive Waveform Viewer, Liberty, LibraryCompiler, ModelSource, Module Compiler, MS-3200, MS-3400, NanoSim,OpenVera, Physical Compiler, Power Compiler, PowerCODE, PowerGate,ProFPGA, Protocol Compiler, RoadRunner, Route Compiler, RTL Analyzer,Schematic Compiler, Scirocco, Shadow Debugger, SmartLicense, SmartModelLibrary, Source-Level Design, SWIFT, Synopsys EagleV, SystemC, SystemC(logo), Test Compiler, TestGen, TimeTracker, Timing Annotator, Trace-On-Demand,VCS, VCS Express, VCSi, VHDL Compiler, VHDL System Simulator, VirSim, andVMC are trademarks of Synopsys, Inc.

Service Marks (SM)DesignSphere, SVP Café, and TAP-in are trademarks of Synopsys, Inc.

synqr.book Page ii Thursday, May 23, 2002 4:42 PM

Printed in the U.S.A.

Document Order Number: 13482-000 MASynthesis Quick Reference, v2002.05

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Contents

Man Page Viewing and Printing Instructions . . . . . . . . . 1

User Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Synthesis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Synthesis Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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Man Page Viewing and PrintingInstructionsThe following sections describe how to set up yourUNIX environment so you can view and print man pages.

Setting Up the UNIX EnvironmentEdit your .cshrc file to contain these lines:

setenv SYN_MAN_DIR synopsys_root/doc/syn/mansetenv MANPATH ${MANPATH}:${SYN_MAN_DIR}

SYN_MAN_DIR is a variable that contains the path tothe man page directories, and synopsys_root representsthe specific path to the Synopsys synthesis softwaredirectory at your site.

Viewing Man Pages From UNIXCommand

% man command_name

Variable% man variable_name

Variable group% man variable_group_name

All attributes% man attributes

Attribute group% man attribute_group_name

Error, warning, or information message% aman message_id

Viewing Man Pages From dc_shellCommand

dc_shell> man command_name

Variabledc_shell> man variable_name

Man Page Viewing and Printing Instructions 1

2


Variable groupdc_shell> man variable_group_name

All attributesdc_shell> man attributes

Attribute groupdc_shell> man attribute_group_name

Error, warning, or information messagedc_shell> man message_id

Printing Man Pages From UNIXUser command

% lpr -t -P printer_name \ $SYN_MAN_DIR/fmt1/command_name.1

Synopsys command% lpr -t -P printer_name \ $SYN_MAN_DIR/fmt2/command_name.2

Variable% lpr -t -P printer_name \ $SYN_MAN_DIR/fmt3/variable_name.3

Variable group% lpr -t -P printer_name \ $SYN_MAN_DIR/fmt3/variable_group_name.3

All attributes% lpr -t -P printer_name \ $SYN_MAN_DIR/fmt3/attributes.3

Attribute group% lpr -t -P printer_name \ $SYN_MAN_DIR/fmt3/attribute_group_name.3

You cannot print error, warning, or information messageman pages from UNIX.

Printing Man Pages From dc_shellYou cannot print man pages from dc_shell.

Man Page Viewing and Printing Instructions


User CommandsInvoke user commands from a UNIX shell.

bc_viewRuns the BCView performance analysis tool.

bc_view[-f project_file][-license_preference package | individual]

amanDisplays Synopsys extended error messages.

aman [error_message_code]

cache_lsLists elements in a Synopsys cache.

cache_lscache_dirreg_expr

cache_rmRemoves elements from a Synopsys cache.

cache_rmcache_dirreg_expr

create_typesExtracts user-defined type information from VHDLpackage files.

create_types[-nc][-w lib][-v][-o logfile]file_list

User Commands 3

4


dc_shell-tInvokes the Design Compiler shell in dctcl mode. Formore information, see the man page for dc_shell.

dc_shell-t[-f script_file][-x command_string][-no_init][-checkout feature_list][-wait wait_time][-timeout timeout_value][-version][-behavioral][-fpga][-syntax_check | -context_check]

dc_shellInvokes the Design Compiler command shell.

dc_shell[-f script_file][-x command_string][-no_init][-checkout feature_list][-tcl_mode][-wait wait_time][-timeout timeout_value][-version][-behavioral][-fpga][-syntax_check | -context_check]

design_analyzerRuns the Design Analyzer menu interface in the XWindow System.

design_analyzer[-menu_script][-no_menu_script][-f script_file][-x command_string][-no_init][-checkout feature_list][-timeout timeout_value][-version][-behavioral][-fpga][-syntax_check | -context_check]

User Commands


design_visionRuns Design Vision visualization for Synopsyssynthesis products.

design_vision[-f script_file][-x command_string][-no_init][-checkout feature_list][-timeout timeout_value][-version][-behavioral][-syntax_check | -context_check][-tcl_mode]

lc_shellRuns the Library Compiler command shell.

lc_shell[-f script_file][-x command_string][-no_init][-version]

library_compilerRuns the Library Compiler graphical interface in theX window system.

library_compiler[-f script_file][-x command_string][-no_init][-version]

ra_shellRuns the RTL Analyzer command shell.

ra_shell[-f script_file][-x command_string][-no_init][-checkout feature_list][-timeout timeout_value][-version]

User Commands 5

6


synencRuns the Synopsys Encryptor for HDL source code.

synenc[-r synopsys_root]file_list

synopsys_usersLists the current users of the Synopsys licensedfeatures.

synopsys_users [feature_list]

User Commands


Synthesis CommandsThis section contains the following subsections:

• Command Syntax

• Commands Specific to dcsh Mode

• Commands Specific to dctcl Mode

Command SyntaxInvoke these commands from within a synthesis tool.Unless otherwise noted, all commands are available inboth dcsh and dctcl mode.

acs_check_directories (dctcl-mode only)

Checks Automated Chip Synthesis (ACS) directorystructure settings for correctness. For use in dc_shell-t(Tcl mode of dc_shell) only.

int acs_check_directories

acs_compile_design (dctcl-mode only)

Compiles the constrained RTL to a netlist usingconstraints propagated from the top-level design. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

int acs_compile_design[-destination pass_name][-prepare_only][-force][-update][-update_source source_pass]design_name

acs_create_directories (dctcl-mode only)

Creates the project directory tree for Automated ChipSynthesis. For use in dc_shell-t (Tcl mode ofdc_shell) only.

int acs_create_directories

Synthesis Commands 7

8


acs_get_parent_partition (dctcl-mode only)

Creates a collection of designs that are compilepartitions and that contain the specified subdesign.For use in dc_shell-t (Tcl mode of dc_shell) only.

string acs_get_parent_partitiondesign_name[-hierarchy][-list]

acs_get_path (dctcl-mode only)

Gets the path location for the specified file. To specifya file, specify its file type and, for pass-dependentfiles, its pass directory. For use in dc_shell-t (Tclmode of dc_shell) only.

string acs_get_path-file_type filetype[-mode read | write][-pass pass_name][[-name filename][-append]][-relative]

acs_merge_design (dctcl-mode only)

Preprocesses a design for incremental design updateby merging the modified designs and their parentcompile partitions with the mapped design beingupdated. For use in dc_shell-t (Tcl mode of dc_shell)only.

int acs_merge_design-update design_list[-unmapped source_dir][-mapped data_dir][-type pre | post][-destination dest_dir]design_name

Synthesis Commands


acs_read_hdl (dctcl-mode only)

Reads in the HDL source code of a design andgenerates the GTECH representation in memory. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

int acs_read_hdl[design_name][-hdl_source file_or_dir_list][-exclude_list file_or_dir_list][-format {verilog | vhdl}][-recurse][-no_dependency_check][-no_elaborate][-ignore_analyze_errors][-library design_lib_name][-verbose]

acs_recompile_design (dctcl-mode only)

Compiles an unmapped constrained .db file usingtime budgets. The time budgets are created by using apreviously-mapped design. For use in dc_shell-t (Tclmode of dc_shell) only.

int acs_recompile_design-budget_source budget_pass-destination destination_pass[-source source_pass][-prepare_only][-force][-update][-update_source source_pass]design_name

acs_refine_design (dctcl-mode only)

Refines an already mapped design. For use indc_shell-t (Tcl mode of dc_shell) only.

int acs_refine_design[-source pass_name][-destination pass_name][-prepare_only][-force][-update][-update_source source_pass]design_name


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acs_report_directories (dctcl-mode only)

Reports the current directory structure settings. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

int acs_report_directories[-file_types type_list]

add_moduleReads in a specified library file containing modulefunctional information and uses it to update anexisting technology library.

int add_module[-overwrite][-permanent]file_namelibrary_name[-no_warnings]

add_to_collection (dctcl-mode only)

Adds objects to a collection, resulting in a newcollection. The base collection remains unchanged.

collection add_to_collectionbase_collectionobject_spec[-unique]

after (dctcl-mode only)

Built-in Tcl command.

aliasDefines an alias for a command, or lists current aliasdefinitions.

int alias [identifier [expansion]]

all_clocksReturns a list of all clocks in the current design. Indctcl mode, a collection is returned.

list all_clocks()

Synthesis Commands


all_cluster_cellsReturns a list of cells contained in the specifiedcluster. In dctcl mode, a collection is returned.

list all_cluster_cells[-hierarchy]cluster_name

all_clustersReturns a list of subclusters associated with aspecified cluster or with the current design. In dctclmode, a collection is returned.

list all_clusters[-cluster cluster_name][-leaf]

all_connectedReturns the objects connected to a net, port, pin, or anet or pin instance.

list all_connected object

all_critical_cellsReturns a list of critical leaf cells in the top hierarchyof the current design. In dctcl mode, a collection isreturned.

list all_critical_cells[-slack_range range_value]

all_critical_pinsReturns a list of critical endpoints or startpoints in thecurrent design. In dctcl mode, a collection is returned.

list all_critical_pins[-type endpoint | startpoint][-slack_range range_value]

all_designsReturns a list of all designs in the current design. Indctcl mode, a collection is returned.

list all_designs


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all_faninReports pins, ports, or cells in the fanin of specifiedsinks.

list all_fanin-to sink_list[-startpoints_only][-exclude_bboxes][-break_on_bboxes][-only_cells][-flat][-levels count]

all_fanoutReturns a set of pins, ports, or cells in the fanout ofthe specified sources.

list all_fanout-clock_tree-from source_list[-endpoints_only][-exclude_bboxes][-break_on_bboxes][-only_cells][-flat][-levels count]

all_inputsReturns a list of input or inout ports in the currentdesign. In dctcl mode, a collection is returned.

list all_inputs[-clock clock_name][-edge_triggered | -level_sensitive]

all_outputsReturns a list of output or inout ports in the currentdesign. In dctcl mode, a collection is returned.

list all_outputs[-clock clock_name][-edge_triggered | -level_sensitive]

Synthesis Commands


all_registersReturns a list of sequential cells or pins in the currentdesign. In dctcl mode, a collection is returned.

list all_registers[-no_hierarchy][-clock clock_name][-cells][-data_pins][-clock_pins][-slave_clock_pins][-inverted_output][-output_pins][-level_sensitive | -edge_triggered][-master_slave]

allocate_budgets (dcsh-mode only)

Allocates budgets to the specified cells.

string allocate_budgets[-incremental][-check_only][-create_context][-no_boundary_annotations][-effort allocation_effort][-min_register_to_output minimum_budget][-min_input_to_output minimum_budget][-min_input_to_register minimum_budget][-no_environment][-interblock_logic][-file_format_spec format_spec][-format script_format][-separator name_separator][-levels budget_levels][-write_context][-budget_design_ware][cell_list]


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allocate_partition_budgets (dctcl-mode only)

Creates budgets for the compile partitions in thespecified design. For use in dc_shell-t (Tcl mode ofdc_shell) only.

int allocate_partition_budgets-source src_pass-destination dst_pass[-absolute_paths][-budget_shell budget_shell_exec][-transcript_exec transcript_exec][-format dcsh | dctcl][-overconstrain overcstr][-effort allocation_effort][-interblock_logic][-min_register_to_output minimum_budget][-min_input_to_output minimum_budget][-min_input_to_register minimum_budget][-no_environment][-generate_script_only][-remove]design

analyzeAnalyzes HDL files and stores the intermediateformat for the HDL description in the specifiedlibrary.

int analyze[-library library_name][-work library_name][-format vhdl | verilog][-create_update][-update][-define define_list][schedule]file_list

Synthesis Commands


annotate_activitySets (or resets) the toggle_rate and static_probabilityvalues for specified objects in the current design.

int annotate_activity[-static_probability sp_value][-toggle_rate tr_value][-clock clock_port_name][-period period_value][-hier][-reset][-select ports|regs|all][-objects object_list][-instances instance_list]

append (dctcl-mode only)


apropos (dctcl-mode only)

Search the command database for a pattern.

string apropos[-symbols_only]pattern

array (dctcl-mode only)


attach_regionAttaches cells to an existing region.

int attach_region[-name region_name]cell_list

auto_execok (dctcl-mode only)


auto_import (dctcl-mode only)


auto_load (dctcl-mode only)


auto_load_index (dctcl-mode only)



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auto_qualify (dctcl-mode only)


balance_bufferBuilds a balanced buffer tree on user-specified netsand drivers.

int balance_buffer[-verify][-verify_hierarchically][-verify_effort low | medium | high][-from start_point_list][-to end_point_list][-net net_list][-force][-library library_name][-prefer buffer | inverter | lib_cell_name]

balance_registersMoves the registers of a design to achieve a minimumcycle time.

int balance_registers [design_name]

bc_check_designPerforms a quick check of Behavioral Compilerscheduling information on the current design andreports incorrect coding styles.

int bc_check_design[-io_mode cycle_fixed | superstate_fixed][-constraints]

bc_dont_register_input_portFor Behavioral Compiler, disables automatic registerallocation for the specified input port.

int bc_dont_register_input_port port_name

Synthesis Commands


bc_dont_ungroupPrevents the compile command from ungrouping cellsgrouped by Behavioral Compiler, for the specifiedgroup classes or for all grouped cells in the currentdesign.

int bc_dont_ungroup[-register][-fsm][-random_logic][-prio_logic][-array_logic]

bc_group_processFor Behavioral Compiler, creates one level ofhierarchy instead of flattening each process afterscheduling.

int bc_group_process [-with_memory]

bc_marginSets the timing margin used by Behavioral Compiler.

int bc_margin[-process process_name][-global margin][-reg margin][-fsm margin ][-mux margin][-preferred_FF cell_name][-report_FF]

bc_report_arraysReports conflicting and non-conflicting accesses toarrays mapped to register files within an elaboratedbehavioral design.

int bc_report_arrays[-conflicting][-non_conflicting]


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bc_report_memoriesReports specific information about the memoriesinstantiated within an elaborated behavioral designand in the available synthetic libraries.

int bc_report_memories[-synthetic_libraries][-bindings][-used_memories][-conflicting][-non_conflicting]

bc_time_designCalculates timing and area estimates and annotatesthem on the current design for Behavioral Compilerand SystemC Compiler.

int bc_time_design[-force][-fastest][-cache_preserved_functions library_name[-except designs]][-use_cached_preserved_functionslibrary_name [-recompile designs]]

bc_viewInvokes BCView on the current design.

int bc_view[-output out_db_file][-project_file project_file_name][-dont_start][-cossap][-search_additional path_list][-host machine_name][-arch architecture_name]

binary (dctcl-mode only)


breakImmediately exits a loop structure.

int break

Synthesis Commands


calculate_rtl_loadCalculates RTL load values using layout-basedannotation.

int calculate_rtl_load-capacitance-delay pin_net_list

catch (dctcl-mode only)


cdChanges the current directory.

int cd [directory]

cell_ofReturns the cell objects for given pins in the currentdesign.

list cell_of [object_list]

chain_operationsSpecifies a list of operations to be scheduled byBehavioral Compiler for a specified process or for allprocesses.

int chain_operations[-process process_name] operation_names

change_linkChanges the design to which a cell is linked.

int change_linkobject_listdesign_name

change_namesChanges the names of ports, cells, and nets in adesign.

int change_names[-rules name_rules][-hierarchy][-verbose][-names_file names_file][-log_changes log_file_name]


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characterizeCaptures information about the environment ofspecific cell instances, and assigns the information asattributes on the design to which the cells are linked.

int characterizecell_list[-no_timing][-constraints][-connections][-power][-verbose]

check_bindingsChecks the bindings in a synthetic library moduledefinition.

int check_bindings[-bindings binding_list][-pin_widths pin_width_list]module_name

check_bsdChecks whether a design's boundary-scanimplementation is compliant with IEEE Std 1149.1.

int check_bsd[-verbose][-effort low | medium | high]

check_budgetChecks that user-specified budgets and fixed delaysare consistent with path constraints.

string check_budget[-verbose][-tolerance tolerance][-from object_list][-to object_list][-no_environment][-interblock_logic][cell_list]

Synthesis Commands


check_designChecks the current design for consistency.

int check_design[-summary][-no_warnings][-one_level][-post_layout | -only_post_layout]

check_dftChecks a design against the design rules of a scan testmethodology with test points that have been insertedby either Autofix or Shadow LogicDFT.

int check_dft[-verbose][-check_contention true | false |scan_shift_only | capture_only][-check_float true | false | scan_shift_only| capture_only]

check_errorPrints extended information on errors from lastcommand.

int check_error[-verbose][-reset]

check_implementationsChecks the implementations in a synthetic librarymodule definition.

int check_implementations[-implementations implementation_list][-parameters parameter_list]module_name

check_scanChecks a design against the design rules of a scan testmethodology.

int check_scan[-verbose][-check_contention true | false][-check_float true | false]


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check_synlibPerforms semantic checks on synthetic libraries.

int check_synlib

check_testChecks a design against the design rules of a scan testmethodology.

int check_test[-verbose][-check_contention true | false| scan_shift_only | capture_only][-check_float true | false| scan_shift_only | capture_only]

check_timingWarns about possible timing problems in the currentdesign.

int check_timing[-overlap_tolerance minimum_distance]

check_unmapped (dcsh-mode only)

Checks for any unmapped design below the currentdesign.

int check_unmapped

clean_buffer_treeRemoves the buffer tree at a given driver pin on amapped design.

int clean_buffer_tree[-from start_point_list |-to end_point_list | -net net_list][-hierarchy]

clock (dctcl-mode only)


close (dctcl-mode only)


Synthesis Commands


compare_collections (dctcl-mode only)

Compares the contents of two collections. If the sameobjects are in both collections, the result is 0 (likestring compare). If they are different, the result isnonzero. The order of the objects can optionally beconsidered.

int compare_collections[-order_dependent]collection1collection2

compare_designCompares two designs for functional equivalence.

int compare_design[-effort low | medium | high][-jtag][-fsm][-verbose][-hierarchical]design1 design2

compare_fsmCompares the sequential behavior of two finite statemachine designs.

int compare_fsmdesign1design2

compare_libPerforms a cross-reference check between atechnology library and a symbol library.

int compare_liblibrary1library2


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compilePerforms logic-level and gate-level synthesis andoptimization on the current design. Performslogic-level and gate-level synthesis and optimizationon the current design.

int compile[-no_map][-map_effort low | medium | high][-area_effort none | low | medium | high][-incremental_mapping][-exact_map][-verify][-verify_hierarchically][-verify_effort low | medium | high][-ungroup_all][-boundary_optimization][-auto_ungroup area | delay][-no_design_rule | -only_design_rule |-only_hold_time][-scan][-background run_name][-host machine_name][-arch architecture][-xterm][-top]

compile_partitions (dctcl-mode only)

Distributes compile jobs for a design. For use indc_shell-t (Tcl mode of dc_shell) only.

compile_partitions-destination pass

Synthesis Commands


compile_preserved_functionsCompiles and/or writes netlists for preservedfunctions.

int compile_preserved_functions[preserved_functions][-exclude preserved_functions][-no_compile][-compile_effort low | medium | high |1 | 2 | 3][-include_script script_name][-write][-filename filename][-design_library library_name][-force_recompile][-stages number_of_stages][-clock_port_name clock_port_name][-output_delay delay_value][-input_delay delay_value][-sync_reset reset_port_name][-async_reset reset_port_name][-reset_polarity high | low]

compile_systemcReads a SystemC source file, checks for compliancewith SystemC Compiler synthesis policy and syntax,and creates an internal database (.db) if there are noerrors.

int compile_systemc[-cpp cpp_program][-cpp_options options][-verbose][-preserve functions][-unroll loop_labels][-trace][-hls][-rtl][-rtl_format db | verilog][-output output_file][-single_file][-w/-library directory_name][-param module_spec_list][-dont_rename module_list]file_name


26


compile_ultraPerforms a two-pass, high-effort compile flow on thecurrent design for better QOR results.

int compile_ultra[-scan][-no_uniquify][-no_autoungroup]

concat (dctcl-mode only)


connect_netConnects a specified net to specified pins or ports.

int connect_netnetobject_list

context_checkEnables or disables the Syntax Checkercontext_check mode in which commands issued arechecked for context errors.

int context_check true | false

continueBegins the next loop iteration.

int continue

copy_collection (dctcl-mode only)

Duplicates the contents of a collection, resulting in anew collection. The base collection remainsunchanged.

collection copy_collection collection1

copy_designCopies a design to a new design, or copies a list ofdesigns to a new file in dc_shell memory.

int copy_designsource_design_nametarget_design_name

Synthesis Commands


create_bsd_patternsGenerates a set of functional patterns for aboundary-scan design.

int create_bsd_patterns[-output test_program_name][-effort low | medium | high][-type vector_type_list]

create_boundsCreates a fixed movebound or floating group bound inthe design.

int create_bounds[-name bound_name][-coordinate {llx1 lly1 urx1 ury1 ...}][-dimension {width height}][-effort low | medium | high | ultra][-type soft | hard]cell_list

create_busCreates a port bus or a net bus.

int create_busobject_listbus_name[-type type_name][-sort][-no_sort][-start start_bit][-end end_bit]

create_cachePopulates the cache directories with instances of therequested synthetic modules.

int create_cache-module module_list[-implementation implementation_list][-parameters parameter_list][-operating_condition operating_condition][-wire_load list][-report]


28


create_cellCreates cells in the current design.

int create_cellcell_list[reference_name][-logic logic_value][-only_physical]

create_clockCreates a clock object and defines its waveform in thecurrent design.

int create_clock[port_pin_list][-name clock_name][-period period_value][-waveform edge_list]

create_clusterCreates a cluster in the physical hierarchy of thedesign.

int create_cluster[-name cluster_name][-keep][-multibits][-parent parent_cluster_object]object_list

create_command_group (dctcl-mode only)

Creates a new command group.

string create_command_group group_name

create_designCreates a design in dc_shell memory.

int create_designdesign_name[file_name]

Synthesis Commands


create_generated_clockCreates a generated clock object.

string create_generated_clock[-name clock_name]-source master_pin[-divide_by divide_factor | -multiply_bymultiply_factor][-duty_cycle percent][-invert][-edges edge_list][-edge_shift edge_shift_list]port_pin_list

create_multibitCreates a multibit component for the specified list ofcells in the current design.

int create_multibitobject_list[-name multibit_name][-sort][-no_sort]

create_netCreates nets in the current design.

int create_net[-instance instance]net_list

create_operating_conditionsCreates a new set of operating conditions in a library.

int create_operating_conditions-name name-library library_name-process process_value-temperature temperature_value-voltage voltage_value[-tree_type tree_type][-calc_mode calc_mode][-rail_voltages rail_value_pairs]

create_pass_directories (dctcl-mode only)

Creates the directory structure required for storingACS data. For use in Tcl mode of dc_shell only.

int create_pass_directories pass_list


30


create_portCreates ports in the current design.

int create_portport_list[-direction dir]

create_schematicGenerates a schematic for the current design.

int create_schematic[-hierarchy][-size sheet_size][-portrait][-fill_percent fill_value][-outputs_attract][-order_outputs output_port_list][-sort_outputs][-dont_left_justify_inputs][-schematic_view][-symbol_view][-hier_view][-no_bus][-bit_mappers][-implicit][-no_rippers][-sge][-no_type_mappers][-reference][-gen_database]

create_test_clockDefines the timing of a clock applied to a designduring manufacturing test.

int create_test_clock port_list-waveform two_value_rise_fall_edge_list[-period period_value][-internal_clocks true | false | default]

create_test_patternsThis command is obsolete. Use the commandestimate_test_coverage for test coverage estimationand see the man page for syntax. To generate testvectors, use TetraMAX ATPG.

Synthesis Commands


create_test_scheduleDefine a series of test modes for the purpose of coretest scheduling.

int create_test_schedule

create_wire_loadCreates wire load models for the current design.

int create_wire_load[-design design_name][-cell cell_list][-cluster cluster_name][-hierarchy][-this_level_nets_only][-mode top | enclosed][-name model_name][-output file_name][-update_lib library_name][-write_script script_file_name][-dont_smooth][-trim trim_value][-percentile percentile_value][-total_area area][-statistics]

current_designSets the working design in dc_shell.

string current_design [design]

current_design_name (dctcl-mode only)


current_instanceSets the working instance object in dc_shell andenables other commands to be used on a specific cellin the design hierarchy.

string current_instance [instance]

current_test_modeSets or gets the working test mode for the currentdesign.

int current_test_mode [test_mode_label]


32


date (dctcl-mode only)

Returns a string containing the current date and time.

string date

dbatt (dctcl-mode only)


dbatt_db (dctcl-mode only)


dc_allocate_budgetsAllocates budgets to specified cells.

string dc_allocate_budgets[cell_list][-write_script][-file_format_spec format_spec][-format dcsh | dctcl][-separator hierarchy_separator][-mode rtl | gate | mixed][-positive_slack_only][-budget_design_ware][-levels budget_levels][-no_interblock_logic]

define_design_libMaps a design library to a UNIX directory.

int define_design_liblibrary_name-path directory

Synthesis Commands


define_name_rulesDefines a set of name rules for designs.

int define_name_rulesname_rules[-max_length length][-target_bus_naming_style bus_naming_style][-allowed allowed_chars][-restricted restricted_chars][-first_restricted first_chars][-last_restricted last_chars][-reserved_words reserves][-replacement_char char][-remove_chars][-equal_ports_nets][-inout_ports_equal_nets][-collapse_name_space][-case_insensitive][-special output_format][-prefix prefix_name][-map map_string][-type object_type][-reset]

define_proc_attributes (dctcl-mode only)

Defines attributes of a Tcl procedure, including aninformation string for help, a command group, a set ofargument descriptions for help, and so on. Thecommand returns the empty string.

string define_proc_attributesproc_name[-info info_text][-define_args arg_defs][-command_group group_name][-hide_body][-hidden][-dont_abbrev][-permanent]

define_test_modeDefine a test mode for the purpose of modelinference.

int define_test_modetest_mode_label[-type mode_purpose]string test_mode_labelstring mode_purpose


34


delete_test (dctcl-mode only)


derive_clocksCreates clock objects for network source pins or portsin the current design.

int derive_clocks

derive_constraintsPropagates design environment, constraints, andattribute settings from the top-level design to thespecified subdesigns.

int derive_constraints[-attributes_only][-verbose][-budget]cell_list

derive_timing_constraintsDerives timing requirements and places thatconstraint information on the current design.

int derive_timing_constraints[-fix_hold][-min_delay][-no_max_delay][-no_max_period][-max_delay_scale max_delay_scale_factor][-min_delay_scale min_delay_scale_factor][-period_scale max_period_scale_factor][-separate_rise_and_fall]

detach_regionDetaches cells from an existing region.

int detach_region[-name region_name]cell_list

disconnect_netDisconnects a net from pins or ports.

int disconnect_net net object_list -all

Synthesis Commands


dont_chain_operationsConstrains what operations are allowed to be chainedby Behavioral Compiler for a specified process or forall processes.

int dont_chain_operations[-process process_name][-into][-from] {operation_names}

drive_ofReturns the drive resistance value of the specifiedlibrary cell pin.

float drive_oflibrary_cell_pin[-rise | -fall][-wire_drive][-piece best | worst | average | int_value]

echoDisplays literal strings and values of variables andexpressions in dc_shell or in dc_shell-t.

dc_shell:

int echo[-n][text_string][variable][(expression)]

dc_shell-t:

int echo[-n][text_string][$variable][[expr expression]]


36


elaborateBuilds a design from the intermediate format of aVerilog module, a VHDL entity and architecture, or aVHDL configuration.

int elaboratedesign_name[-library library_name | -work library_name][-architecture arch_name][-parameters param_list][-file_parameters file_list][-update][-schedule][-gate_clock]

encoding (dctcl-mode only)


encrypt_libEncrypts a VHDL source library file.

int encrypt_libfile_name[-output encrypted_file]

eof (dctcl-mode only)


error (dctcl-mode only)


error_info (dctcl-mode only)

Prints extended information on errors from lastcommand.

string error_info

estimate_test_coverageGenerates test coverage statistics on the curent design.

int estimate_test_coverage[-sample percent]

eval (dctcl-mode only)


Synthesis Commands


exec (dctcl-mode only)


execute (dcsh-mode only)

Executes command arguments.

int execute[-s]command[arguments]

exitExits dc_shell.

int exit [exit_code_value]

expr (dctcl-mode only)


externalize_cellMakes a cell instance used by Behavioral Compilerexternal to the current design after scheduling.

int externalize_cell {cell_names}

extractExtracts a state-machine representation from a netlistor HDL description.

int extract[-minimize][-reachable]

extract_ilmTransforms the current design into interface logicmodel (ILM) and writes out the model to the specifiedoutput file in .db format. After command execution,the design in memory is the interface logic model.

int extract_ilm[-include_side_load side_load_type][-physical][-verbose]-output file_name

fblocked (dctcl-mode only)



38


fconfigure (dctcl-mode only)


fcopy (dctcl-mode only)


file (dctcl-mode only)


fileevent (dctcl-mode only)


filterReturns a list of design objects that satisfy aconditional attribute expression.

list filterobject_listexpression[-dont_check_real_objects]

filter_collection (dctcl-mode only)

Filters a collection, resulting in a new collection. Thebase collection remains unchanged.

collection filter_collectionbase_collectionexpression[-regexp][-nocase]

findFinds a design or library object.

list findtype[name_list][-hierarchy][-flat]

flush (dctcl-mode only)


for (dctcl-mode only)


Synthesis Commands


foreachSpecifies the control structure for list traversal loopexecution.

int foreach(variable_name, list_expression){loop_statement_block}

foreach_in_collection (dctcl-mode only)

Iterates over the elements of a collection.

string foreach_in_collectionitr_varcollectionsbody

format (dctcl-mode only)


get_attributeReturns the value of an attribute on a list of design orlibrary objects.

list get_attributeobject_listattribute_name[-bus][-quiet]

get_cells (dctcl-mode only)

Creates a collection of cells from the current designrelative to the current instance. You can assign thesecells to a variable or pass them into another command.For use in Tcl-based dc_shell only.

string get_cells[-hierarchical][-quiet][-regexp][-nocase][-exact][-filter expression]patterns | -of_objects objects


40


get_clocks (dctcl-mode only)

Creates a collection of clocks from the current design.You can assign these clocks to a variable or pass theminto another command. For use in Tcl-based dc_shellonly.

string get_clocks[-quiet][-regexp][-nocase][-filter expression]patterns

get_clusters (dctcl-mode only)

Creates a collection of one or more clusters loadedinto dc_shell. You can assign these clusters to avariable or pass them into another command. For usein Tcl-based dc_shell only.

string get_clusters[-hierarchical][-quiet][-regexp][-nocase][-exact][-filter expression][patterns]

get_design_lib_pathReturns the directory to which the specified library ismapped.

int get_design_lib_path library_name

get_design_parameterReturns the value of a parameter on a parameterizeddesign object. The parameter can be a generic inVHDL or a parameter in Verilog.

int get_design_parameterparameter_name[-quiet]

Synthesis Commands


get_designs (dctcl-mode only)

Creates a collection of one or more designs loadedinto dc_shell. You can assign these designs to avariable or pass them into another command. For usein Tcl-based dc_shell only.

string get_designs[-hierarchical][-quiet][-regexp][-nocase][-exact][-filter expression]patterns

get_generated_clocks (dctcl-mode only)

Creates a collection of generated clocks. For use inTcl mode of dc_shell only.

string get_generated_clocks[-quiet][-regexp][-nocase][-filter expression]patterns

get_ilm_objectsReturns a collection of nets, cells, or pins that are partof the interface logic for the current design.

collection get_ilm_objects[-type {net | pin | cell}]

get_lib_cells (dctcl-mode only)

Creates a collection of library cells from librariesloaded into dc_shell. You can assign these librarycells to a variable or pass them into another command.For use in Tcl-based dc_shell only.

string get_lib_cells[-filter expression][-quiet][-regexp][-nocase][-exact]patterns | -of_objectsobjects


42


get_lib_pins (dctcl-mode only)

Creates a collection of library cell pins from librariesloaded into dc_shell. You can assign these library cellpins to a variable or pass them into another command.For use in Tcl-based dc_shell only.

string get_lib_pins[-filter expression][-quiet][-regexp][-nocase][-exact]patterns | -of_objectsobjects

get_libs (dctcl-mode only)

Creates a collection of libraries loaded into dc_shell.You can assign these libraries to a variable or passthem into another command. For use in Tcl-baseddc_shell only.

string get_libs[-filter expression][-quiet][-regexp][-nocase][-exact]patterns | -of_objectsobjects

get_licenseObtains a license for a feature.

int get_license feature_list

get_message_info (dctcl-mode only)

Returns information about diagnostic messages.

string get_message_info[-error_count | -warning_count |-info_count]

Synthesis Commands


get_multibits (dctcl-mode only)

Creates a collection of one or more multibits loadedinto dc_shell. You can assign these multibits to avariable or pass them into another command. For usein Tcl-based dc_shell only.

string get_multibits[-hierarchical][-quiet][-regexp][-nocase][-exact][-filter expression][patterns]

get_nets (dctcl-mode only)

Creates a collection of nets from the current design.You can assign these nets to a variable or pass theminto another command. For use in Tcl-based dc_shellonly.

string get_nets[-hierarchical][-filter expression][-quiet][-regexp][-nocase][-exact]patterns | -of_objectsobjects

get_object_name (dctcl-mode only)

Returns the name of the object in a single-objectcollection. For use in Tcl-based dc_shell only.

string get_object_name collection


44


get_path_groups (dctcl-mode only)

Creates a collection of path groups from the currentdesign. You can assign these path groups to a variableor pass them into another command. For use in Tclmode of dc_shell only.

string get_path_groups[-quiet][-regexp][-nocase][-filter expression]patterns

get_pins (dctcl-mode only)

Creates a collection of pins from the curren design.You can assign these pins to a variable or pass theminto another command. For use in Tcl-based dc_shellonly.

string get_pins[-hierarchical][-filter expression][-quiet][-regexp][-nocase][-exact][-leaf]patterns | -of_objectsobjects

get_ports (dctcl-mode only)

Creates a collection of ports from the current design.You can assign these ports to a variable or pass theminto another command. For use in Tcl-based dc_shellonly.

string get_ports[-filter expression][-quiet][-regexp][-nocase][-exact]patterns | -of_objectsobjects

Synthesis Commands


get_references (dctcl-mode only)

Creates a collection of one or more references loadedinto dc_shell. You can assign these references to avariable or pass them into another command. For usein dc_shell -tcl mode only.

string get_references[-hierarchical][-quiet][-regexp][-nocase][-exact][-filter expression]patterns

get_timing_paths (dctcl-mode only)

Creates a collection of timing paths for customreporting and other processing. You can assign thesetiming paths to a variable or pass them into anothercommand.

string get_timing_paths[-to to_list][-from from_list][-through through_list][-delay_type delay_type][-nworst paths_per_endpoint][-max_paths max_path_count][-enable_preset_clear_arcs][-group group_name][-true][-true_threshold path_delay][-greater greater_limit][-lesser lesser_limit][-slack_greater_than greater_slack_limit][-slack_lesser_than lesser_slack_limit][-include_hierarchical_pins]

get_unix_variableReturns the value of a UNIX environment variable.

string get_unix_variable variable_name

getenv (dctcl-mode only)

Returns the value of a system environment variable.

string getenv variable_name


46


gets (dctcl-mode only)


glob (dctcl-mode only)


global (dctcl-mode only)


groupCreates a new level of hierarchy.

int group[cell_list | -logic | -pla | -fsm][-soft | -hdl_block block_name |-hdl_all_blocks | -hdl_bussed][-design_name design_name][-cell_name cell_name][-except exclude_list]

group_pathGroups a set of paths for cost function calculations.

int group_path[-weight weight_value][-critical_range range_value]-default | -name group_name[-from from_list][-to to_list][-through through_list]

group_variableAdds a variable to the specified variable group. Thiscommand is typically used by the systemadministrator only.

int group_variable group_name variable_name

Synthesis Commands


helpIn standard dc_shell (dcsh mode), the help commanddisplays man pages for Synopsys commands. InTcl-based dc_shell (dctcl mode), it displays quickhelp for one or more commands.

dc_shell:

int help [topic]

dc_shell-t:

string help[-verbose]pattern

highlight_pathHighlights timing paths in a schematic.

int highlight_path[pin_port_list][-from source_pins_or_ports][layer_name][-critical_path][-min][-max][-min_rise][-min_fall][-max_rise][-max_fall][-no_auto_cycle]

historyDisplays the history list (an ordered list of previouslyexecuted commands).

dc_shell:

int history[-h][-r][n]

dc_shell-t:

string history[-h][-r][n][keep m][advanced_args]


48


identify_interface_logicSets the is_interface_logic attribute on cells, nets andpins of the current design that are part of its interfacelogic.

int identify_interface_logic[-ignore_ports port_list][-latch_level levels]

ifConditional execution control structure.

dc_shell:

if ( expression ) {then-statement-block}

dc_shell-t:

if { expression } {then-statement-block}

ignore_array_loop_precedencesRemoves loop-carried dependencies between arrayaccesses for the Behavioral Compiler product.

int ignore_array_loop_precedences[-process process_name]operations

ignore_array_precedencesRemoves dependency-related constraints betweenarray accesses for the Behavioral Compiler product.

int ignore_array_precedences[-process process_name]-from_set from_operations-to_set to_operations

ignore_memory_loop_precedencesRemoves loop carried dependencies between memoryaccesses for the Behavioral Compiler product.

int ignore_memory_loop_precedences[-process process_name]operations

Synthesis Commands


ignore_memory_precedencesRemoves dependency related constraints betweenmemory accesses for the Behavioral Compilerproduct.

int ignore_memory_precedences[-process process_name]-from set from_operations-to set to_operations

include (dcsh-mode only)

Executes a script of dc_shell commands. For use instandard dc_shell (dcsh mode) only.

int includefile_name[-quiet]

incr (dctcl-mode only)


index_collection (dctcl-mode only)

Given a collection and an index into it, if the index isin range, extracts the object at that index and creates anew collection containing only that object. The basecollection remains unchanged.

collection index_collectioncollection1index

info (dctcl-mode only)


insert_bsdCreates ANSI/IEEE Std 1149.1-compliant boundaryscan circuitry using DesignWare macro cells.

int insert_bsd

insert_clock_gatingPerforms clock gating on an appropriately-preparedGTECH netlist.

int insert_clock_gating -mc


50


insert_dftAdds test points and scan chains to the current design.

int insert_dft[-dont_fix_constraint_violations][-map_effort low | medium | high][-ignore_compile_design_rules][-no_scan][-background run_name][-host machine_name][-arch architecture][-xterm][-physical]

insert_jtag (dctcl-mode only)


insert_padsInserts I/O pads in a design.

int insert_pads[-verify][-verify_hierarchically][-verify_effort low | medium | high][-thru_hierarchy][-respect_hierarchy][design_list]

insert_scanAdds scan circuitry to the current design.

int insert_scan[-dont_fix_constraint_violations][-map_effort low | medium | high][-ignore_compile_design_rules][-physical][-background run_name][-host machine_name][-arch architecture][-xterm]

interp (dctcl-mode only)


Synthesis Commands


is_false (dctcl-mode only)

Tests the value of a specified variable, and returns a 1if the value is 0 or the case-insensitive string is false;returns a 0 if the value is 1 or the case-insensitivestring is true. For use in Tcl-based dc_shell only.

int is_false value

is_true (dctcl-mode only)

Tests the value of a specified variable, and returns a 1if the value is 1 or the case-insensitive string is true;returns a 0 if the value is 0 or the case-insensitivestring is false. For use in Tcl-based dc_shell only.

int is_true value

join (dctcl-mode only)


lappend (dctcl-mode only)


lib2saifCreates a SAIF forward-annotation file from aspecified library file or from a list of library files.

int lib2saif[-output file_name][-lib_pathname lib_path_name]library_file_name

library_analysis (dctcl-mode only)


license_usersLists the current users of the Synopsys licensedfeatures.

license_users [feature_list]

lindex (dctcl-mode only)



52


linkResolves design references.

int link

linsert (dctcl-mode only)


listIn standard dc_shell (dcsh mode), lists informationabout the commands, variables, and licenses currentlyin Design Analyzer or standard dc_shell (dcsh mode).In Tcl-based dc_shell, it creates a list.

dc_shell:

int list {-commands | -variablesvariable_group | variable_name | -licenses |-files}

dc_shell-t:

list ? arg1 arg2 arg arg ... ?

list_attributes (dctcl-mode only)

Lists currently defined attributes. For use in dc_shell-t(Tcl mode of dc_shell) only.

string list_attributes[-application][-class class_name]

list_designsList the designs available in dc_shell.

int list_designs[design_list][-show_file]

list_files (dctcl-mode only)

Lists the files that are loaded into dc_shell. For use inTcl-based dc_shell only.

int list_files

Synthesis Commands


list_instancesLists the instances in dc_shell.

int list_instances[instance_list][-hierarchy][-max_levels num_levels][-full]

list_libsLists the available libraries in dc_shell or psyn_shell.

int list_libs [lib_list]

list_licenses (dctcl-mode only)

Displays a list of licenses currently checked out by theuser. For use in dc_shell -tcl_mode only.

string list_licenses

list_test_modelsList the designs with test models available in dc_shell.

int list_test_models

list_test_modesDisplays all the test modes defined for the currentdesign.

int list_test_modes

llength (dctcl-mode only)


lminus (dctcl-mode only)

Removes one or more named elements from a list andreturns a new list.

list lminusthe_listelements

load_ofReturns the capacitance of the specified library cellpin.

float load_of library_cell_pin


54


lrange (dctcl-mode only)


lreplace (dctcl-mode only)


ls (dctcl-mode only)

Lists the contents of a directory.

int ls [filename ...]

lsearch (dctcl-mode only)


lsort (dctcl-mode only)


man (dctcl-mode only)

Displays reference manual pages.

string man topic

merge_saifReads a list of SAIF files with their correspondingweights, annotates switching activity attributes withmerged toggle_rate and merged static_probability fornets, pins, and ports in the current design, andgenerates a merged output SAIF file.

int merge_saif-input_list saif_file_and_weight_list-instance_name inst_name[-output merged_saif_name][-simple_merge][-ignore ignore_name][-ignore_absolute ig_absolute_name][-exclude exclude_file_name][-exclude_absolute ex_absolute_file_name][-unit_base unit_value][-scale scale_value][-khrate khrate_value]

minimize_fsmPerforms state minimization on a state table design.

int minimize_fsm

Synthesis Commands


namespace (dctcl-mode only)


open (dctcl-mode only)


optimize_bsdOptimizes ANSI/IEEE Std 1149.1-compliantboundary-scan circuitry synthesized by the insert_bsdcommand using DesignWare macro cells.

int optimize_bsd

optimize_registersPerforms (register) retiming on a mapped gate-levelnetlist; determines the placement of registers in adesign to achieve a target clock period; and minimizesthe number of registers while maintaining that clockperiod.

int optimize_registers[design_name][-period period_value][-no_clock_correction][-minimum_period_only][-flatten][-no_incremental_map][-no_compile][-sync_transform multiclass | decompose |dont_retime][-async_transform multiclass | decompose |dont_retime][-sync_state preserve | dont_care][-async_state preserve | dont_care][-check_design [-verbose]][-print_critical_loop]

package (dctcl-mode only)


parent_clusterReturns the name of the parent cluster of the passedcluster.

string parent_cluster cluster_object


56


parse_proc_arguments (dctcl-mode only)

Parses the arguments passed into a Tcl procedure.

string parse_proc_arguments-args arg_listresult_array

partition_dpTransforms arithmetic operators (for example,addition, subtraction, and multiplication) intodatapath blocks to be implemented by a datapathgenerator for the specified design or for the currentdesign.

int partition_dp[design_name][-duplicate][-dont_split]

pid (dctcl-mode only)


pipeline_designPipelines combinational designs by adding registers atthe outputs and retiming the circuit.

int pipeline_designdesign_name[-period period_value][-flatten][-stages number_of_stages ][-stall_ports port_list][-stall_polarity high | low][-sync_reset reset_port |-async_reset reset_port][-reset_polarity high | low][-clock_port_name clock_port][-no_incremental_map][no_compile][-check_design [-verbose]][-print_critical_loop][-no_clock_correction][-minimum_period_only][-register_outputs]

Synthesis Commands


pipeline_loopSpecifies the name of a loop for Behavioral Compilerto pipeline.

int pipeline_looploop_name-initiation_interval interval_time-latency latency_time

plotPlots the schematic or symbol view for the currentdesign using PostScript format.

int plot[-hierarchy][-sheet_list sheet_number_list][-output file_name][-symbol_view][-schematic_view]

prescheduleDirects Behavioral Compiler to schedule an operationor operations in a specific cycle for a specified processor for all processes.

int preschedule[-process process_name]{operation_names}cycle

preview_bsdPreviews the boundary-scan design.

int preview_bsd[-show cells | data_registers | instructions| tap | all ][-script]


58


preview_dftPreviews, but does not implement, the test points andscan chains to be added to the current design, basedon the current set of scan and test point specifications.

int preview_dft[-verbose][-script][-show bidirectionals | cells | scan |scan_clocks | scan_signals | segments |tristates | all][-test_points all][-no_scan][-physical]

preview_scanPreviews the scan design.

int preview_scan[-command insert_scan | reoptimize_design][-script][-physical][-show bidirectionals | cells | scan |scan_clocks | scan_signals | segments |tristates | all]

print_suppressed_messages (dctcl-mode only)

Displays an alphabetical list of message ids that arecurrently suppressed.

string print_suppressed_message

print_variable_group (dctcl-mode only)

Lists the variables defined in a specified variablegroup, along with their current values. For use inTcl-based dc_shell only.

int print_variable_group variable_group

printenv (dctcl-mode only)

Prints the value of environment variables.

string printenv [variable_name]

Synthesis Commands


printvar (dctcl-mode only)

Prints the values of one or more variables.

string printvar[pattern][-user_defined][-application]

proc (dctcl-mode only)


proc_args (dctcl-mode only)

Displays the formal parameters of a procedure.

string proc_args proc_name

proc_body (dctcl-mode only)

Displays the body of a procedure.

string proc_body proc_name

propagate_annotated_delay_upPropagates annotated delay information for thespecified list of hierarchical cells from their respectivereference designs to the current design. If no cell listis specified, the default list is the set of InterfaceLogic Model (ILM) sub-designs in the current design.

int propagate_annotated_delay_up

propagate_constraintsPropagates timing constraints from lower levels of thedesign hierarchy to the current design.

int propagate_constraints[-design design_list]

propagate_placement_upPropagates placement information for all leaf cells inthe specified list of hierarchical cells from theirrespective reference designs to the current design. Ifno cell list is specified, the default list is the set ofInterface Logic Model (ILM) sub-designs in thecurrent design.

int propagate_placement_up


60


puts (dctcl-mode only)


pwdDisplays the pathname of the present workingdirectory (pwd), also called the current directory.

int pwd

query_objects (dctcl-mode only)

Searches for and displays objects in the database. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

string query_objects[-verbose][-class class_name][-truncate elem_count]object_spec

quitExits dc_shell.

int quit

Synthesis Commands


readIn standard dc_shell (dcsh mode), reads designs intomemory in Synopsys internal database (.db) format.In Tcl-based dc_shell (dctcl mode), reads from achannel. In lc_shell, reads libraries into memory inSynopsys internal database (.db) format.

dcsh:

list read[-library library_name][-work library_name][-define macro_names][-format input_format][-single_file file_name][-names_file name_mapping_files][-define define_list]file_list

dctcl:

read ?-nonewline? channelIdread channelId numBytes

lc_shell:

list read file_list

read_bsd_init_protocolReads a boundary-scan initialization protocol file.

int read_bsd_init_protocol[init_protocol_file]

read_bsd_protocolReads a custom boundary-scan protocol file.

int read_bsd_protocol [protocol_file]

read_clustersAnnotates a design with physical cluster hierarchydata from a file in Physical Design Exchange Format(PDEF).

int read_clusters[-design design_name]cluster_file_name


62


read_db (dctcl-mode only)

Reads in one or more design or library files inSynopsys database (.db) format.

string read_db file_names

read_edif (dctcl-mode only)

Reads in one or more design or library files in EDIFformat.

string read_edif file_names

read_fileReads designs or libraries into dc_shell, or readslibraries into lc_shell.

dc_shell:

list read_file[-library library_name][-work library_name][-define macro_names][-format input_format][-netlist | -rtl][-single_file file_name][-names_file name_mapping_files]file_list

lc_shell:

list read_file file_list

read_init_protocolReads an initialization protocol file.

int read_init_protocol[init_protocol_file][-format tpf | stil]

read_libReads a technology library, physical library, orsymbol library into dc_shell or lc_shell. Creates aphysical library for gdsii.

int read_lib[-format format_name][-symbol intermediate_symbol_library_file][-plibrary physical_library_output_file][-pplibrary pseudo_physical_file_name]

Synthesis Commands


read_parasiticsReads net parasitics information from an SPEF file,and uses it to annotate the current design.

string read_parasitics-elmore[-increment][-pin_cap_included][-net_cap_only][-complete_with zero | wlm][-syntax_only][-path path_name][-strip_path path_name][-quiet] file_names

read_partition (dctcl-mode only)

Reads the database for a design. For use only indc_shell-t (Tcl mode of dc_shell).

int read_partition-source pass-type pre | postdesign_name

read_pin_mapReads in a port-to-pin mapping file, which defines thedesign port-to-package pin mapping for aboundary-scan design.

int read_pin_map path_name

read_preserved_function_netlistReads an external precompiled netlist for a preservedfunction.

int read_preserved_function_netlist[preserved_functions][-exclude preserved_functions][-design_library library_name][-force_reload][-filename filename][-return_port return_port_name][-clock_port_name clock_port_name][-clock_edge positive | negative][-sync_reset reset_port_name][-async_reset reset_port_name][-reset_polarity high | low]


64


read_saifReads a SAIF file and annotates the switching activityattributes toggle_rate and static_probability for nets,pins, and ports in the current design.

int read_saif -input file_name-instance_name name[-ignore ignore_name][-ignore_absolute ig_absolute_name][-exclude exclude_file_name][-exclude_absolute ex_absolute_file_name][-names_file name_changes_log_file][-unit_base unit_value][-scale scale_value][-khrate khrate_value][-rtl_direct][-verbose]

read_sdc (dctcl-mode only)

Reads in a script in Synopsys Design Constraints(SDC) format.

int read_sdcfile_name[-echo][-syntax_only][-version sdc_version]

read_sdfReads leaf cell and net timing information from a filein Standard Delay Format (SDF) and uses thatinformation to annotate the current design.

string read_sdf[-load_delay net | cell][-path path_name][-min_type sdf_min | sdf_typ | sdf_max][-max_type sdf_min | sdf_typ | sdf_max][-worst]sdf_file_name

read_test_modelReads a test model file.

list read_test_model[-format ctl | db][-design design_name]model_files

Synthesis Commands


read_test_protocolReads a custom test protocol file.

int read_test_protocol[protocol_file][-format tpf | stil]

read_toggleReads a TOGGLE file and annotates the switchingactivity attributes toggle_rate and static_probabilityonto nets, pins, and ports in the database file of thecurrent design.

int read_toggle-input file_name-instance_name name[-unit_base unit_value][-scale scale_value][-khrate khrate_value][-names_file change_name_log_file][-case_insensitive][-output saif_file_name]

read_verilog (dctcl-mode only)

Reads in one or more design or library files in Verilogformat.

string read_verilog[-netlist | -rtl]file_names

read_vhdl (dctcl-mode only)

Reads in one or more design or library files in VHDLformat.

string read_vhdl file_names

redirect (dctcl-mode only)

Redirects the output of a command to a file.

string redirect[-append]file_name{command}


66


reduce_fsmReduces the logic for each state transition in a statetable design.

int reduce_fsm

reg_global_var (dctcl-mode only)


regexp (dctcl-mode only)


regsub (dctcl-mode only)


remove_analysis_infoRemoves BCView analysis information from thespecified design.

int remove_analysis_info [design]

remove_annotated_checkRemoves annotated timing check information.

int remove_annotated_check-all | -from from_list | -to to_list[-rise | -fall][-clock rise | fall][-setup][-hold][-recovery][-removal][-nochange_low][-nochange_high]

remove_annotated_delayRemoves the annotated delay between two pins.

int remove_annotated_delay-all | -cell_all | -net_all | -fromfrom_list | -to to_list

remove_annotated_transitionRemoves the annotated transition at a pin.

int remove_annotated_transition-all | -at pin_list

Synthesis Commands


remove_attributeRemoves an attribute from a design or library object.

list remove_attributeobject_listattribute_name[-bus][-quiet]

remove_bsd_instructionRemoves boundary-scan instructions from theinstruction list to be used by insert_bsd for the currentdesign.

int remove_bsd_instruction instruction_list

remove_bsd_portRemoves from specified ports the attributes thatidentify those ports as IEEE Std 1149.1 test accessports (TAPs) in the current design.

int remove_bsd_port port_list

remove_bsd_signalRemoves boundary-scan signal types from specifiedports in the current design.

int remove_bsd_signal port_list

remove_bsd_specificationRemoves the IEEE 1149.1 specifications from aboundary-scan design.

int remove_bsd_specification[-all][-configuration][-compliance all|pattern_name][-intest][-runbist][-data_cell port_name][-control_cell hierarchical_cell_name][-path][-tap_element design_name][-bsr_element design_name][-linkage_port][-register][-instruction instruction_list]


68


remove_bsr_cell_typeRemoves the boundary-scan cell type specificationfrom a set of design ports.

int remove_bsr_cell_type port_list

remove_busRemoves a port bus or net bus.

int remove_bus object_list

remove_cacheSelectively removes elements from the syntheticlibrary cache directories.

int remove_cache[-design_lib list][-module list][-implementation list][-parameters parameter_list][-tech_lib list][-wire_load list][operating_conditions list][-directory dir_list][-smaller size | -larger size][-netlist_only | -model_only][-accessed_since days |-accessed_beyond days]

remove_case_analysisRemoves the case analysis value from specified inputports or pins.

string remove_case_analysisport_or_pin_list | -all

remove_cellRemoves cells from the current design.

int remove_cell cell_list | -all

remove_cell_degradationRemoves the cell_degradation attribute on specifiedports or designs.

int remove_cell_degradation object_list

Synthesis Commands


remove_clockRemoves clocks from the current design.

int remove_clock clock_list | -all

remove_clock_gatingDirects the compile -incremental, physopt, andphysopt -incremental commands to remove clockgating from registers clock-gated by Power Compiler.

int remove_clock_gating[-gating_cells clock_gating_cells_list][-gated_registers gated_register_list][-all][-hier][-verbose][-undo]

remove_clock_gating_checkRemoves setup and hold checks from the specifiedclock gating cells.

int remove_clock_gating_check[-setup][-hold][-rise][-fall]object_list

remove_clock_latencyRemoves clock latency information from the specifiedobjects.

string remove_clock_latency[-fall][-min][-max][-source][-early][-late]object_list

remove_clock_transitionRemoves clock transition attributes on the specifiedclock objects.

int remove_clock_transition clock_list


70


remove_clock_uncertaintyRemoves clock uncertainty information.

string remove_clock_uncertaintyobject_list[-from from_clock][-to to_clock][-rise][-fall][-setup][-hold]

remove_clustersRemoves the physical cluster hierarchy associatedwith a design.

int remove_clusters [designs_or_clusters]

remove_constraintRemoves all constraint attributes, clocks, and pathdelay information from the current design.

int remove_constraint -all

remove_designRemoves a list of designs or libraries from dc_shellmemory.

int remove_design[design_list | -designs | -all][-hierarchy][-quiet]

remove_dft_configurationRemoves the current DFT configuration from thecurrent design.

int remove_dft_configuration

remove_dft_signal (dctcl-mode only)


Synthesis Commands


remove_disable_clock_gating_checkFor specified cells and pins, restores clock gatingchecks previously disabled by theset_disable_clock_gating_check command.

string remove_disable_clock_gating_checkobject_list

remove_driving_cellRemoves driving cell attributes from the specifiedinput or inout ports of the current design.

int remove_driving_cell [port_list]

remove_from_collection (dctcl-mode only)

Removes objects from a collection, resulting in a newcollection. The base collection remains unchanged.

collection remove_from_collectionbase_collection

remove_generated_clockRemoves a generated_clock object.

string remove_generated_clock-all | clock_list

remove_highlightingRemoves highlighting from schematics of the currentinstance or the current design.

int remove_highlighting [-all | -hier]

remove_ideal_latencyRemoves user-specified ideal latency informationfrom specified objects.

string remove_ideal_latency[-rise | -fall][-min][-max]object_list

remove_ideal_netRemoves the ideal_net at -tribute from the specifiednets in the current design.

int remove_ideal_net net_list


72


remove_ideal_networkRemoves a set of ports or pins in an ideal network inthe current design. Cells and nets in the transitivefanout of the specified objects are no longer treated asideal.

int remove_ideal_network object_list

remove_ideal_transitionRemoves ideal transition information from thespecified objects.

string remove_ideal_transition[-rise | -fall][-min][-max]object_list

remove_input_delayRemoves input delay on pins or input ports.

int remove_input_delay[-clock clock][-clock_fall][-level_sensitive]][-rise][-fall][-max][-min]port_pin_list

remove_isolate_portsRemoves the specified ports from the list of ports thatare isolated in the current design.

int remove_isolate_ports port_list

remove_licenseRemoves a licensed feature.

int remove_license feature_list

remove_multibitRemoves multibit components in the current design,or detaches cells in the current design from themultibit components that contain them.

int remove_multibit object_list

Synthesis Commands


remove_netRemoves nets from the current design.

int remove_netnet_list | -all[-only_physical]

remove_operand_isolationRemoves the isolation logic that Power Compilerinserted in the circuit during operand isolation.

int remove_operand_isolation[-from from_list][-to to_list]

remove_output_delayRemoves output delay on pins or output ports.

int remove_output_delay[-clock clock[-clock_fall][-level_sensitive]][-rise][-fall][-max][-min]port_pin_list

remove_padsRemoves I/O pads from a design.

int remove_pads[-verify][-verify_effort effort][design_list]

remove_pass_directories (dctcl-mode only)

Removes the data directories associated with thespecified passes. For use only in dc_shell-t (Tcl modeof dc_shell).

int remove_pass_directories pass_list

remove_pin_mapRemoves a design port-to-package pin mapping for aboundary-scan design.

int remove_pin_map package_name


74


remove_portRemoves ports from the current design.

int remove_port port_list | -all

remove_port_configurationRemoves the Shadow LogicDFT port configurationfrom the specified port on the specified list ofelements, so that insert_dft inserts the default testpoint circuitry.

int remove_port_configuration-cell cell_design_ref_list-port port_name

remove_propagated_clockRemoves a propagated clock specification.

string remove_propagated_clock object_list

remove_rtl_loadRemoves previously-set capacitance and resistanceRTL load values from pins, ports, and nets.

int remove_rtl_load -all | pin_net_list

remove_scan_register_typeRemoves existing scan register types, previously setby set_scan_register_type, from specified cells orfrom the current design.

int remove_scan_register_type[cell_or_design_list]

remove_scan_specificationRemoves scan specifications from the current design.

int remove_scan_specification[-all][-bidirectionals][-chain chain_name_list][-configuration][-link link_name_list][-segment segment_name_list][-signal port_name_list][-tristates]

Synthesis Commands


remove_scheduling_constraintsRemoves explicit Behavioral Compiler schedulingconstraints from the specified process or from allprocesses.

int remove_scheduling_constraints[-process process_name]

remove_test_modeRemove the mode declared by the define_test_modecommand.

int remove_test_mode design_name

remove_test_modelPermanently removes the test model associated with adesign.

int remove_test_model [-design design_name]

remove_unconnected_portsRemoves unconnected ports or pins from cells,references, and subdesigns.

int remove_unconnected_portscell_list[-blast_buses]

remove_variable (dcsh-mode only)

Removes a variable from dc_shell.

int remove_variable variable_name

remove_wire_load_min_block_sizeRemoves the wire_load_min_block_size attributefrom the current design.

int remove_wire_load_min_block_size


76


remove_wire_load_modelRemoves wire load model attributes from designs,ports, hierarchical cells, or the specified cluster of thecurrent design.

int remove_wire_load_model[-min][-max][-cluster cluster_name][object_list]

remove_wire_load_selection_groupRemoves wire load model selection group fromdesigns and cells, or from a specified cluster of thecurrent design.

int remove_wire_load_selection_group[-min][-max][-cluster cluster_name][object_list]

remove_wrapper_elementRemoves the wrapper_element attribute from a list ofelements.

int remove_wrapper_elementcell_design_ref_list

rename (dctcl-mode only)

Rename or delete a user-defined procedure.

string renameoldNamenewName

rename_designRenames a design in dc_shell, or moves a list ofdesigns to a file.

int rename_designdesign_name1design_name2

Synthesis Commands


reoptimize_designIncrementally optimizes a design usinglayout/floorplanning information.

int reoptimize_design[-map_effort low | medium | high][-sizing][-pin_swap][-buffer_insertion][-buffer_removal][-cpr][-tolerance_to_change low | medium | high][-ignore_footprint][-ignore_cell_area][-no_design_rule | -only_design_rule][-only_hold_time][-area_recovery]

replace_fpga (dctcl-mode only)


replace_syntheticImplements all synthetic library parts of a designusing generic logic.

int replace_synthetic [-ungroup]

report_annotated_checkDisplays all annotated timing checks on the currentdesign.

int report_annotated_check [-nosplit]

report_annotated_delayDisplays all annotated delays on cells and nets of thecurrent design.

int report_annotated_delay[-cell][-net][-min][-nosplit]

report_annotated_transitionDisplays annotated transitions on all pins of thecurrent design.

int report_annotated_transition


78


report_areaDisplays area information and statistics for the designof the current instance, if set; or for the current designotherwise.If the design is an Interface Logic Model(ILM), the report also displays area information andstatistics of the original design for which the ILM wascreated.

int report_area[-nosplit][-physical]

report_attributeDisplays attributes and their values associated with acell, net, pin, port, instance, or design.

int report_attribute[object_list] | [-net][-cell][-design][-hierarchy][-instance][-pin][-port][-reference][-nosplit]

report_auto_ungroupDisplays information about the cell hierarchies thathave been ungrouped with compile -auto_ungrouparea | delay.

int report_auto_ungroup[-nosplit][-full]

report_buffer_treeDisplays the buffer tree and its level information atthe given driver pin.

int report_buffer_tree[-from start_point_list | -net net_list][-depth max_depth][-connections][-hierarchy][-physical][-nosplit]

Synthesis Commands


report_busLists the bused ports and nets in the current instance,if set; or in the current design otherwise.

int report_bus [-nosplit]

report_cacheReports on the contents of synthetic library caches.

int report_cache[-design_lib list][-module list][-implementation list][-parameters parameter_list][-tech_lib list][-wire_load list][-operating_conditions list][-directory dir_list][-smaller size | -larger size][-accessed_since days | -accessed_beyonddays][-netlist_only | -model_only][-sort_largest | -sort_oldest |-sort_cache_key][-statistics]

report_case_analysisReports case analysis on ports or pins.

string report_case_analysis[-all][-nosplit]

report_cellDisplays information about cells in the currentinstance, if set; or in the current design otherwise.

int report_cell[-nosplit][-connections [-verbose]][-physical [-verbose]][-only_physical][cell_list]


80


report_clockDisplays clock-related information on the currentdesign.

int report_clock[-attributes][-skew][-nosplit]

report_clock_gatingReports information about clock gating performed byPower Compiler.

report_clock_gating[-hier][-verbose][-gated][-ungated][-gating_elements][-only cell_list][-nosplit][-physical]

report_clock_gating_checkPrints a report of the clock gating checks.

string report_clock_gating_check[-nosplit][-type user | power | all][instance_list]

report_clustersReports on the physical cluster hierarchy associatedwith the current design.

int report_clusters[-cluster cluster_name][-leaf][-nosplit]

report_compile_optionsDisplays information about the compile options forthe design of the current instance, if set; or for thecurrent design otherwise.

int report_compile_options[-nosplit]

Synthesis Commands


report_constraintDisplays constraint-related information about adesign.

int report_constraint[-all_violators][-verbose][-significant_digits digits][-max_area][-max_delay][-critical_range][-min_delay][-max_capacitance][-min_capacitance][-max_transition][-max_fanout][-cell_degradation][-min_porosity][-max_dynamic_power][-max_leakage_power][-connection_class][-multiport_net][-nosplit]

report_delay_calculationDisplays the actual calculation of a timing arc delayvalue for a cell or net.

int report_delay_calculation-min-max-from from_pin-to to_pin[-nosplit]

report_designDisplays attributes of the current design.

int report_design[-nosplit][-physical[-verbose]


82


report_design_libLists the design units contained in the specifiedlibraries.

int report_design_lib[-libraries][-designs][-architectures][-packages][library_list]

report_direct_power_rail_tieReports all the library pins on which the attributedirect_power_rail_tie is set to true.

int report_direct_power_rail_tie

report_disable_timingReports disabled timing arcs in the current design.

string report_disable_timing [-nosplit]

report_fpga (dctcl-mode only)


report_fsmDisplays state-machine attributes and information forthe design of the current instance, if set; or for thecurrent design otherwise.

int report_fsm [-nosplit]

report_hierarchyDisplays the reference hierarchy of the currentinstance, if set; or of the current design otherwise.

int report_hierarchy[-nosplit][-full]

Synthesis Commands


report_ideal_networkDisplays information about ports, pins, nets, and cellson ideal networks in the current design.

int report_ideal_network[-net][-cell][-load_pin][-timing][object_list]

report_internal_loadsDisplays internal loads on the nets in the currentdesign.

int report_internal_loads [-nosplit]

report_isolate_portsDisplays the status of port isolation on ports on whichisolation was requested.

int report_isolate_ports [-nosplit]

report_libDisplays information about technology or symbollibraries.

int report_liblibrary_name[-timing_arcs][-timing][-power][-em][-vhdl_name][-table][-full_table][-timing_label][-power_label][-routing_rule][-rwm][-fpga][-all][cell_list]


84


report_modePrints a report of the instance modes.

string report_mode[-nosplit][instance_list]

report_multibitDisplays information about multibit components inthe current design.

int report_multibit[-nosplit][object_list]

report_multicyclesReports on scheduled multicycle operations forBehavioral Compiler.

int report_multicycles[-process process_name]

report_name_rulesReports the values of name rules.

int report_name_rules [name_rules]

report_namesReports potential name changes of ports, cells, andnets in a design.

int report_names[-rules name_rules][-hierarchy][-original][-nosplit]

Synthesis Commands


report_netDisplays net information for the design of the currentinstance, if set; or for the current design otherwise.

int report_net[-nosplit][-noflat][-transition_times][-only_physical [-verbose]][-cell_degradation][-min][-connections [-verbose]][-physical [-verbose]][net_list][-max_toggle_rate]

report_net_fanoutDisplays net fanout or buffer tree information for thedesign of the current instance, if set; or for the currentdesign otherwise.

int report_net_fanout[-nosplit][-high_fanout][-threshold lower][-bound upper][-verbose][-connections][-physical][-min][-tree [-depth level]][net_list]

report_operand_isolationReports the status of operand isolation cells in thecurrent design.

int report_operand_isolation

report_packagesDisplays the package names for all the port-to-pinmapping files that are read in for a boundary-scandesign.

int report_packages


86


report_partitions (dctcl-mode only)

Lists the hierarchical designs and their associatedattributes and relative size (estimated in RTL). For usein dc_shell-t (Tcl mode of dc_shell) only.

int report_partitions [-nosplit]

report_pass_data (dctcl-mode only)

Reports the data files that are available for a designcreated by Automated Chip Synthesis. For use indc_shell-t (Tcl mode of dc_shell) only.

int report_pass_data[-hierarchy][-pass_list pass_list][design]

report_path_budgetDisplays budgeting information about a design. Thedelay number shown for each block/cell shows theamount of budget allocated for that block/cell in thepath. The overall budget for the path is the sum ofthese budgets (delays).

int report_path_budget[-to to_list][-from from_list][-through through_list][-nworst paths_per_endpoint][-max_paths max_path_count][-input_pins][-nets][-transition_time][-capacitance][-significant_digits digits][-nosplit][-sort_by group | slack][-all][-verbose]

report_path_groupReports information about path groups in the currentdesign.

int report_path_group [-nosplit]

Synthesis Commands


report_portDisplays information about ports for the design of thecurrent instance, if set; or for the current designotherwise.

int report_port[-drive][-verbose][-physical][-nosplit][port_list]

report_powerCalculates and reports dynamic and static power for adesign or instance.

int report_power[-net][ -cell][-only cell_or_net_list][-hier][-hier_level level_value][-verbose][-cumulative][-flat][-exclude_boundary_nets][-analysis_effort low | medium | high][-nworst number][-sort_mode mode][-histogram [-exclude_leq le_val |-exclude_geq ge_val]][-nosplit]

report_referenceDisplays information about references in the currentinstance, if set; or in the current design otherwise.

int report_reference [-nosplit]

report_resource_estimatesDisplays timing and area estimates for BehavioralCompiler operations in the current design.

int report_resource_estimates


88


report_resourcesLists the resources and datapath blocks used in thedesign of the current instance, if set; or in the currentdesign otherwise.

int report_resources[-nosplit][-hierarchy]

report_routabilityDisplays information about the routability of thecurrent design.

int report_routability [-nosplit]

report_saifReports switching activity annotations for nets, pins,and ports of the current design or instance.

int report_saif[-flat][-type rtl | gate][-missing][-only cell_or_net_list]

report_scheduleDisplays the results of scheduling and allocation asperformed by Behavioral Compiler.

int report_schedule[-process process_name][-operations [-mask [r][w][l][L][o][p]][-start start_cycle][-finish end_cycle][-delimiter character]][-variables [-min min_width][-max max_width][-start start_cycle][-finish end_cycle][-delimiter character]][-summary][-abstract_fsm [-mask [r][w][o][s]]][-verbose_fsm [-mask [r][w][o][d][s]]]

Synthesis Commands


report_scheduling_constraintsDisplays Behavioral Compiler scheduling constraintson the current design for a specified process or for allprocesses.

int report_scheduling_constraints[-process process_name][-dont_chain][-chains][-antichains][-two_point][-preschedule][-pipeline]

report_synlibDisplays information about synthetic libraries.

int report_synlib library [module_list]

report_testDisplays test-related information about the currentdesign.

int report_test[-assertions][-bsd][-bsd_configuration][-configuration][-constraints][-dft][-inst design_instance_list][-inst design_instance_list]][-methodology][-port][-scan_path][-state][-trace_nets][-nosplit]

report_test_modeDisplays the test mode information attached to amodel.

int report_test_mode[-design design_name][-all][-verbose][test modes]


90


report_test_modelDisplays the test model information attached to adesign.

int report_test_model [-design design_name]

report_timingDisplays timing information about a design.

int report_timing[-to to_list][-from from_list][-through through_list][-path short | full | full_clock | only |end][-delay min | min_rise | min_fall | max |max_rise | max_fall][-nworst paths_per_endpoint][-max_paths max_path_count][-input_pins][-nets][-transition_time][-capacitance][-attributes][-locations][-physical][-lesser_path max_path_delay][-greater_path min_path_delay][-loops][-true [-true_threshold path_delay]][-justify][-enable_preset_clear_arcs][-significant_digits digits][-nosplit][-sort_by group|slack]

report_timing_requirementsReports timing path requirements (user attributes) andrelated information.

int report_timing_requirements[-attributes][-ignored][-from from_list][-through through_list][-to to_list][-expanded][-nosplit]

Synthesis Commands


report_transitive_faninReports logic in the transitive fanin of specified sinks.

int report_transitive_fanin-to sink_list[-nosplit]

report_transitive_fanoutReports logic in the transitive fanout of specifiedsources.

int report_transitive_fanout-clock_tree | -from source_list[-nosplit]

report_ultra_optimizationReports on whether or not the DC Ultra optimizationmode is set and whether licenses have been checkedout correctly.

int report_ultra_optimization

report_wire_loadDisplays the characteristics of the wire load modelsset on a design or in a library.

int report_wire_load[-design design_name][-name model_name][-libraries][-nosplit]

report_xrefGenerates a cross-reference between schematicobjects and sheets on which they occur.

int report_xref [-nosplit]

reset_compare_design_scriptRemoves the compare_design script if it exists.

int reset_compare_design_script


92


reset_designRemoves from the current design all user-specifiedobjects and attributes, except those defined usingset_attribute.

int reset_design

reset_modeResets the modes of the specified instances.

int reset_mode [instance_list]

reset_pathResets specified paths to single cycle timing.

int reset_path[-setup | -hold][-rise | -fall][-from from_list][-through through_list][-to to_list]

reset_switching_activityRemoves the toggle_rate and static_probabilityattributes, and/or the max_toggle_rate attribute, fromnets, pins, cells and/or ports of the current design.

int reset_switching_activity-switching_activity | -max_toggle_rate| -all[-verbose]

restore_test (dctcl-mode only)


return (dctcl-mode only)


Synthesis Commands


rewire_clock_gatingProvides a mechanism for directing compile-incremental, physopt, and physopt -incremental tochange the clock-gating cell implemented by PowerCompiler for a particular register.

int rewire_clock_gating[-gating_cell new_clock_gating_cell][-gated_registers gated_registers_list][-verbose][-undo]

rtl2saifCreates a SAIF forward-annotation file starting fromthe top level of the design.

int rtl2saif[-output file_name][-design design_name]

rtl_analyzer (dctcl-mode only)


rtldrcAnalyzes the testability of a design at the RTL andgate level, using Verilog or VHDL RTL sources.

int rtldrc[-tristate][-max_detail_lines n]

scan (dctcl-mode only)


scheduleInvokes the scheduling and allocation functions ofBehavioral Compiler.

int schedule[-effort quick | low | medium | high][-io_mode cycle_fixed | superstate_fixed][-extend_latency][-host hostname][-arch remote_host_architecture][-allocation_effort quick | low | medium |high]


94


seek (dctcl-mode only)


set (dctcl-mode only)


set_annotated_checkSets the setup, hold, recovery, or removal timingcheck value between two pins.

int set_annotated_checkcheck_value-from from_pins -to to_pins-setup | -hold | -recovery | -removal |-nochange_high | -nochange_low[-rise | -fall][-clock clock_check][-worst]

set_annotated_delaySets the net or cell delay value between two pins.

int set_annotated_delay-net | -cell[-load_delay load_delay_type][-rise | -fall][-min][-max]delay_value-from from_pins -to to_pins[-worst]

set_annotated_transitionSets the transition time at a given pin.

int set_annotated_transition[-rise | -fall][-min][-max] transitionport_pin_list

Synthesis Commands


set_attributeSets the value of an attribute on a design or libraryobject.

list set_attribute object_listattribute_nameattribute_value[-type boolean | integer | float | string][-bus][-quiet]

set_auto_disable_drc_netsSets the auto_disable_drc_net attribute on the currentdesign, causing the specified networks to be haveDRC disabled. This command was previously calledset_auto_ideal_nets.

int set_auto_disable_drc_nets[-default][-none][-all][-clock true | false ][-constant true | false][scan true | false ]

set_autofix_asyncSpecifies the asynchronous port to be used toautomatically correct uncontrollable asynchronousviolations of specified cells, during execution ofpreview_dft or insert_dft, when Autofix utility isenabled.

int set_autofix_asyncasync_portcell_list

set_autofix_clockIf Autofix is enabled, specifies a clock port to be usedfor specified cells, for automatic fixing ofuncontrollable clock violations during execution ofpreview_dft or insert_dft.

int set_autofix_clock clock_port cell_list


96


set_autofix_configurationIf Autofix is enabled, optionally disables automaticfixing of all uncontrollable clock violations or allasynchronous preset/clear violations, duringexecution of preview_dft or insert_dft.

int set_autofix_configuration[-clock true | false][-async true | false][-fix_async_with_scan_en true | false]

set_autofix_elementIf Autofix is enabled, optionally disables automaticfixing of uncontrollable clock violations orasynchronous preset/clear violations for specifiedsequential elements, during execution of preview_dftor insert_dft.

int set_autofix_elementcell_list-clock true | false-async true | false

set_balance_registersSets the balance_registers attribute on the specifieddesigns or on the current design, so that the design isretimed during compile.

int set_balance_registers[true | false][-design design_list]

set_behavioral_resetDirects Behavioral Compiler to set reset behavior forprocess, port, synchronicity, active state, directconnection or FSM generation.

int set_behavioral_reset[-process process_name][-port signal_name][-active high | low][-fsm][-async][-all]

Synthesis Commands


set_boundary_optimizationSets the boundary_optimization attribute on specifiedcells, references, or designs, thus allowing foroptimization across hierarchical boundaries.

int set_boundary_optimizationobj_list[true | false]

set_bsd_bsr_elementCharacterizes a design cell as a boundary-scanregister to be used for the boundary-scan insertion.

int set_bsd_bsr_element-type cell_type-design design_name-access access_list

set_bsd_complianceSpecifies an IEEE 1149.1 compliance-enable patternfor a boundary-scan design.

int set_bsd_compliancepattern_namesignal_port_bit_value_pairs

set_bsd_configurationSpecifies the boundary-scan configuration for adesign.

int set_bsd_configuration[-asynchronous_reset true | false][-default_package package_name][-instruction_encoding default | one_hot][-ir_width instruction_register_length][-style asynchronous | synchronous][-infer_instructions true | false][-check_pad_designs none | all |pad_designs_list]

set_bsd_control_cellDeclares a boundary-scan control register cell tocontrol tristate port pads.

int set_bsd_control_cellBSD_control_register_name -type cell_type-port_list port_list


98


set_bsd_data_cellSpecifies a boundary-scan register cell type to be usedon a specified list of ports in the current design.

int set_bsd_data_cell cell_type-port_list port_list[-direction in | out]

set_bsd_instructionSpecifies boundary-scan instructions to be used byinsert_bsd for the current design or used bycheck_bsd in the verification flow.

int set_bsd_instruction instruction_set[-code inst_code_list][-register user_data_reg][-input_clock_condition clock_conditioning][-output_condition output_conditioning][-internal_scan pin_name]

set_bsd_intestSpecifies the parameters for the INTEST instruction.

int set_bsd_intest[-time real_numbers][-clock_cycles clock_port_integer_pairs]

set_bsd_linkage_portIdentifies the linkage ports in your design.

int set_bsd_linkage_port-port_list list_of_ports

set_bsd_pad_designSpecifies and characterizes a design present inmemory as a pad cell.

int set_bsd_pad_designdesign_name-access access_list-type pad_type-differential differential-disable_res disable_result-lib_cell true | false

Synthesis Commands


set_bsd_pathSpecifies the order of the cells in the boundary scanregister.

int set_bsd_path identifier_list

set_bsd_portIdentifies existing ANSI/IEEE Std. 1149.1 TestAccess ports of the current design, for the check_bsdcommand.

int set_bsd_port port_type TAP_port

set_bsd_power_up_resetSpecifies and characterize the power up reset cell forthe current design.

int set_bsd_power_up_reset-cell_name cell_name-reset_pin_name reset_pin_name-active high | low-delay power up reset delay

set_bsd_registerDeclares a user-defined data register to be used for theboundary-scan insertion.

int set_bsd_registerregister_identifier-cell hierarchical_cell_name-access access_list[-style asynchronous | synchronous | global]

set_bsd_runbistSpecifies the parameters for the RUNBISTinstruction.

int set_bsd_runbist[-time runtime][-clock_cycles clock_port_integer_pairs][-signature pattern]

set_bsd_signalSpecifies a boundary scan signal type to be placed ona specified port in the current design.

int set_bsd_signal port_type port_name


100


set_bsd_tap_elementCharacterizes a design cell as a boundary-scan tapcontroller to be used for boundary-scan insertion.

int set_bsd_tap_element-design design_name-access access_list

set_bsr_cell_typeSpecifies the minimum acceptable boundary-scan cellimplementation for a set of ports in the current design.

int set_bsr_cell_type-port port_list[-direction in | out]cell_type

set_case_analysisSpecifies that a port or pin is at a constant logic value1 or 0.

string set_case_analysisvalueport_or_pin_list

set_cell_degradationSets the cell_degradation attribute to a specified valueon specified ports or designs.

int set_cell_degradationcell_degradation_valueobject_list

set_cell_internal_powerSets or removes the power_value attribute on or fromspecified pins; the value represents the powerconsumption for a single toggle of each pin.

int set_cell_internal_powerpin_names[power_value [unit]]

Synthesis Commands


set_clock_gating_checkPuts setup and hold checks on clock gating cells.

int set_clock_gating_check[-setup setup_margin][-hold hold_margin][-rise][-fall][-high | -low] object_list

set_clock_gating_registersForces the enabling or disabling of clock gating forspecified registers in the current design, overriding allconditions necessary for automatic RTL clock gatingby the insert_clock_gating command.

int set_clock_gating_registers[-include_instances register_list][-exclude_instances register_list][-undo register_list]

set_clock_gating_signalsForces the enabling or disabling of clock gating forspecified signals, overriding the conditions necessaryfor automatic RTL clock gating by elaborate-gate_clock.

int set_clock_gating_signals[-design design_name][-include signal_list][-exclude signal_list]

set_clock_gating_styleSets the clock gating style that HDL Compiler and theinsert_clock_gating command use for clock gating.

int set_clock_gating_style[-sequential_cell seq_cell][-minimum_bitwidth minsize_value][-setup setup_value][-hold hold_value][-positive_edge_logic gate_list][-negative_edge_logic gate_list][-control_point none | before | after][-control_signal scan_enable | test_mode][-observation_point true | false][-observation_logic_depth depth_value][-max_fanout max_fanout_count][-no_sharing]


102


set_clock_latencySpecifies clock network latency.

string set_clock_latency[-rise][-fall][-min][-max][-source][-early][-late]delayobject_list

set_clock_transitionSets clock transition attributes on clock objects.

int set_clock_transitiontransition[-rise | -fall][-min][-max]clock_list

set_clock_uncertaintySpecifies uncertainty (skew) of clock networks.

string set_clock_uncertainty[-from from_clock][-to to_clock][-rise][-fall][-setup][-hold] uncertainty[object_list]

set_combinational_typeSets attributes on cell instances to specify whichcombinational cells from the target library are to beused by compile.

int set_combinational_type-replacement_gate replacement_gate[cell_list]

Synthesis Commands


set_common_resourceSpecifies a group of operations to be scheduled on thesame resources by Behavioral Compiler.

int set_common_resource[-process process_name]operation_names[-min_count min_resources][-max_count max_resources][-force_sharing][-exclusive]

set_compare_design_scriptA command to be added to the compare_designscript, to be used during verification with thebalance_buffer, compare_design, compile,insert_pads, reoptimize_design, and translatecommands.

int set_compare_design_script[-ignore endpoint_list][-only endpoint_list][-accept sub_design_list]

set_compile_partitions (dctcl-mode only)

Specifies the compile partitions for the current design.For use in dc_shell-t (Tcl mode of dc_shell) only.

int set_compile_partitions{-level level} | {-designs design_list} |-all | -auto[-force][-no_reset]

set_connection_classSets the connection class value on ports.

int set_connection_classconnection_class_valueobject_list


104


set_context_marginSpecifies the margin by which to tighten or relaxconstraints.

string set_context_margin[-percent][-relax][-min][-max]value[object_list]

set_cost_prioritySets the cost_priority attribute to a specified value onthe current design.

int set_cost_priority[-default][-delay][-min_delay][-design_rules][-firm_area_limit]cost_types

set_critical_rangeSets the critical_range attribute to a specified value ona list of designs.

int set_critical_rangerange_value designs

set_cyclesSets the number of cycles between two BehavioralCompiler operations and/or loop boundaries for aspecified process or for all processes.

int set_cycles[-process process_name]cycle_offset-from_option start_operation-to_option end_operation

Synthesis Commands


set_datapath_optimizationSets the datapath_optimization attribute on arithmeticoperations in the current design to prevent them frombeing transformed by the built-in datapathoptimization feature in the compile command.

This command is not currently supported.

int set_datapath_optimizationobject_list[true | false]

set_default_driveSets the default driving strength for specified objects,to be used by Top-Down Environmental Propagation(TDEP).

int set_default_drive[-min][-max][-rise][-fall][-none][resistance][cell_or_pin_list]

set_default_driving_cellSets the default driving cell for specified objects, to beused by Top-Down Environmental Propagation(TDEP).

int set_default_driving_cell[-lib_cell lib_cell_name][-library lib][-rise][-fall][-pin pin_name][-from_pin from_pin_name][-dont_scale][-no_design_rule][-multiply_by factor][-none]cell_or_pin_list


106


set_default_fanout_loadSets the default fanout load to be used by Top-DownEnvironmental Propagation (TDEP).

int set_default_fanout_load[-none][fanout_load_value][cell_or_pin_list]

set_default_input_delaySets the value of the input delay as a percentage of theclock period to be assigned during environmentpropagation.

int set_default_input_delay[-none]percent_delay[cell_or_pin_list]

set_default_loadSets the default load to be used by Top-DownEnvironmental Propagation (TDEP).

int set_default_load[-min][-max][-pin_load][-wire_load][-none][value][cell_or_pin_list]

set_default_output_delaySets the output delay as a percentage of the clockperiod to be assigned during environmentpropagation.

int set_default_output_delay[-none]percent_delay[cell_or_pin_list]

Synthesis Commands


set_design_licenseAdds license information to the current design. Theset_design_license command can be used to require alicense before a design can be read in.

int set_design_license[-dont_show references][-quiet][-limited limited_keys]regular_keys

set_dft_configurationSets the DFT configuration for the current design.

int set_dft_configuration[-order list_of_clients]

set_dft_signalSpecifies DFT signals for insert_dft to use forimplementing test point signals of a specified signaltype.

int set_dft_signaldft_signal_type-port port_list[-hookup pin [-sense sense]]

set_direct_power_rail_tieSets the direct_power_rail_tie attribute on librarypins.

int set_direct_power_rail_tielib_pin_list[true | false]

set_disable_clock_gating_checkDisables the clock gating check for specified objectsin the current design.

string set_disable_clock_gating_checkobject_list


108


set_disable_timingDisables timing arcs in the current design.

int set_disable_timingobject_list[-from from_pin_name -to to_pin_name][-restore]

set_dont_touchSets the dont_touch attribute on cells, nets, references,and designs in the current design, and on library cells,to prevent these objects from being modified orreplaced during optimization.

int set_dont_touch object_list[true | false]

set_dont_touch_networkSets the dont_touch_network attribute on clocks, pins,or ports in the current design to prevent cells and netsin the transitive fanout of the set_dont_touch_networkobjects from being modified or replaced duringoptimization.

int set_dont_touch_network object_list

set_dont_useSets the dont_use attribute on library cells to excludethem from the target library during optimization.

int set_dont_use object_list

set_driveSets the rise_drive or fall_drive attributes to specifiedresistance values on specified input and inout ports.

int set_driveresistance[-rise][-fall][-min][-max]port_list

Synthesis Commands


set_driving_cellSets attributes on input or inout ports of the currentdesign, specifying that a library cell or pin will drivethe ports.

int set_driving_cell[-lib_cell lib_cell_name][-library lib][-rise][-fall][-pin pin_name][-from_pin from_pin_name][-dont_scale][-no_design_rule][-input_transition_rise rtran][-input_transition_fall ftran][-multiply_by factor]port_list

set_electromigration_drcSets or resets the electromigration DRC constraint forthe current design by setting the electromigration_drcattribute.

int set_electromigration_drcon | off[-use_switching_activity]

set_equalDefines two input ports as logically equivalent.

int set_equalport1port2

set_exclusive_useMaps a specified HDL variable to a unique BehavioralCompiler register for a specified process or for allprocesses.

int set_exclusive_use[-process process_name]variable_name[-shared]


110


set_false_pathRemoves timing constraints from particular paths.

int set_false_path[-rise | -fall][-setup | -hold][-from from_list][-through through_list][-to to_list][-reset_path]

set_fanout_loadSets the fanout_load attribute to a specified value onspecified output ports of the current design.

int set_fanout_load value port_list

set_fix_holdSets a fix_hold attribute on clocks in the currentdesign.

int set_fix_hold clock_list

set_fix_multiple_port_netsSets the fix_multiple_port_nets attribute to a specifiedvalue on the current design.

int set_fix_multiple_port_nets-default | -all | [-feedthroughs][-outputs][-constants][-buffer_constants]

set_flattenSets or removes the flatten attribute on specifieddesigns or on the current design, to enable or disablethe flattening optimization step during compile.

int set_flatten[true | false][-effort low | medium | high][-minimize single_output | multiple_output |none][-phase true | false][-design design_list][-quiet]

Synthesis Commands


set_fpgaConfigures the current design for behavioral synthesistargeting an FPGA.

int set_fpga[-target FPGA_target][-device FPGA_device][-speed FPGA_speed_grade][-module][-list]

set_fsm_encodingSpecifies the bit encodings for states in the currentdesign.

int set_fsm_encoding encoding_list

set_fsm_encoding_styleDefines the encoding style for assigning unencodedstates.

int set_fsm_encoding_styleone_hot | binary | gray | auto

set_fsm_minimizeDetermines whether or not state minimization is to beperformed on the state machine design duringcompile.

int set_fsm_minimize true | false

set_fsm_orderSets the ordering of states in a state machine design.

int set_fsm_order state_list

set_fsm_preserve_stateSpecifies states to be preserved during stateminimization.

int set_fsm_preserve_state state_list

set_fsm_state_vectorSpecifies the instance names for flip-flops used toimplement the state vector.

int set_fsm_state_vector vector_list


112


set_ideal_latencySpecifies ideal network latency.

string set_ideal_latency[-rise | -fall][-min][-max]delayobject_list

set_ideal_netSets the ideal_net attribute on specified individualnets in the current design.

int set_ideal_net net_list

set_ideal_networkMarks a set of ports or pins in the current design assources of an ideal network. This disables timingupdate and optimization of cells and nets in thetransitive fanout of the specified objects.

int set_ideal_network[-dont_care_placement]object_list

set_ideal_transitionSpecifies ideal transition for the ideal network andideal nets.

string set_ideal_transition[-rise | -fall][-min][-max]transition_timeobject_list

set_impl_prioritySets the formula attribute of the priority parameterand/or the set_id attribute for implementations insynthetic libraries.

int set_impl_priority[-priority formula][-set_id id]implementation_list

Synthesis Commands


set_implementationSpecifies the implementation to use for syntheticlibrary cell instances in a design.

int set_implementationimplementation_namecell_list[-check_impl]

set_input_delaySets input delay on pins or input ports relative to aclock signal.

int set_input_delaydelay_value[-clock clock[-clock_fall][-level_sensitive]][-network_latency_included][-source_latency_included][-rise][-fall][-max][-min][-add_delay]port_pin_list

set_input_transitionSets the max_transition_rise, max_transition_fall,min_transition_rise, or min_transition_fall attributesto the specified transition values on the specified inputand inout ports.

int set_input_transitiontransition[-rise][-fall][-min][-max]port_list


114


set_isolate_portsSpecifies the ports that are to be isolated from internalfanouts of their driver nets.

int set_isolate_ports[-type buffer][-type inverter][-driver cell_name][-force]port_list

set_isolation_operationsSpecifies a group of operations for operand isolationby Behavioral Compiler.

int set_isolation_operations[-process process_name][-exclude_operations operation_names][-include_operations operation_names]

set_jtag_implementation (dctcl-mode only)


set_jtag_instruction (dctcl-mode only)


set_jtag_manufacturer_id (dctcl-mode only)


set_jtag_part_number (dctcl-mode only)


set_jtag_port (dctcl-mode only)


set_jtag_port_mode (dctcl-mode only)


set_jtag_port_routing_order (dctcl-mode only)


set_jtag_port_type (dctcl-mode only)


Synthesis Commands


set_jtag_version_number (dctcl-mode only)


set_layerDefines features of a schematic layer.

int set_layerlayer_nameattributevalue

set_libcell_dimensionsSets the width and height of a library cell.

int set_libcell_dimensions-cell cell_name-width width-height height

set_libpin_locationSets the location of a pin of a library cell relative tothe origin of the library cell.

int set_libpin_location-cell library_cell_name-pin pin_name_of_the_library_cell-coordinate {x_coordinate y_coordinate}

set_loadSets the load attribute to a specified value on specifiedports and nets.

int set_loadvalueobjects[-subtract_pin_load][-min][-max][[-pin_load][-wire_load]]

set_local_link_librarySets the local_link_library attribute to specified filesand libraries on the current design.

int set_local_link_librarylocal_link_library


116


set_logic_dcSpecifies one or more input ports in the current designthat are to be driven by don't care. The set_logic_oneand set_logic_zero commands are used the same wayas this command.

int set_logic_dc port_list

set_logic_oneSpecifies one or more input ports in the current designthat are to be driven by logic 1. The set_logic_zeroand set_logic_dc commands are used the same way asthis command.

int set_logic_one port_list

set_logic_zeroSpecifies one or more input ports in the current designthat are to be driven by logic 0. The set_logic_one andset_logic_dc commands are used the same way as thiscommand.

int set_logic_zero port_list

set_map_onlySets the map_only attribute on specified objects sothat they can be excluded from logic-leveloptimization during compile.

int set_map_onlyobject_listflag

set_max_areaSets the max_area attribute to a specified value on thecurrent design.

int set_max_area[-ignore_tns]area_value

Synthesis Commands


set_max_capacitanceSets the max_capacitance attribute to a specified valueon the specified ports and designs.

int set_max_capacitancecapacitance_valueobject_list

set_max_cyclesSets the maximum number of cycles between twoBehavioral Compiler operations and loop boundariesfor a specified process or for all processes.

int set_max_cycles[-process process_name]cycle_offset-from_option start_operation-to_option end_operation

set_max_delaySpecifies a maximum delay target for paths in thecurrent design.

int set_max_delaydelay_value[-rise | -fall][-from from_list][-through through_list][-to to_list][-group_path group_name][-reset_path]

set_max_dynamic_powerSets the target dynamic power for the current designby setting the max_dynamic_power attribute to aspecified value.

int set_max_dynamic_powerdynamic_power[GW | MW | KW | W | mW | uW | nW | pW | fW |aW]


118


set_max_fanoutSets the max_fanout attribute to a specified value onspecified input ports and/or designs.

int set_max_fanoutfanout_valueobject_list

set_max_leakage_powerSets the target leakage power for the current design bysetting the max_leakage_power attribute to a specifiedvalue.

int set_max_leakage_power leakage_power[GW | MW | KW | W | mW | uW | nW | pW | fW |aW]

set_max_peak_noiseSets the max_peak_noise attribute to a specified valueon specified ports or designs.

int set_max_peak_noisenoise_valueobject_list

set_max_time_borrowSets the max_time_borrow attribute to a specifiedvalue on clocks, latch cells, data pins, or clock(enable) pins, to constrain the amount of timeborrowing possible for level-sensitive latches.

int set_max_time_borrowdelay_valueobject_list

set_max_toggle_rateSets or resets the max_toggle_rate attribute ondesigns, cells, nets, pins, and ports of the currentdesign.

int set_max_toggle_rateobject_list[-value max_tr_value][-clock clock_name]

Synthesis Commands


set_max_transitionSets the max_transition attribute to a specified valueon specified ports or designs.

int set_max_transitiontransition_valueobject_list

set_memory_input_delaySets the input delay on a memory to be used byBehavioral Compiler.

int set_memory_input_delay[delay_value][-external ext_delay_value][-name mem_name]

set_memory_output_delaySets the output delay on a memory to be used byBehavioral Compiler, and enables operation chainingon the outputs of the memory.

int set_memory_output_delaydelay_value[-external ext_delay_value][-name mem_name]

set_min_capacitanceSets the min_capacitance attribute to a specified valueon specified input ports in the current design.

int set_min_capacitancecapacitance_valueobject_list

set_min_cyclesSets the minimum number of cycles between twoBehavioral Compiler operations and loop boundariesfor a specified process or for all processes.

int set_min_cycles[-process process_name]cycle_offset-from_option start_operation-to_option end_operation


120


set_min_delaySpecifies a minimum delay target for paths in thecurrent design.

int set_min_delaydelay_value[-rise | -fall][-from from_list][-through through_list][-to to_list][-reset_path]

set_min_fault_coverage (dctcl-mode only)


set_min_librarySets an alternate library to use for minimum delayanalysis.

int set_min_librarymax_library-min_versionmin_library | -none

set_min_porositySets the minimum_porosity attribute on specifieddesigns or on the current design.

int set_min_porosityporosity_value[design_list]

set_minimize_tree_delaySets the minimize_tree_delay attribute on a design ordesigns, thus determining whether an arithmeticexpression tree will be restructured to minimize delayduring compile. By default, all expression trees arecandidates for tree height minimization if timingconstraints are specified.

int set_minimize_tree_delay[true | false][-design design_list]

Synthesis Commands


set_modeSelects the mode of a component.

int set_mode[mode_list][instance_list]

set_model_driveSets the model_drive attribute to a specified value onspecified input or inout ports to set their drive valuesduring synthetic library modeling.

int set_model_drivedrive_valueport_list

set_model_loadSets the model_load attribute to a specified value onspecified ports to set their load values during syntheticlibrary modeling.

int set_model_loadload_valueport_list

set_model_map_effortSets the model_map_effort attribute to a specifiedvalue on the current design, to specify the relativeamount of CPU time to use during synthetic librarymodeling.

int set_model_map_effort low | medium | high

set_model_scaleSets the model_scale attribute to a specified value onthe current design, to use as a scale factor incalculating timing constraints during synthetic librarymodeling.

int set_model_scale scale


122


set_multibit_optionsSets the multibit_mode and minimum_multibit_widthattributes to specified values on the current design.

int set_multibit_options[-default][-mode multibit_mode][-minimum_width width]

set_multicycle_pathModifies the single-cycle timing relationship of aconstrained path.

int set_multicycle_pathpath_multiplier[-rise | -fall][-setup | -hold][-start | -end][-from from_list][-to to_list][-through through_list][-reset_path]

set_operand_isolation_cellSpecifies a list of GTECH cells to be operandisolation candidates.

int set_operand_isolation_cell[object_list]

set_operand_isolation_slackSets the timing threshold below which the automaticisolation roll back operation is not triggered.

int set_operand_isolation_slack slack_number

set_operand_isolation_styleSets the operand isolation style that Power Compileruses for operand isolation.

int set_operand_isolation_style[-logic logic_style]

Synthesis Commands


set_operating_conditionsDefines the operating conditions for the currentdesign.

int set_operating_conditions[-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib][-min_phys min_proc][-max_phys max_proc][-library lib][condition]

set_oppositeDefines two input ports as logically opposite.

int set_oppositeport1port2

set_optimize_registersSets the optimize_registers attribute on the specifieddesign or on the current design, so that compileautomatically invokes the DC-Ultraoptimize_registers command to retime the designduring optimization.

int set_optimize_registers[true | false][-design design_list]

set_output_delaySets output delay on pins or output ports relative to aclock signal.

int set_output_delaydelay_value[-clock clock[-clock_fall] ][[-level_sensitive]][-network_latency_included][-source_latency_included][-rise][-fall][-max][-min][-add_delay][-group_path group_name] port_pin_list


124


set_pad_typeIndicates the type of I/O pads needed on given ports.

int set_pad_type[-example example_pad][-exact exact_pad][-schmitt | -hysteresis][-pullup][-pulldown][-opendrain][-opensource][-vil vil][-vih vih][-vol vol][-voh voh][-vimin vimin][-vimax vimax][-vomin vomin][-vomax vomax][-currentlevel currentlevel][-clock][-no_clock][-slewrate slewratevalue]design_or_port_list

set_pipeline_stagesSets directives to control the implementation ofDW03_mult_n_stage operators referenced by thespecified cells.

int set_pipeline_stages[cell_list][-min min_stages][-fixed fixed_stages][-auto]

set_port_configurationProvides the Shadow LogicDFT utility withinformation about the input and output ports of thespecified elements that are to receive wrappers.

int set_port_configuration-cell cell_design_ref_list-port port_name[-tristate][-wrapper_exclude][-clock clock_name][-read signal_value_pin_pairs[-write signal_value_pin_pairs

Synthesis Commands


set_port_fanout_numberSets the number of external fanout points driven byspecified ports in the current design.

int set_port_fanout_numberfanout_number port_list

set_port_is_padSets the port_is_pad attribute on specified portsand/or designs, to indicate that those ports are to haveI/O pads attached.

int set_port_is_pad [port_design_list]

set_port_locationAnnotates the specified top-level port with X, Ycoordinates and layer geometry, to be used byFloorplan Manager and Physical Compiler duringexecution of reoptimize_design.

int set_port_location[-coordinate {x_coordinate y_coordinate}][-layer_name {layer_name}][use only in Physical Compiler][-layer_area {lower_x_coordinatelower_y_coordinateupper_x_coordinate upper_y_coordinate}][use only in Physical Compiler]

set_preferSets the preferred attribute on specified library gates.

int set_prefer[-min]gate_list

set_propagated_clockSpecifies propagated clock latency.

string set_propagated_clock object_list


126


set_register_typeSets the latch_type or flip_flop_type attributes ondesigns or cell instances, to specify which sequentialcells from the target library are to be used by compile.

int set_register_type[[-exact] -latch example_latch][[-exact] -flip_flop example_flip_flop][cell_or_design_list]

set_resistanceSets the resistance value on nets.

int set_resistancevalue[-min][-max]net_list

set_resource_allocationSets the resource_allocation attribute on the currentdesign, thus specifying the type of resource allocationto be used by compile.

int set_resource_allocationnone | area_only | area_no_tree_balancing |constraint_driven

set_resource_implementationSets the resource_implementation attribute on thecurrent design, thus specifying the type of resourceimplementation to be used by compile.

int set_resource_implementationarea_only | constraint_driven | use_fastest

set_rtl_loadSets an RTL load value for capacitance and resistanceon pins, ports and nets.

int set_rtl_load-cap cvalue-res rvalue[-min][-max]pin_net_list

Synthesis Commands

128


set_scan_elementSets the scan_element attribute on specified designobjects, to determine whether or not insert_scanreplaces them with scan cells.

int set_scan_elementtrue | falsecell_design_ref_list-multibit multi-bit_list

set_scan_linkDeclares a scan link for the current design.

int set_scan_linkscan_link_name wire | scan_out_lockup

set_scan_pathSpecifies a scan chain for the current design.

int set_scan_pathscan_chain_name[ordered_list][-dedicated_scan_out true | false][-complete true | false][-chain_length integer_or_default][-clock clock_name]

set_scan_register_typeSpecifies a list of scan sequential cells from the targetlibrary that are to be used by insert_scan or compile-scan when scan replacing designs or cell instances.

int set_scan_register_type[-exact]-type example_scan_seq_cell_list[cell_or_design_list]

set_scan_segmentIdentifies existing logic in the current design that is tobe designated a scan segment.

int set_scan_segmentscan_segment_name[-access signal_type_pin_pairs][-contains member_list][-synthesizable true | false | default][-reverse_order true | false]

Synthesis Commands


set_scan_signalSpecifies one or more scan signals for the currentdesign.

int set_scan_signalscan_signal_type-port port_list[-hookup pad_instance_name/port [-sensesense]][-chain chain_list]

set_scan_stateSets the scan state status for the current db design.

int set_scan_statetest_ready | scan_existing

set_scan_style (dctcl-mode only)


set_scan_transparentSets the scan_latch_transparent attribute on specifieddesign objects, to determine whether or notlevel-sensitive sequential cells are modeled astransparent latches during automatic test patterngeneration (ATPG).

int set_scan_transparenttrue | falsecell_design_ref_list-multibit multi-bit_list-existing

set_scan_tristateFor specified tristate nets, determines whetherinsert_scan and insert_dft disable all drivers, enableexactly one driver, or leave the nets untouched, duringscan shift.

int set_scan_tristatedisabling_option-net net_list


130


set_share_cseSets the share_cse attribute, which determineswhether common subexpressions are shared duringcompile. By default, all common subexpressions areshared unless otherwise specified.

int set_share_cse[true | false][-design design_list]

set_signal_typeSets the signal type on a list of pins or ports.

int set_signal_typesignal_type port_list[-associated_clock clk][-index signal_index]

set_simple_compile_modePlaces Design Compiler into simple compile mode.

int set_simple_compile_mode[true | false][-verbose][-budget]

set_state_for_retimingSets the state_for_retiming attribute on cells in thecurrent design. This command can effect bothhierarchical cells and sequential leaf cells.

int set_state_for_retimingcell_list preserve | dont_care

set_structureSets various structure attributes on a design or on a listof designs, to determine whether and how the designsare structured during compile.

int set_structure[true | false][-design design_list][-boolean true | false][-boolean_effort low | medium | high][-timing true | false]

Synthesis Commands


set_switching_activitySets (or resets) the toggle_rate and static_probabilityvalues for nets, pins, and ports of the current design.

int set_switching_activity[-static_probability sp_value][-toggle_rate tr_value][-state_dep boolean_eq_of_pins][-path_dep sources_of_path][-transition_type rising | falling][-period period_value | -clock clock_name]object_list

set_synlib_dont_get_licenseSpecifies a list of synthetic library part licenses thatare not automatically checked out.

int set_synlib_dont_get_licenselicense_list

set_test_assumeSets the test_assume attribute to a logic value to beassumed on specified cell output pins throughout testdesign rule checking.

int set_test_assumezero_or_one_valuepin_list

set_test_dont_fault (dctcl-mode only)


set_test_holdSets the test_hold attribute to a logic value to beassumed on specified input ports during testing.

int set_test_holdzero_or_one_valueport_list

set_test_initialSets the test_initial attribute to a logic value to beassumed on specified cell output pins at the start oftest design rule checking and fault simulation.

int set_test_initialzero_or_one_valuepin_list


132


set_test_isolateSets the test_isolate attribute on the specified cells,pins or ports, indicating that they are to be logicallyisolated and considered untestable during test designrule checking.

int set_test_isolate pin_cell_port_list

set_test_mask_fault (dctcl-mode only)


set_test_methodology (dctcl-mode only)


set_test_require (dctcl-mode only)


set_test_signalSpecifies test-mode signals for the current design.

int set_test_signaltest_signal_type-port port_name

set_test_targetDefine the core wrapper modes for a specific mode inthe test schedule.

int set_test_target[-purpose core_internal_test |top_internal_test | mission_mode][-cores core_list][-test_mode mode_name ]

set_test_unmask_fault (dctcl-mode only)


set_timing_rangesSets timing ranges for the current design.

int set_timing_ranges[timing_ranges][-library library_name]

Synthesis Commands


set_transform_for_retimingSets the transform_for_retiming attribute on cells inthe current design. This can effect both hierarchicalcells and sequential leaf cells.

int set_transform_for_retimingcell_listmulticlass | decompose | dont_retime

set_true_delay_case_analysisSets the true_delay_case_analysis attribute, whichspecifies the input vector value to use for specifiedpins or ports of the current design for the -true and-justify options of report_timing.

int set_true_delay_case_analysis0 | 1 | r | f | none port_pin_list

set_ultra_optimizationSets the DC Ultra optimization mode and checks outthe DC Ultra license, if available, for the currentDesign Compiler session.

int set_ultra_optimization[true | false][-force]

set_unconnectedLists output ports to be unconnected.

int set_unconnected port_list

set_ungroupSets the ungroup attribute on specified designs, cells,or references, indicating that they are to be ungroupedduring compile.

int set_ungroupobject_listtrue | false

set_unix_variableSets the value of a UNIX environment variable.

string set_unix_variablevariable_namenew_value


134


set_user_budgetSets user budgets or budget ratios.

string set_user_budget-from object_list-to object_list[-percent]value

set_wire_load_min_block_sizeSets the wire load min_block_size attribute on thecurrent design.

int set_wire_load_min_block_size size

set_wire_load_modeSets the wire_load_model_mode attribute on thecurrent design, specifying how wire load models areto be used to calculate wire capacitance in nets.

int set_wire_load_mode mode_name

set_wire_load_modelSet the wire_load_attach_name attribute on designs,ports, hierarchical cells of current design, or thespecified cluster of the current design, for selecting awire load model to use in calculating wirecapacitance.

int set_wire_load_model-name model_name[-library lib][-min][-max][-cluster cluster_name][object_list]

Synthesis Commands


set_wire_load_selection_groupSpecify a selection group to use for determining awire load model to be assigned to designs and cells orto a specified cluster. This command is supported onlyfor the enclosed wire load mode.

int set_wire_load_selection_group[-library lib][-min][-max][-cluster cluster_name]group_name[object_list]

set_wired_logic_disableSets the wired_logic_disable attribute on the specifiedECL designs, to indicate whether or not the creationof wired OR logic is to be disabled when optimizingthe designs using compile.

int set_wired_logic_disableobject_list[true | false]

set_wrapper_elementSets the wrapper_element attribute on a list ofelements around which preview_dft and insert_dft areto insert a wrapper when the Shadow LogicDFTutility is enabled.

int set_wrapper_elementcell_design_ref_list-type wrapper_type

setenv (dctcl-mode only)

Sets the value of a system environment variable.

string setenv variable_name new_value

shSends a command to the UNIX operating system.

int sh command


136


simplify_constantsPropagates constants and other information in thecurrent design.

int simplify_constants[-verify][-verify_hierarchically][-verify_effort low | medium | high][-boundary_optimization]

sizeof_collection (dctcl-mode only)

Returns the number of objects in a collection.

int sizeof_collection collection1

socket (dctcl-mode only)


sort_collection (dctcl-mode only)

Sorts a collection based on one or more attributes,resulting in a new, sorted collection. The sort isascending by default.

collection sort_collection[-descending]collection1criteria

source (dctcl-mode only)

Read a file and evaluate it as a Tcl script.

string source[-echo][-verbose] file

split (dctcl-mode only)


string (dctcl-mode only)


Synthesis Commands


sub_designs_of (dctcl-mode only)

Gets the subdesigns according to the options. For usein dc_shell-t (Tcl mode of dc_shell) only.

collection sub_designs_of[-hierarchy][-in_partition | -partition_only][-dt_only | -ndt_only][-multiple_instances | -single_instances][-names_only]design

sub_instances_of (dctcl-mode only)

Gets the subinstances according to the options. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

collection sub_instances_of[-hierarchy][-in_partition][-partition_only][-dt_only][-ndt_only][-of_references reference_list][-master_instance][-names_only]design

subst (dctcl-mode only)


suppress_message (dctcl-mode only)

Disables printing of one or more informational orwarning messages.

string suppress_message [message_list]

switch (dctcl-mode only)


syntax_checkEnables or disables Syntax Checker syntax_checkmode, which checks commands for syntax errorswithout executing them.

int syntax_check true | false


138


tclLog (dctcl-mode only)


tell (dctcl-mode only)


time (dctcl-mode only)


trace (dctcl-mode only)


trace_netsEnables global net tracing during check_test on thespecified nets in the current design.

int trace_nets hierarchical_net_list

transform_csaTransforms arithmetic operators (for example,addition, subtraction, and multiplication) into thecarry save adder (CSA) operator, for the specifieddesign or for the current design.

int transform_csa[design_name][-labelled_only][-decompose_multiply all | none | constant][-duplicate][-area][-group][-dont_split]

translateTranslates a design from one technology to another.

int translate[-verify][-verify_hierarchically][-verify_effort low | medium | high][-preserve_structure]

Synthesis Commands


unaliasRemoves alias definitions.

list unalias[-all][alias_list]

ungroupRemoves a level of hierarchy.

int ungroupcell_list | -all[-prefix prefix_name][-flatten][-simple_names][-soft][-small n][-force]

uniquifyRemoves multiply-instantiated hierarchy in thecurrent design by creating a unique design for eachcell instance.

int uniquify[-force][-base_name base_name][-cell cell_list][-reference design_name][-new_name new_design_name]

unschedulePermits Behavioral Compiler to reschedule I/Ooperations into cycles different from those defined inthe original HDL description.

int unschedule operation_names

unset (dctcl-mode only)


unset_fpgaRemoves the behavioral synthesis FPGAconfiguration on the current design. The design isrestored to targeting an ASIC implementation.

int unset_fpga


140


unsuppress_message (dctcl-mode only)

Enables printing of one or more suppressedinformational or suppressed warning messages.

string unsuppress_message [messages]

untrace_netsDisables global net tracing during check_test on anyspecified nets for which net tracing had beenpreviously enabled by trace_nets.

int untrace_netshierarchical_net_list | -all

update (dctcl-mode only)


update_boundsUpdates an existing bound by adding or removingobjects. The bound should be of type movebound.

int update_clusters cell_list

update_clustersUpdates the clusters associated with the currentdesign to reflect the changes made to a subdesign.

int update_bounds[-name bound_name][-bound bound_object][-add][-remove]cell_listcell_list

update_libReads in a specified library file and uses it to updatean existing technology, synthetic, or symbol library.

int update_lib[-overwrite][-permanent]library_namefile_name[-no_warnings]

Synthesis Commands


update_scriptModifies an old dc_shell script to use current dc_shellcommands.

int update_script[-from_version version]script_file_name[-output_file output_file_name]

update_timingUpdates timing information on the current design.

int update_timing

uplevel (dctcl-mode only)


upvar (dctcl-mode only)


variable (dctcl-mode only)


vwait (dctcl-mode only)


whichDisplays the pathname of one or more files, indc_shell or in dc_shell-t (Tcl mode of dc_shell).

list which file_names

whileLoop execution control structure.

while ( expression ) {loop-statement-block}


142


writeWrites a design netlist or schematic from dc_shell to afile.

int write[-format output_format][-hierarchy][-no_implicit][-modified][-output output_file_name][-library library_name][design_list][-names_file name_mapping_files][-donot_expand_dw]

write_bsd_protocolWrites a boundary-scan protocol file.

int write_bsd_protocol[-out protocol_file][-format tpf | stil]

write_bsdlGenerates the boundary-scan description language(BSDL) file for a boundary-scan design.

int write_bsdl[-naming_check VHDL | BSDL | none][-output file_name][-effort low | medium | high]

write_clustersWrites to a file in Physical Design Exchange Format(PDEF) the physical cluster annotations associatedwith a design.

int write_clusters[-design design_name][-output new_cluster_file_name][-no_attributes][-hier_cells][-new_cells_only original_cluster_file_name]

Synthesis Commands


write_compare_design_scriptSaves the compare_design script, which containsdc_shell commands to be used during verificationwith balance_buffer, compare_design, compile,insert_pads, reoptimize_design, and translate.

int write_compare_design_script

write_compile_script (dctcl-mode only)

Writes a compile script for the specified design. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

write_compile_script[-absolute_paths][-hierarchy][-format dcsh | dctcl][-no_reports][-refining]-destination pass[-update design_list][design]

write_constraintsWrites constraints for the place and route tools.

int write_constraints[-output file_name][-format synopsys | sdf | sdf-v2.1][-max_paths max_path_number][-nworst nworst_number][-max_path_slack slack_value][-cover_design | -cover_nets][-net_priorities][-min_net_priority min_priority_number][-max_net_priority max_priority_number][-low_priorities][-max_path_timing][-net_timing][-load_delay net | cell][-net_capacitance][-subtract_pin_cap][-cell_groups][-hierarchy][-by_input_pin_name][-by_output_pin_name][-max_nets max_net_number][-from start_point_list][-to end_point_list][-through through_point_list]


144


write_design_lib_pathsWrites to a file the paths to which design libraries aremapped.

int write_design_lib_paths[-filename file_name][-dc_setup]

write_designlist (dcsh-mode only)

Writes a list of designs referenced by the specifieddesign or by the current design.

int write_designlist[-output listfile][design]

write_environmentWrites the variable settings and constraints for thespecified cells or designs.

write_environment[-cells cell_list | -designs design_list][-format dcsh | dctcl][-output file_name][-suffix suffix][-environment_only][-constraints_only][-no_lib_info]

write_file (dctcl-mode only)


write_ibm_constraintsWrites Synopsys Design Constraints (SDC) in aneutral format for import into the IBM EinsTimerstatic timing analysis tool.

int write_ibm_constraints[-hierarchy][-full_path_lib_names][-output output-file-name][-ignored_file ignored-commands-file-name]

Synthesis Commands


write_layout_scanWrites scan chain information for performing scanchain reordering using third-party place and routetools.

This command is part of Scan Planner, which isavailable with a separate license.

int write_layout_scan[-output output_command_file][-noclockdomain]

write_libWrites a compiled library to disk in Synopsysdatabase, EDIF, or VHDL format.

int write_lib library_name[-format db | edif | vhdl][-output file_name][-names_file file_list][-macro_only]

write_makefile (dctcl-mode only)

Writes a makefile that defines the dependencies andcommands required to compile the specified design.For use in dc_shell-t (Tcl mode of dc_shell) only.

write_makefile[-absolute_paths][-dependencies depends][-dc_shell exec_name][-format dcsh | dctcl]-destination pass[-target target_name][-lsf [-bsubargs bsub_args]][-update design_list][design]

write_parasiticsWrites parasitics in SPEF format to a disk file for thedelay calculation tools.

int write_parasitics[-output file_name][-format reduced | distributed][-min][-ratio ratio_number][-script]


146


write_partition (dctcl-mode only)

Writes the database for a design into the AutomatedChip Synthesis data structure. For use only indc_shell-t (Tcl mode of dc_shell).

int write_partition-type pre | post[-destination pass][-hierarchy][design]

write_partition_constraints (dctcl-mode only)

Writes out the timing constraints for a design. For useonly in dc_shell-t (Tcl mode of dc_shell).

int write_partition_constraints[-hierarchy][-format dcsh | dctcl]-destination pass[-update design_list][design]

write_powerCalculates and saves dynamic and static powerinformation of a design or instance for interface withRTL Analyzer.

int write_power[-net][ -cell][-only cell_or_net_list][-cumulative][-flat][-exclude_boundary_nets][-analysis_effort low | medium | high]

Synthesis Commands


write_rtlWrites the design synthesized by BehavioralCompiler to a file in a hardware description language(VHDL, Verilog, SystemC).

int write_rtl[-format output_format][-output output_file_name][-use_packages vhdl_packages][-include_filesverilog_or_systemc_include_files][-simulation][-debug_mode][-rtl_script script_name][-ignore_rtl_processes]

write_rtl_loadWrites a script of RTL load commands for the currentdesign.

int write_rtl_load[-format dctcl | dcsh][-output file_name]

write_scriptWrites dc_shell commands to save the currentsettings.

int write_script[-hierarchy][-no_annotated_check][-no_annotated_delay][-full_path_lib_names][-format dctcl | dcsh][-output file_name]

write_sdcWrites out a script in Synopsys Design Constraints(SDC) format.

int write_sdcfile_name[-version sdc_version]


148


write_sdfWrites a Standard Delay Format (SDF)back-annotation file.

string write_sdf[-version sdf_version][-instance inst_name]file_name

write_testFormats the test patterns for the current design intoone or more test vector files.

int write_test[-input test_program_name][[-output output_vector_file_name][-cumulative]][-format test_program_format][-first n_patterns][-parallel][-part_number part_number][-revision revision]

write_test_modelWrites a test model file.

int write_test_model[-format ctl | db][-output model_file][design_name]

write_test_protocolWrites a test protocol file.

int write_test_protocol[-out file_name][-format tpf | stil]

write_testsim_libNote: TestSim is obsolete with 1999.10, and has beenreplaced by the TetraMax fault simulator. For moreinformation, see the TetraMax documentation.

Synthesis Commands


write_timingWrites leaf cell pin-to-pin timing information to adisk file.

int write_timing[-output timing_file_name][-load_delay net | cell][-design design_name]


150


Commands Specific to dcsh ModeThe following commands are available only in dcshmode:

allocate_budgetscheck_unmappedexecuteincluderemove_variablewrite_designlist

Commands Specific to dctcl ModeThe following commands are available only in dctclmode:

acs_check_directoriesacs_compile_designacs_create_directoriesacs_get_parent_partitionacs_get_pathacs_merge_designacs_read_hdlacs_recompile_designacs_refine_designacs_report_directoriesadd_to_collectionafterallocate_partition_budgetsappendaproposarrayauto_execokauto_importauto_loadauto_load_indexauto_qualifybinarycatchclockclosecompare_collectionscompile_partitionsconcatcopy_collectioncreate_command_group

Synthesis Commands


create_pass_directoriescurrent_design_namedatedefine_proc_attributesencodingeoferrorerror_infoevalexecexprfblockedfconfigurefcopyfilefileeventfilter_collectionflushforforeach_in_collectionformatget_cellsget_clocksget_clustersget_designsget_generated_clocksget_lib_cellsget_lib_pinsget_libsget_message_infoget_multibitsget_netsget_object_nameget_path_groupsget_pinsget_portsget_referencesget_timing_pathsgetenvgetsglobglobalincrindex_collectioninfointerpis_false


152


is_truejoinlappendlindexlinsertlist_attributeslist_fileslist_licensesllengthlminuslrangelreplacelslsearchlsortmannamespaceopenpackageparse_proc_argumentspidprint_suppressed_messagesprint_variable_groupprintenvprintvarprocproc_argsproc_bodyputsquery_objectsread_dbread_edifread_partitionread_sdcread_verilogread_vhdlredirectreg_global_varregexpregsubremove_from_collectionremove_pass_directoriesrenamereport_partitionsreport_pass_datareturnscan

Synthesis Commands


seeksetset_compile_partitionssetenvsizeof_collectionsocketsort_collectionsourcesplitstringsub_designs_ofsub_instances_ofsubstsuppress_messageswitchtclLogtelltimetraceunsetunsuppress_messageupdateuplevelupvarvariablevwaitwrite_compile_scriptwrite_makefilewrite_partitionwrite_partition_constraints


154


Synthesis VariablesSynthesis tools define variables that are used to controlthe behavior of the tools.

access_internal_pinsControls the creation, deletion, and user access ofinternal pins.

Default value for this variable is false.

acs_area_report_suffixSpecifies the suffix for area reports generated duringthe automated compile process. For use in dc_shell-t(Tcl mode of dc_shell) only.

Default value for this variable is area.

acs_autopart_max_areaDefines partition threshold; used with other acsvariables to control chip-level partitioning. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is 0.0 (no maximumarea specified).

acs_autopart_max_percentControls chip-level partitioning; used with other acsvariables. For use in dc_shell-t (Tcl mode of dc_shell)only.

Default value for this variable is 0.0% (no maximumpercentage specified).

acs_bs_execSpecifies the location of the budget_shell executable.For use in dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is$SYNOPSYS/$arch/syn/bin/budget_shell.

Synthesis Variables


acs_bsub_argsSpecifies the command arguments for the batchsubmission command in the makefile.

Default value for this variable is "-K -P".

acs_bsub_execSpecifies the batch submission command used to runthe dc_shell command when compiling the design.

Default value for this variable is bsub.

acs_budget_output_file_suffixSpecifies the default suffix for log files generated bythe allocate_partition_budgets command. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is btcl.out.

acs_budget_script_file_suffixSpecifies the default suffix for design budgeting scriptfiles generated by the allocate_partition_budgetscommand. For use in dc_shell-t (Tcl mode ofdc_shell) only.

Default value for this variable is btcl.

acs_budgeted_cstr_suffixSpecifies the suffix for constraint files generated bythe derive_partition_budgets command. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is con.

acs_compile_script_suffixSpecifies the default suffix for script files generated bythe write_compile_script command, sourced in themakefile generated by the write_makefile command,and located by the report_pass_data command. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is autoscr.

Synthesis Variables 155

156


acs_constraint_file_suffixSpecifies the default suffix for constraint filesgenerated by write_partition_constraints during theautomated compile process. For use in dc_shell-t (Tclmode of dc_shell) only.

Default value for this variable is con.

acs_cstr_report_suffixSpecifies the default suffix for constraint reportsgenerated during the automated compile process. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is cstr.

acs_db_suffixSpecifies the default suffix for .db files that are read orwritten during the automated compile process. For usein dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is db.

acs_dc_execSpecifies the location of the dc_shell executable. Thisvariable is used by the acs_compile_design,acs_refine_design, and acs_recompile_designcommands to generate the makefile. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is$SYNOPSYS/$arch/syn/bin/dc_shell.

acs_default_pass_nameSpecifies the prefix for the default data directorynames. The pass number (either 0 or 1) is added to theprefix to generate the directory name.

Default value for this variable is pass.

acs_exclude_extensionsSpecifies the file endings of files you do not want theacs_read_hdl command to analyze.

Default value for this variable is "".

Synthesis Variables


acs_exclude_listSpecifies files and directories you do not want theacs_read_hdl command to analyze.

Default value for this variable is "[list$synopsys_root]".

acs_global_user_compile_strategy_scriptSpecifies the base file name for the user-defineddefault compile strategy. For use in dc_shell-t (Tclmode of dc_shell) only.

Default value for this variable is default.

acs_hdl_sourceSpecifies the location of the source code filesanalyzed by the acs_read_hdl command.


acs_lic_waitSpecifies the maximum wait time for checking out allthe licenses required by a compile job. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is 0.

acs_log_file_suffixSpecifies the default suffix for log files generatedduring the automated compile process. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is log.

acs_make_argsSpecifies the command arguments for the make utilitycommand (gmake, by default).

Default value for this variable is "-j".

acs_make_execSpecifies the make utility command used to run thecompile jobs.

Default value for this variable is gmake.


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acs_makefile_nameSpecifies the file name for the makefile generated bythe write_makefile command and run by thecompile_partitions command. For use in dc_shell-t(Tcl mode of dc_shell) only.

Default value for this variable is Makefile.

acs_num_parallel_jobsSpecifies the number of compile jobs to run in parallelwhen using gmake as the make utility. For use indc_shell-t (Tcl mode of dc_shell) only.


acs_override_report_suffixSpecifies the suffix for user-defined partition reportscripts. For use in Tcl mode of dc_shell (dc_shell-t)only.

Default value for this variable is report.

acs_override_script_suffixSpecifies the suffix for user-defined partition compilescripts. For use in dc_shell-t (Tcl mode of dc_shell)only.

Default value for this variable is scr.

acs_qor_report_suffixSpecifies the suffix for QOR reports generated duringthe automated compile process; the default is qor. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is qor.

acs_script_modeSpecifies the dc_shell mode used by Automated ChipSynthesis for the compile process when running oneof the pass commands (acs_compile_design,acs_refine_design, or acs_recompile_design). For usein dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is dctcl.

Synthesis Variables


acs_timing_report_suffixSpecifies the suffix for timing reports generatedduring the automated compile process. For use indc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is tim.

acs_tr_execSpecifies the location of the transcript executable. Foruse in dc_shell-t (Tcl mode of dc_shell) only.

Default value for this variable is$SYNOPSYS/$arch/syn/bin/dc-transcript.

acs_use_autopartitionSets autopartitioning as the default partitioningstrategy for the chip-level compile commands. For usein dc_shell-t (Tcl mode of dc_shell) only.


acs_use_dc_gate_level_budgetingSpecifies that ACS should use dc_shell budgeting toperform gate-level budgeting. For use in dc_shell-t(Tcl mode of dc_shell) only.

Default value for this variable is true.

acs_use_default_delaysSets top-down environment propagation as theconstraint generation method for GTECH designs (theacs_compile_design command). When this variable isfalse (the default), the acs_compile_design commanduses RTL budgeting to generate constraints for thecompile partitions.


acs_use_lsfSpecifies how the dc_shell command is run within themakefile. For use in dc_shell-t (Tcl mode of dc_shell)only.



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acs_user_budgeting_scriptSpecifies the file name for the user-defined budgetingscript. For use in dc_shell-t (Tcl mode of dc_shell)only.

Default value for this variable is budget.scr.

acs_user_compile_strategy_script_suffixSpecifies the suffix for user-defined partition compilestrategies. For use in dc_shell-t (Tcl mode ofdc_shell) only.

Default value for this variable is compile.

acs_verilog_extensionsSpecifies the file endings of files analyzed as Verilogsource code by the acs_read_hdl command.

Default value for this variable is ".v".

acs_vhdl_extensionsSpecifies the file endings of files analyzed as VHDLsource code by the acs_read_hdl command.

Default value for this variable is ".vhd".

acs_work_dirSpecifies the root of the Automated Chip Synthesisproject directory. For use in dc_shell-t (Tcl mode ofdc_shell) only.

Default value for this variable is the current workingdirectory.

auto_link_disableSpecifies whether the code to perform an auto_linkduring any Design Compiler command should bedisabled.


Synthesis Variables


auto_link_optionsSpecifies the link command options to be used whenlink is invoked automatically by various DesignCompiler and DFT Compiler commands (forexample, create_schematic and compile).

Default value for this variable is -all.

auto_wire_load_selectionTurns the automatic selection of the wire load modelon or off.


bc_add_io_traceInserts additional code to write out I/O debugginginformation during the RTL simulation run.


bc_allow_shared_memoriesEnables sharing of memories between processes whenusing Behavioral Compiler.


bc_chain_read_into_memEnables Behavioral Compiler to chain input readsdirectly into a memory even if the inputs to thememory have been specified as non-chainable.


bc_chain_read_into_operEnables Behavioral Compiler to chain input readsdirectly into a operation even if the inputs to theoperation have been specified as non-chainable.


bc_constrain_signal_memoriesDetermines whether shared memory accesses arescheduled as signals or variables.



162


bc_detect_array_accessesDetermines whether precedences (dependency-relatedconstraints) between nonconflicting pairs of arrayaccesses to the same register file are automaticallyignored.


bc_detect_memory_accessesDetermines whether precedences (dependency relatedconstraints) between nonconflicting pairs of memoryaccesses are automatically ignored.


bc_enable_analysis_infoEnables the generation of BCView analysisinformation.


bc_enable_chainingEnables chaining of synthetic library operations.


bc_enable_multi_cycleEnables inference of multicycle synthetic libraryoperations.


bc_enable_speculative_executionControls whether speculative execution is enabled.


bc_estimate_mux_inputSpecifies the number of mux inputs forbc_time_design to use when estimating thecombinational delay through muxes introduced byresource sharing.


Synthesis Variables


bc_estimate_timing_effortSpecifies the level of timing estimation effort to beused in addition to the operator timing performed bybc_time_design.

Default value for this variable is high.

bc_fsm_coding_styleControls the state assignment for the controllergenerated by Behavioral Compiler.

Default value for this variable is one_hot.

bc_group_eql_logicControls whether Behavioral Compiler groups alllogic gates for the equal/non-equal operation.


bc_group_index_logicControls whether Behavioral Compiler groups alllogic gates for the array indexing operation.


bc_report_filterContains a string to be used to filter the operators andvariables for report_schedule -op and report_schedule-var.


bc_time_all_sequential_op_bindingsControls the delay calculation for operations mappedonto DW03_mult_n_stage.


bc_use_registerfilesSelects the array style.



164


bsd_max_in_switching_limitSpecifies the maximum number of design inputs thatmay switch simultaneously while generating inputDC parametric tests using the create_bsd_patternscommand.


bsd_max_out_switching_limitSpecifies the maximum number of design outputs thatmay switch simultaneously while generating outputDC parametric tests using the create_bsd_patternscommand.


bus_dimension_separator_styleSpecifies the style to use in naming an individual portmember, net member, or cell instance member of amulti-dimensional EDIF array or of a multi-dimensional Verilog or VHDL vector.

Default value for this variable is "][".

bus_extraction_styleSpecifies the style used to extract the base name of netarrays, port arrays, and cell instance arrays in EDIFfiles.

Default value for this variable is %s[%d:%d].

bus_inference_descending_sortSpecifies that the members of that port bus are to besorted in descending order rather than in ascendingorder.


bus_inference_styleSpecifies the pattern used to infer individual bits intoa port bus.


Synthesis Variables


bus_minus_styleControls the naming of individual members of bit-blasted port, instance, or net buses with negativeindices.

Default value for this variable is -%d.

bus_multiple_separator_styleDetermines the name of a multibit cell whichimplements bits that do not form a range.

Default value for this variable is ,.

bus_naming_styleSpecifies the style to use in naming an individual portmember, net member, or cell instance member of anEDIF array or of a Verilog or VHDL vector.

Default value for this variable is %s[%d].

bus_range_separator_styleSpecifies the style to use in naming a net connected tothe wire end of a ripper in the EDIF file.

Default value for this variable is :.

cache_dir_chmod_octalSpecifies the value of the mode bits for created cachedirectories.


cache_file_chmod_octalSpecifies the value of the mode bits for created cachefiles.


cache_readSpecifies a list of directories that contain cache filesthat will be read from whenever a cache entry isneeded.

Default value for this variable is {"remote/dac1","/remote/dac1"}.


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cache_read_infoSpecifies whether an informational message will beprinted each time a cache element is read.


cache_writeSpecifies the directory where optimized andunoptimized synlib parts will be written, if they arenot already in the cache.

Default value for this variable is /remote/dac1.

cache_write_infoSpecifies whether an informational message will beprinted each time a cache element is written.


case_analysis_log_fileSpecifies the name of a log file generated duringpropagation of constant values, from case analysis orfrom nets tied to logic zero or logic one.


case_analysis_with_logic_constantsWhen true, enables constant propagation, even if adesign contains only logic constants.


change_names_dont_change_bus_membersControls how the change_names command modifiesthe names of bus members.


change_names_update_inst_treeDetermines whether the instance trees for all designsin dc_shell are updated whenever names change.


Synthesis Variables


check_error_listSpecifies the error codes that the check_errorcommand checks for.

Default value for this variable is EQN-16 EQN-18EQN-20.

collection_result_display_limitSets the maximum number of objects that can bedisplayed by any command that displays a collection.


command_log_fileSpecifies the name of the file to which a log of theinitial values of variables and commands executed iswritten. If the value is an empty string, a commandlog file is not created.

Default value for this variable is /.command.log.

companySpecifies the name of the company where Synopsyssoftware is installed. The company name is displayedon the schematics.

Default value for this variable is Synopsys.

compatibility_versionSets the default behavior of the system to be the sameas the Synopsys software version specified in thevariable.

Default value for this variable is current release.

compile_assume_fully_decoded_three_state_bussesSpecifies whether the compile and translatecommands can assume that three-state busses arefully decoded.



168


compile_auto_ungroup_area_num_cellsDefines the minimum number of cells all subdesignsin a hierarchy must have so that compile-auto_ungroup area does not ungroup the hierarchy.


compile_auto_ungroup_delay_num_cellsDefines the minimum number of cells all subdesignsin the hierarchy must have so that the compile-auto_ungroup delay command does not ungroup thehierarchy.


compile_auto_ungroup_override_wlmSpecifies whether the compiler considers a cellinstance for automatic ungrouping, if the cell's wireload model differs from that of its parent.


compile_automatic_clock_phase_inferenceSpecifies the method used to determine clock phaseduring sequential mapping.

Default value for this variable is strict.

compile_checkpoint_cpu_intervalSpecifies a time, in minutes, to be used as the intervalbetween each automatic checkpoint.

Default value for this variable is 0.0.

compile_checkpoint_filenameSpecifies the name of the file to which the databasecontaining all hierarchy of the checkpointed design isto be written.

Default value for this variable is ./CHECKPOINT.db.

Synthesis Variables


compile_checkpoint_phasesDetermines whether checkpoints are generated duringexecution of the compile command.


compile_checkpoint_pre_area_filenameSpecifies the name of the file to which the .db filecontaining all hierarchy of checkpointed design iswritten before the Area-Recovery phase.

Default value for this variable is./CHECKPOINT_PRE_AREA.db.

compile_checkpoint_pre_delay_filenameSpecifies the name of the file to which the databasecontaining all hierarchy of the checkpointed design isto be written before the delay optimization phase.

Default value for this variable is./CHECKPOINT_PRE_DELAY.db.

compile_checkpoint_pre_drc1_filenameSpecifies the name of the file to which the databasecontaining all hierarchy of the checkpointed design iswritten before Design Rule Fixing Phase 1.

Default value for this variable is./CHECKPOINT_PRE_DRC1.db.

compile_checkpoint_pre_drc2_filenameSpecifies the name of the file to which the databasecontaining all hierarchy of the checkpointed design iswritten before Design Rule Fixing Phase 2.

Default value for this variable is./CHECKPOINT_PRE_DRC2.db.


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compile_cpu_limitSpecifies a time, in minutes, to be used as the limit forthe amount of time to be spent in the phases afterstructuring and mapping. Optimization cancels whenthe limit is reached.


compile_create_mux_op_hierarchyControls whether MUX_OP implementations havetheir own level of hierarchy.


compile_create_wire_load_tableControls the type of wire load model generated by thecreate_wire_load command.


compile_delete_unloaded_sequential_cellsControls whether the compile command deletesunloaded sequential cells.


compile_disable_hierarchical_inverter_optControls whether inverters can be moved acrosshierarchical boundaries during boundaryoptimization.


compile_dont_touch_annotated_cell_during_inplace_opt

Controls whether cells that have annotated delays canbe optimized.


Synthesis Variables


compile_dont_use_dedicated_scanoutControls whether test-ready compile (compile -scan ),and subsequent compiles, use a scan cell's dedicatedscan-out pin for functional connections.


compile_dw_simple_modeThis variable is for use only with theset_simple_compile_mode command. Controlswhether DesignWare parts are compiled in simplecompile mode.


compile_fast_optimizationControls whether fast algorithms are used in lieu ofthe default algorithms, for delay and areaoptimization.

Default value for this variable is true in low andmedium effort, false in high effort.

compile_fix_cell_degradationControls whether the algorithms for fixing celldegradation violation are activated.


compile_hold_reduce_cell_countControls whether the logic used to fix hold timeviolations is selected based on minimum cell count orminimum area.


compile_implementation_selectionControls whether the compile command reevaluatesthe current implementation of a synthetic moduleduring optimization.



172


compile_instance_name_prefixSpecifies the prefix used in generating cell instancenames when compile is executed.

Default value for this variable is U.

compile_instance_name_suffixSpecifies the suffix used for generating cell instancenames when compile is executed.


compile_log_formatControls the format of the columns to be displayedduring the mapping phases of compile andreoptimize_design.

Default value for this variable is "%elap_time %area%wns %tns %drc %endpoint".

compile_mux_no_boundary_optimizationControls whether the compile command performsboundary optimization on MUX_OPimplementations.


compile_negative_logic_methodologySpecifies the logic value connected to floating inputsby the compile and translate commands.


compile_new_Boolean_structureControls which Boolean structure optimizationalgorithm is used.


compile_new_optimizationControls which optimization algorithms DesignCompiler uses.


Synthesis Variables


compile_no_new_cells_at_top_levelControls whether the compile command adds newcells to the top-level design.


compile_power_opto_onlyEnables or disables power optimization in thepresence of timing violations during incrementalcompile.


compile_preserve_subdesign_interfacesControls whether the compile command preserves thesubdesign interface.


compile_retime_license_behaviorControls how the compile command behaves whenthe optimize_registers or balance_registers attributesare set on a design or parts of a design and therequired license(s) (BOA-BRT or DC-Expert) are notavailable immediately.

Default value for this variable is wait.

compile_seqmap_enable_output_inversionControls whether the compile command allowssequential elements to have their output phaseinverted.

Default value for this variable is asynchronous set andasynchronous reset sequential cells..

compile_sequential_area_recoveryControls whether the compile command tries toreduce area by remapping sequential elements.



174


compile_simple_mode_block_effortSpecifies the map effort value for compiling the lowerlevel blocks in simple compile mode.

Default value for this variable is none.

compile_top_acs_partitionControls whether the compile -top command onlyfixes all violations that cross top-level partitions.


compile_top_all_pathsControls whether the compile -top command fixes allviolations in the design, or only those that cross top-level hierarchical boundaries.


compile_update_annotated_delays_during_inplace_opt

Controls whether compile -in_place can updateannotated delay values in the neighborhood ofswapped cells. It has no effect for reoptimize_designand physopt, which always update annotated delayvalues.


compile_use_fast_delay_modeSelects the algorithm used for delay calculationswhen using the CMOS2 or nonlinear delay models.


compile_use_low_timing_effortControls the tradeoff between runtime and accuracyfor delay calculations when using technology librariesin which the input transition time affects the outputtransition time.


Synthesis Variables


context_check_statusReports whether the context_check mode is enabled(read-only).


cps_default_spSpecifies the default static probability value to be usedby Power Compiler for modeling switching activity.


cps_default_trSpecifies the default toggle rate value to be used byPower Compiler for modeling switching activity.


create_clock_no_input_delayAffects delay propagation characteristics of clocksources created using create_clock.


current_designSpecifies the design being worked on. This variable isused by most of the Synopsys commands.


dc_shell_modeReports the mode of the current dc_shell session.

Default value for this variable is default or tcl.

default_input_delaySpecifies the global default input delay value to beused for environment propagation.



176


default_name_rulesContains the name of a name_rule to be used as adefault by change_names if a name_rule is notspecified using the -rules name_rules option.


default_output_delaySpecifies the global default output delay value to beused for environment propagation.


default_port_connection_classContains the value of the connection class to beassigned to ports that do not have a connection classassigned to them.

Default value for this variable is universal.

default_schematic_optionsSpecifies options to use when schematics aregenerated.

Default value for this variable is -size infinite.

design_library_fileSpecifies the name of a file that contains designlibrary mappings.

Default value for this variable is".synopsys_vss.setup".

designerSpecifies the name of the current user.


disable_auto_time_borrowDetermines whether the report_timing command andother commands will use automatic time borrowing.


Synthesis Variables


disable_case_analysisWhen true, disables constant propagation from bothlogic constants and set_case_analysis commandconstants.


disable_library_transition_degradationControls whether the transition degradation table isused to determine the net transition time.


do_operand_isolationEnables or disables automatic operand isolation bythe Pragma or GTECH methods, for a design.


dpcm_arc_sense_mappingControls whether Design Compiler maps half unatearcs to preset and clear arcs for sequential cells.


dpcm_debuglevelDetermines the level of debugging for DesignCompiler.


dpcm_functionscopeControls how DPCM determines the FunctionalModevalue when doing timing calculations.

Default value for this variable is global.

dpcm_levelControls the mode used by DPCM for timingcalculations.

Default value for this variable is performance.


178


dpcm_librariesSpecifies the libraries of the link_path that use DPCMdelay calculation.


dpcm_rulepathSpecifies a list of paths, similar to a search path, forlocating the DPCM main rule.


dpcm_rulespathLocates the DPCM subrules when provided a list ofpaths, the list being similar to a search path.

Default value for this variable is {}.

dpcm_slewlimitDetermines Design Compiler behavior when input pinslew exceeds library limits.


dpcm_tablepathSpecifies a list of paths, similar to a search path, forlocating the DPCM tables.


dpcm_temperaturescopeControls whether DPCM requests Temperature foreach delay calculation.


dpcm_versionSpecifies the version of the API used by the DPCMdelay calculation.

Default value for this variable is IEEE-P1481.

Synthesis Variables


dpcm_voltagescopeControls whether DPCM requests RailVoltage valuesfor every delay calculation.


dpcm_wireloadscopeControls whether DPCM requests WireLoadModelvalues for every delay calculation.


duplicate_portsSpecifies whether ports are to be drawn on every sheetfor which an input or output signal appears.


dw_prefer_mc_insideEnables Synopsys Module Compiler to generatearithmetic DesignWare parts.


echo_include_commandsControls whether the contents of a script file is printedas it executes.


edifin_autoconnect_offpageconnectorsControls whether the EDIF reader can input a filecontaining an off-page connector and a port with thesame name.


edifin_autoconnect_portsControls whether the EDIF reader connects a port to anet with the same name (if there is one), even if thereis no explicit connection statement.



180


edifin_dc_script_flagControls whether the EDIF reader ignores commentsin the input file, or parses them to look for DesignCompiler commands.


edifin_delete_empty_cellsControls whether the EDIF reader deletes empty cellswhen reading in files.


edifin_delete_ripper_cellsControls whether the EDIF reader deletes designs ofcellType RIPPER when reading in EDIF files.


edifin_ground_net_nameSpecifies EDIF ground nets.


edifin_ground_net_property_nameSpecifies EDIF ground nets.


edifin_ground_net_property_valueSpecifies EDIF ground nets.


edifin_ground_port_nameSpecifies EDIF ground ports.


edifin_instance_property_nameSpecifies the EDIF property used to determine thevalue of the cell_property attribute on a cell.


Synthesis Variables


edifin_lib_in_osc_symbolSpecifies the name of the input off-sheet connectorsymbol in the EDIF symbol library.


edifin_lib_in_port_symbolSpecifies the name of the input port symbol in theEDIF symbol library.


edifin_lib_inout_osc_symbolSpecifies the name of the input/output off-sheetconnector symbol in the EDIF symbol library.


edifin_lib_inout_port_symbolSpecifies the name of the input/output port symbol inthe EDIF symbol library.


edifin_lib_logic_0_symbolSpecifies the name of the ground symbol in the EDIFsymbol library.


edifin_lib_logic_1_symbolSpecifies the name of the power symbol in the EDIFsymbol library.


edifin_lib_mentor_netcon_symbolSpecifies the name of the Mentor $netcon symbol inthe EDIF symbol library.



182


edifin_lib_out_osc_symbolSpecifies the name of the output off-sheet connectorsymbol in the EDIF symbol library.


edifin_lib_out_port_symbolSpecifies the name of the output port symbol in theEDIF symbol library.


edifin_lib_ripper_bits_propertySpecifies the ripped_bits_property attribute of theripper symbol (which is specified by theedifin_lib_ripper_cell_name variable).


edifin_lib_ripper_bus_endSpecifies the ripped_pin attribute of the ripper symbol(which is specified by theedifing_lib_ripper_cell_name variable).


edifin_lib_ripper_cell_nameSpecifies the name of the ripper symbol in the EDIFsymbol library.


edifin_lib_ripper_view_nameSpecifies the view of the ripper cell (as specified bythe edifin_lib_ripper_cell_name variable) used in theSynopsys symbol library.


edifin_lib_route_gridSpecifies the size of the route grid of the library.


Synthesis Variables


edifin_lib_templatesSpecifies the sheet sizes available in a library.


edifin_portinstance_disabled_property_nameSpecifies the EDIF property used to determine thevalue of the disabled attribute on a pin.


edifin_portinstance_disabled_property_valueControls whether the disabled attribute should beplaced on the pin of the cell by specifying the requiredvalue of the corresponding EDIF property.


edifin_portinstance_property_nameSpecifies the EDIF property used to determine thevalue of the pin_properties attribute on a pin.


edifin_power_net_nameSpecifies EDIF power nets.


edifin_power_net_property_nameSpecifies EDIF power nets.


edifin_power_net_property_valueSpecifies EDIF power nets.


edifin_power_port_nameSpecifies EDIF power ports.



184


edifin_use_identifier_in_renameControls whether objects are named using theidentifier value or the name value.


edifin_view_identifier_property_nameAllows multiple views (representations) of a cell to becreated in the Synopsys database.


edifout_dc_script_flagControls whether the EDIF writer embeds commentscontaining Design Compiler commands into the EDIFfile.


edifout_design_nameControls the identifier in the design construct writtenat the end of EDIF files.

Default value for this variable is Synopsys_edif.

edifout_designs_library_nameSpecifies the name that is given to the EDIF libraryconstruct that contains the cell constructs for thedesigns being written.

Default value for this variable is DESIGNS.

edifout_display_instance_namesControls whether cell names are displayed in theschematic.


edifout_display_net_namesControls whether net names are displayed in theschematic.


Synthesis Variables


edifout_externalControls whether the EDIF output contains completesymbol definitions or only interface descriptions.


edifout_external_graphic_view_nameSpecifies the name of an EDIF view used in a librarycontained in an external construct in a schematicEDIF file.

Default value for this variable isGraphic_representation.

edifout_external_netlist_view_nameSpecifies the name of an EDIF view used in a librarycontained in an external construct in a netlist EDIFfile.

Default value for this variable isNetlist_representation.

edifout_external_schematic_view_nameSpecifies the name of an EDIF view used in a librarycontained in an external construct in a schematicEDIF file.

Default value for this variable isSchematic_representation.

edifout_ground_nameSpecifies the name used by the EDIF writer for theSynopsys built-in ground cell.

Default value for this variable is logic_0.

edifout_ground_net_nameSpecifies the name of the ground net.



186


edifout_ground_net_property_nameSpecifies the name of the property used to identifyground nets.


edifout_ground_net_property_valueSpecifies the value of the property used to identifyground nets.


edifout_ground_pin_nameSpecifies the name of the ground cell pin.

Default value for this variable is logic_0_pin.

edifout_ground_port_nameSpecifies the name of the ground port.

Default value for this variable is GND.

edifout_instance_property_nameSpecifies the name of the EDIF property used torepresent the value of the cell_property attribute on anEDIF instance.


edifout_instantiate_portsControls whether symbol constructs for ports and off-sheet connectors are included in a library (or external)construct in an EDIF schematic.


edifout_library_graphic_view_nameSpecifies the name of an EDIF view used in a librarycontained in a library construct (not an externalconstruct) in a schematic EDIF file.

Default value for this variable isGraphic_representation.

Synthesis Variables


edifout_library_netlist_view_nameSpecifies the name of an EDIF view used in a librarycontained in a library construct (not an externalconstruct) in a netlist EDIF file.

Default value for this variable isNetlist_representation.

edifout_library_schematic_view_nameSpecifies the name of an EDIF view used in a librarycontained in a library construct (not an externalconstruct) in a schematic EDIF file.

Default value for this variable isSchematic_representation.

edifout_merge_librariesControls whether the EDIF writer writes all cells foran EDIF file in the same library.


edifout_multidimension_arraysControls whether the EDIF writer can represent a busas a multi-dimensional array.


edifout_name_oscs_different_from_portsControls whether each off-sheet connector that isconnected to a port is given a different name from theport in the descriptions of designs written in EDIFformat.


edifout_name_rippers_same_as_wiresControls whether bus ripper cell instances are namedbased on the order they are created during schematicgeneration or based on the names of the extractedwires.



188


edifout_netlist_onlyControls whether the EDIF writer generates both anetlist and a schematic, or a netlist only.


edifout_no_arrayControls whether the EDIF writer uses arrayconstructs.


edifout_numerical_array_membersControls the method used to generate the array indexvalues.


edifout_pin_direction_in_valueIncludes an EDIF property with the same name asedifout_pin_direction_property_name, and value thesame as this variable string, on input pins.


edifout_pin_direction_inout_valueIncludes an EDIF property with the same name asedifout_pin_direction_property_name, and value thesame as this variable, on input/output pins.


edifout_pin_direction_out_valueIncludes an EDIF property with the same name asedifout_pin_direction_property_name, and value thesame as this variable, on output pins.


edifout_pin_direction_property_nameSpecifies the name of the EDIF pin direction property.


Synthesis Variables


edifout_pin_name_property_nameIncludes on pins an EDIF property with the samename as this variable string, and value the same as thepin name.


edifout_portinstance_disabled_property_nameCreates in the portInstance construct a property withthe same name as this variable string and a value thatis the same as that ofedifout_portinstance_disabled_property_value, if thepin of a cell instance has the disabled attribute on it.


edifout_portinstance_disabled_property_valueCreates in the portInstance construct a property withthe same name asedifout_portinstance_disabled_property_name andthe same value as this variable string, if the pin of acell instance has the disabled attribute on it.


edifout_portinstance_property_nameCreates in the portInstance construct a property withthe same name as this variable string and the samevalue as the pin_properties attribute, if thepin_properties attribute is on the pin of a cell instance.


edifout_power_and_ground_representationDetermines power and ground representations inEDIF files.

Default value for this variable is cell.

edifout_power_nameSpecifies the name used by the EDIF writer for theSynopsys built-in power cell.

Default value for this variable is logic_1.


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edifout_power_net_nameSpecifies the name of the power net.


edifout_power_net_property_nameSpecifies the name of the property used to identifypower nets.


edifout_power_net_property_valueSpecifies the value of the property used to identifypower nets.


edifout_power_pin_nameSpecifies the name of the power cell pin.

Default value for this variable is logic_1_pin.

edifout_power_port_nameSpecifies the name given to the power port.

Default value for this variable is VDD.

edifout_skip_port_implementationsControls whether the EDIF writer writesportImplementation constructs for ports in thecontents constructs of EDIF schematics.


edifout_target_systemSpecfies the target system for the generated EDIFfiles.


edifout_top_level_symbolControls whether the EDIF writer writes the top-levelsymbol in EDIF schematic files.


Synthesis Variables


edifout_translate_originSpecifies the origin for the EDIF schematics.


edifout_unused_property_valueSpecifies the property value to be output for unusedpins.


edifout_write_attributesControls whether the EDIF writer embeds commentscontaining Design Compiler attribute definitions intothe EDIF file.


edifout_write_constraintsControls whether the EDIF writer embeds commentscontaining Design Compiler constraint commandsinto the EDIF file.


edifout_write_properties_listSpecifies a list of library, cell, or port properties towrite into the EDIF description.


enable_instances_in_report_netEnables report_net to report on instances in thecurrent design.


When true, long reports are displayed one page at atime (similar to the UNIX more command).Commands affected by this variable include list, help,and the report commands.



192


enable_recovery_removal_arcsControls whether Design Compiler accepts recoveryand removal arcs that are specified in the technologylibrary.


enable_slew_degradationDetermines whether the transition degradation istaken into account for nets with physical information.


equationout_and_signSpecifies the and sign to use when writing a design inequation format.

Default value for this variable is *.

equationout_or_signSpecifies the or sign to use when writing a design inequation format.

Default value for this variable is +.

equationout_postfix_negationControls whether a single quote (`) or an exclamationmark (!) is used as the negation operator.


exit_delete_filename_log_fileControls whether the file specified by the variablefilename_log_file is deleted after design_analyzer ordc_shell exits normally.


filename_log_fileSpecifies the name of the filename log file to be usedin case a fatal error occurs during execution ofdesign_analyzer or dc_shell.

Default value for this variable is filenames.log.

Synthesis Variables


find_converts_name_listsControls whether the find command converts thename_list string to a list of strings before searchingfor design objects.


fsm_auto_inferringDetermines whether or not to automatically extractfinite state machine during the compile.


fsm_enable_state_minimizationDetermines whether or not the state minimization isperformed for all finite state machines (FSMs) in thedesign.


fsm_export_formality_state_infoDetermines whether or not state machine encodinginformation is exported into the files that will be usedby Formality.


gen_bussing_exact_implicitControls whether schematics generated using thecreate_schematic -implicit command should containimplicit bus names instead of bus rippers.


gen_cell_pin_name_separatorSpecifies the character used to separate cell namesand pin names in the bus names generated by thecreate_schematic command.

Default value for this variable is /.


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gen_create_netlist_bussesControls whether create_schematic creates netlistbuses whenever it creates buses on the schematic.


gen_dont_show_single_bit_bussesControls whether single-bit buses are generated in theschematic.


gen_match_ripper_wire_widthsControls whether the create_schematic commandgenerates rippers whose width always equals thewidth of the ripped net.


gen_max_compound_name_lengthControls the maximum length of compound names ofbus bundles (for the create_schematic -sgecommand).


gen_max_ports_on_symbol_sideSpecifies the maximum allowed size of a symbolcreated by create_schematic.


gen_open_name_postfixSpecifies the postfix to be used by create_schematic-sge when creating placeholder net names forunconnected pins.


gen_open_name_prefixSpecifies the prefix to be used by create_schematic-sge when creating placeholder net names forunconnected pins.

Default value for this variable is Open.

Synthesis Variables


gen_show_created_bussesControls whether a message is printed out every timea schematic bus is created from cell pins for which noequivalent net bus exists in the netlist.


gen_show_created_symbolsControls whether create_schematic prints a warningmessage every time it generates a new symbol for acell because an appropriate symbol could not befound in the symbol libraries.


gen_single_osc_per_nameControls whether more than one off-sheet connectorwith any particular name is drawn on any schematicsheet.


generic_symbol_librarySpecifies the generic symbol library used forschematics.

Default value for this variable is generic.sdb.

hdl_keep_licensesControls whether HDL licenses that are checked outremain checked out throughout the dc_shell session orare released after use.


hdl_naming_thresholdDetermines the maximum character length that aparameter can have in order to be included in thedesign name.



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hdl_preferred_licenseSelects an hdl license to check out, if none is currentlychecked out.


hdlin_allow_mixed_blocking_and_nonblockingControls whether blocking and nonblockingassignments to the same variable are considered anerror. Effective only for Presto HDL Compiler andVerilog.


hdlin_array_instance_naming_styleSets the naming style for Verilog arrays of instances.

Default value for this variable is %s[%d].

hdlin_auto_full_caseControls whether HDL Compiler attempts to detectfull-case statements.


hdlin_auto_netlist_readerControls whether the read -f verilog commandattempts to automatically determine the type of inputfile and select the most efficient reader.


hdlin_auto_parallel_case_earlyControls whether HDL Compiler tries to auto-detecteasy to find parallel cases earlier in the elaboratephase.


hdlin_auto_save_templatesControls whether HDL designs containing parametersare read in as templates.


Synthesis Variables


hdlin_black_box_pin_hdlc_styleControls whether to follow HDL Compiler pinnaming style when performing black box moduleinstantiation.


hdlin_build_selectop_for_var_indexControls whether the Presto HDL Compilerimplements variable indexing expressions using aMUX_OP or SELECT_OPs with additional decodelogic.


hdlin_call_stack_depthLimits the depth of nested or recursive function calls.


hdlin_check_no_latchControls whether a warning message is issued if alatch is inferred from a design.


hdlin_check_user_full_caseCauses a warning to be issued if the full_case pragmais placed on a case statement that is not full.


hdlin_check_user_parallel_caseCauses a warning to be issued if the parallel_casepragma is placed on a case statement that is notparallel.


hdlin_compare_const_with_gatesSpecifies whether comparisons with constants areimplemented with gates or synthetic operators.Effective only for Presto HDL Compiler.



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hdlin_compare_eq_with_gatesSpecifies whether equality comparisons areimplemented with gates or synthetic operators.Effective only for Presto HDL Compiler.


hdlin_decoder_max_input_widthControls the circumstances in which the Presto HDLCompiler attempts to use a decoder to implement aseries of comparisons involving an expression and anumber of constants.


hdlin_decoder_min_input_widthControls the circumstances in which the Presto HDLCompiler attempts to use a decoder to implement aseries of comparisons involving an expression and anumber of constants.


hdlin_decoder_min_use_percentageControls the circumstances in which the Presto HDLcompiler attempts to use a decoder to implement aseries of comparisons involving an expression and anumber of constants.


hdlin_dont_check_param_widthControls whether HDL Compiler checks that aVerilog parameter is large enough to contain the valueassigned to it.


hdlin_dont_infer_mux_for_resource_sharingControls whether HDL Compiler infers a MUX_OPfor a signal/variable assigned in a case statement.


Synthesis Variables


hdlin_dyn_array_bnd_checkControls whether logic is added to check the validityof array indices.


hdlin_enable_analysis_infoControls whether RTL Analyzer creates analysisinformation for designs processed by subsequentdc_shell commands.


hdlin_enable_prestoControls whether the two commands read and analyzeuse the Presto HDL Compiler for Verilog input files.


hdlin_enable_rtldrc_infoControls whether RTL TestDRC creates file name andline number information for HDL constructs andinstances for designs processed by subsequentdc_shell commands.


hdlin_enable_vppEnables Verilog Preprocessing (VPP).


hdlin_escape_special_namesCauses a backslash '\' character to be prepended toVerilog names that contain special characters.


hdlin_ff_always_async_set_resetControls whether HDL Compiler checks and reportsasynchronous set and reset conditions of flip-flops.



200


hdlin_ff_always_sync_set_resetControls whether every constant 0 loaded on a flip-flop under the clock event is used for synchronousreset, and every constant 1 loaded on a flip-flop underthe clock event is used for synchronous set.


hdlin_generate_naming_styleSpecifies the naming style for generated designinstances.

Default value for this variable is "%s_%d".

hdlin_generate_separator_styleSpecifies the separator string for instances generatedin multiple-nested loops.

Default value for this variable is "__".

hdlin_group_selectorsEnables grouping of single-bit selectors into multi-bitselectors.


hdlin_hide_resource_line_numbersControls whether (V)HDL Compiler appends theHDL source line number to the inferred cell's namewhen inferring a synthetic library or DesignWare part.


hdlin_infer_block_local_latchesControls whether latches are allowed to be inferredfor function- and task-scope variables.


Synthesis Variables


hdlin_infer_comparatorsControls whether the Presto HDL compiler willattempt to infer 6-output comparators. A 6-outputcomparator may save area when there are severaldifferent types of comparisons between the same twoexpressions in the design.


hdlin_infer_decodersControls whether the Presto HDL compiler attemptsto infer synthetic decoders. When an expression iscompared against a series of different constants, thatset of comparisons can optionally be implementedusing a decoder.


hdlin_infer_enumerated_typesControls whether the Presto HDL Compiler tries toinfer variables that have enumerated types.


hdlin_infer_fsmControls whether the compiler automatically detectsfinite state machines (FSMs) in the HDL code in thePresto HDL Compiler flow.


hdlin_infer_function_local_latchesControls whether the Presto HDL Compiler inferslatches inside functions and tasks.


hdlin_infer_multibitSpecifies inference of multibit components for anentire design.

Default value for this variable is default_none.


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hdlin_infer_muxDetermines whether and how HDL Compiler infers aMUX_OP.


hdlin_keep_feedbackRemoves (when false) all flip-flop feedback loops.


hdlin_keep_inv_feedbackWhen true, retains all inverted flip-flop feedbackloops.


hdlin_latch_always_async_set_resetUses, for asynchronous reset, every constant 0 loadedon a latch, and uses, for asynchronous set, everyconstant 1 loaded on a latch, for a designsubsequently analyzed.


hdlin_link_designControls whether the Presto HDL Compiler links adesign as it is elaborated.


hdlin_loop_invariant_code_motionControls whether the Presto HDL Compiler attemptsto move expressions calculated inside a loop to alocation outside the loop, when it is safe to do so.


hdlin_map_to_entityDetermines whether the Presto HDL Compiler willsupport map_to_entity synopsys pragmas.


Synthesis Variables


hdlin_map_to_moduleDetermines whether the Presto HDL Compiler willsupport map_to_module synopsys pragmas.


hdlin_map_to_operatorDetermines whether the Presto HDL Compiler willsupport map_to_operator synopsys pragmas.


hdlin_merge_nested_conditional_statementsInfers a SELECT_OP (a generic logic componentinferred for conditional statements) for each if or casestatement in a nested conditional construct. Effectiveonly in original HDLC flow, not in Presto.


hdlin_module_arch_name_splittingControls whether Presto HDL Compiler recognizes aspecial format of Verilog module names, whichallows users to specify both a module and animplementation architecture.


hdlin_mux_oversize_ratioPrevents inference of a sparse multiplexer, when theratio of MUX_OP data inputs to unique data inputs isabove the hdlin_mux_oversize_ratio.


hdlin_mux_size_limitLimits the number of inputs of an inferredmultiplexer.



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hdlin_mux_size_minSets the lower bound for the number of inputsrequired to infer a multiplexer.


hdlin_netlist_transformDetermines whether the Presto HDL Compilerperforms netlist transformation steps duringelaboration.


hdlin_no_adder_feedthroughsControls whether Presto HDL Compiler performsfeed-through optimizations on adders or subtractors.


hdlin_no_sequential_mappingDetermines whether Presto HDL Compiler performsthe sequential mapping step.


hdlin_one_hot_one_cold_onDetermines whether to use one_hot and one_coldattributes to simplify circuits.


hdlin_optimize_array_referencesEnables the optimization of array references whenthere are constants in the index expression.


hdlin_optimize_case_defaultEnables HDL Compiler to optimize the control logicfor the default branch of a case statement.


Synthesis Variables


hdlin_optimize_enum_typesControls whether the Presto HDL compiler attemptsto simplify designs by using the information thatcertain variables have an enumerated type.


hdlin_optimize_shift_expressionsEnables the optimizing of shift expressions when theinput and output widths differ.


hdlin_preserve_vpp_filesControls deletion of files with pp extension created byVerilog Preprocessing.


hdlin_print_modfilesControls the printing of informational messageswhenever modules are read from or written to diskduring Presto HDL Compiler activities.


hdlin_prohibit_nontri_multiple_driversControls whether the Presto HDL compiler issues anerror, or only a warning, when it finds multiple driversof a net.


hdlin_redundancy_eliminationControls whether the Presto HDL Compiler applies aseries of transformations to remove redundantcomputations from a design.



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hdlin_reg_report_lengthSets the maximum length, in characters, of theBoolean formulas reported whenhdlin_report_inferred_modules is set to verbose.


hdlin_register_report_depthControls the effort the Presto HDL Compiler puts intothe accuracy of the sequential inference report.


hdlin_replace_syntheticProcesses synthetic library parts in HDL designsduring the read and elaborate commands. Actual gate-level implementations are inserted during the readcommand.


hdlin_report_enumerated_typesControls whether the Presto HDL Compiler prints areport of the variables in a design that are known tohave an enumerated type. This includes both user-declared and automatically detected enumeratedtypes.


hdlin_report_fsmControls whether the compiler reports finite statemachines (FSMs) discovered in the HDL code in thePresto HDL Compiler flow.


hdlin_report_inferred_modulesGenerates a brief report for inferred latches, flip-flops,three-state, and multiplexer devices.


Synthesis Variables


hdlin_report_mux_opDetermines whether mux_op information is reportedduring HDL Compiler activity.


hdlin_report_syn_cellDetermines whether the Presto HDL Compiler printsa report summary of synthetic cells.


hdlin_report_tri_stateControls whether the Presto HDL Compiler prints areport of three-state buffers inferred. Three-statebuffers are inferred when a variable is assigned to thethree-state value in the design.


hdlin_selector_simplify_effortControls the effort the Presto HDL Compiler puts intosimplifying selectors with constant inputs.


hdlin_seqmap_search_depthControls how deep Presto HDL Compiler looks forsets and resets of flip-flops and latches.


hdlin_share_all_operatorsControls whether the Presto HDL compiler attemptsto share all identical arithmetic expressions or defersthe sharing decision to the compile command.


hdlin_subprogram_default_valuesDetermines which value the compiler will use as thedefault value for variables, 'LEFT of its type or 0s.



208


hdlin_translate_off_onIgnores the translate_off and translate_on directives,when disabled by setting the value to false.


hdlin_translate_off_skip_textCauses VHDL Compiler to treat as comments the textbetween the translation directives translate_off andtranslate_on.


hdlin_unsigned_integersControls whether the Presto HDL Compiler generatessigned arithmetic operators for signed operations.


hdlin_upcase_namesControls whether identifiers in the Verilog sourcecode are converted to uppercase letters or left in theiroriginal case.


hdlin_use_carry_inControls whether the Presto HDL Compiler attemptsto use the carry-in input of adders and subtracters, inconjunction with the hdlin_use_cin variable.


hdlin_use_syn_shifterMaps DesignWare shifter parts to shift operators inyour HDL code. When this variable is disabled (false,the default), a flattened implementation is supplied.


hdlin_verbose_cell_namingEnables/disables the verbose naming style of cells.


Synthesis Variables


hdlin_vhdl93_concatControls the concatenation behavior the compiler usesto conform to the VHDL '93 Standard or the '87Standard.


hdlin_vhdl_93Controls whether Presto-VHDL follows VHDL '93Standard or '87 Standard.


hdlin_vpp_temporary_directoryDetermines where to create intermediate files, whichVerilog preprocessing constructs.


hdlin_vrlg_stdControls whether Presto Verilog enforces Verilog1995 or Verilog 2000.


hdlin_warn_array_boundCauses warning messages to be issued or suppressedwhen the index of an array element is out of bounds.


hdlin_warn_implicit_wiresControls whether the compiler warns users aboutimplicitly declared wires.



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hdlin_warn_mixed_blocking_and_nonblockingControls whether warnings are issued when blockingand nonblocking assignments to the same variable arepresent. Effective only for Presto HDL compiler andVerilog and only if the variablehdlin_allow_mixed_blocking_and_nonblocking is setto true.


hdlin_warn_sens_listControls whether the Presto HDL Compiler issues awarning when it detects that a variable or signal in acombinational always block is read but does notappear in the sensitivity list.


hdlin_while_loop_iterationsPlaces an upper bound on the number of times a loopis unrolled (to prevent potential infinite loops).


hdlin_work_directorySpecifies the directory used to store analyzed Verilogmodules. Effective only for Presto HDL Compiler.

Default value for this variable is "./WORK".

hdlin_write_gtech_design_directorySpecifies the directory in which to place the RTLAnalyzer intermediate files.

Default value for this variable is ".".

hdlout_internal_bussesControls the way in which the write -format verilogcommand and the write -format vhdl command writeout internal bused nets by parsing the names of thenets.


Synthesis Variables


hier_dont_trace_ungroupDisables ungroup tracing set on the design with theungroup command.


high_fanout_net_pin_capacitanceSpecifies the pin capacitance used to compute theloading of high-fanout nets.


high_fanout_net_thresholdSpecifies the minimum number of loads for a net to beclassified as a high-fanout net.


hlo_disable_datapath_optimizationDisables built-in data-path optimization feature incompile.


hlo_ignore_prioritiesDetermines whether priorities set for syntheticimplementations are to be observed during resourcesharing and implementation selection under compile.


hlo_minimize_tree_delayDuring compile, enables tree height minimizationduring resource sharing, if the minimize_tree_delayattribute is not set.


hlo_resource_allocationSets the default resource sharing type to be used bythe compile command, if the resource_allocationattribute is not set.

Default value for this variable is constraint_driven.


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hlo_resource_implementationSets the default implementation selection type to beused by the compile command, if theresource_implementation attribute is not set.

Default value for this variable is use_fastest.

hlo_share_common_subexpressionsEnables (during compile) sharing of commonsubexpressions during resource sharing.


hlo_share_effortSets the relative amount of CPU time to be spent onresource sharing during compile.

Default value for this variable is low.

hlo_transform_constant_multiplicationReplaces, during elaborate command activity, allmultiplications that have one constant input, by aseries of shift, add, and subtract operations. Thedefault is false, meaning that the multiplications arenot replaced.


ilm_derive_keepoutEnables and disables automatic inference ofplacement and wiring keepouts for interface logicmodels (ILMs) in Physical Compiler.


insert_dft_clean_upCauses the insert_dft command to use area recoverytechniques to reduce the amount of test point logic.


Synthesis Variables


insert_test_design_naming_styleSpecifies how the insert_dft command names newdesigns created during the addition of test circuitry.

Default value for this variable is %s_test_%d.

lbo_cells_in_regionsPuts new cells at specific locations within a cluster.


lib_thresholds_per_libCauses tripPoint values in the Synopsys library tooverride user-specified values.


libgen_max_differencesSpecifies to the read_lib command the maximumnumber of differences to list between the v3.1 formatdescription of a library cell and its statetabledescription.

Default value for this variable is -1.

link_force_caseControls the case-sensitive or case-insensitivebehavior of the link command.

Default value for this variable is check_reference.

link_librarySpecifies the list of design files and libraries usedduring linking.

Default value for this variable is {"*"your_library.db}.

lsiin_net_name_prefixContains the prefix added to names assigned tounnamed nets within a design read in the LSI/NDLformat. Only alphanumeric characters and theunderscore are allowed in the string.

Default value for this variable is NET_.


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lsiout_inverter_cellPrevents the write -format lsi command from directlyconnecting logic zero or logic one to internal pins orports.


lsiout_upcaseConverts to uppercase all of the names withinLSI/NDL netlists.


ltl_obstruction_typeControls the routing blockage type for the namedobstructions, without route type being specified.

Default value for this variable is placement_only.

mentor_bidirect_valueSpecifies the value of the property that identifies thedesign's pins or primary ports as being bidirectional.

Default value for this variable is INOUT.

mentor_do_pathSpecifies a non-default directory that contains theNETED DO macros referenced by the write -f mentoroutput.


mentor_input_output_property_nameSpecifies the name of the property whose valuerepresents the direction of pins and primary ports ofthe design.

Default value for this variable is PINTYPE.

Synthesis Variables


mentor_input_valueSpecifies the value of the property that identifies inputpins or primary input ports. You can specify theproperty name using the variablementor_input_output_property_name.

Default value for this variable is IN.

mentor_logic_one_valueSpecifies the value of the property that identifies logicone nets. You can specify the name of the propertyusing the variablementor_logic_zero_one_property_name.

Default value for this variable is 1SF.

mentor_logic_zero_one_property_nameSpecifies the name of the property whose valuedetermines whether the net is connected to logic one(power) or logic zero (ground).

Default value for this variable is INIT.

mentor_logic_zero_valueSpecifies the value of the property that identifies logiczero nets. You can specify the property name usingthe variable mentor_logic_zero_one_property_name.

Default value for this variable is OSF.

mentor_output_valueSpecifies the value of the property that identifiesoutput pins or primary output ports. You can specifythe name of the property using the variablementor_primitive_property_name.

Default value for this variable is OUT.

mentor_primitive_property_nameSpecifies the name of the property placed on allautomatically generated symbols.

Default value for this variable is PRIMITIVE.


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mentor_primitive_property_valueSpecifies the value of the property placed on allautomatically generated symbols. You can specify thename of the property using the variablementor_primitive_property_name.

Default value for this variable is MODULE.

mentor_reference_property_nameSpecifies the name of the property that contains thereference name of every instance. The reference nameis the name of the cell of which this object is aninstantiation.

Default value for this variable is COMP.

mentor_search_pathCauses the write -f mentor command to add a NETEDSEARCH command to the beginning of an output file.This variable contains the list of directories to besearched for cells to be instantiated while executingthe NETED DO macro.


mentor_write_symbolsCauses the write -f mentor command to includesymbol (SYMED) information in the output file forall automatically generated symbols.


mgi_scratch_directorySpecifies a directory in which to store theintermediate files created by external generators. Bydefault, the scratch directory is set todesignware_generator in the current workingdirectory.

Default value for this variable isdesignware_generator.

Synthesis Variables


pdefout_full_path_nameControls the output PDEF file during the writing outof hierarchical designs.


pdefout_diff_originalUsed in conjunction with the option -new_cells_onlyof the command write_clusters.


physical_librarySpecifies the list of technology physical libraries ofcomponents used in physical synthesis.


pla_read_create_flip_flopAffects read -f pla and when set to true, enablesoutput register information in PLA files to be read inand stored, so that the output registers are instantiatedwithin the design.


plot_boxCauses a box to be drawn around the plot. The defaultis false.


plot_commandSpecifies the operating system command thatproduces a hard copy of the plot.

Default value for this variable is lpr -Plw -h.

plot_orientationSpecifies whether the schematic is vertical orhorizontal.

Default value for this variable is best_fit.


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plot_scale_factorSpecifies a scaling factor for the schematic.


plotter_maxxSpecifies the x coordinate of the upper right corner ofthe plot output device.


plotter_maxySpecifies the y coordinate of the upper right corner ofthe plot output device.


plotter_minxSpecifies the x coordinate of the lower left corner ofthe plot output device.


plotter_minySpecifies the y coordinate of the lower left corner ofthe plot output device.


port_complement_naming_styleDefines the convention the compile command uses torename ports complemented as a result of using theset_boundary_optimization command.

Default value for this variable is %s_BAR.

power_cg_flattenSpecifies to the ungroup command whether to flattenSynopsys clock-gating cells.


Synthesis Variables


power_do_not_size_icg_cellsWhen true, compile does not size the integrated clock-gating cells in the design to correct DRC violations,because doing so results in lower area and power. Thedefault is false.


power_hdlc_do_not_split_cg_cellsWhen true, elaborate does not split clock-gating cellsto limit their fanout.


power_keep_license_after_power_commandsAffects the amount of time a DesignPower license ischecked out during a dc_shell (Design Compiler)session.


power_preserve_rtl_hier_namesPreserves the hierarchy information of the RTLobjects in the RTL design.


power_rtl_saif_fileDefines for the rtl2saif command where to store theforward-annotation SAIF file, if you do not specifythe -output option.

Default value for this variable is power_rtl.saif.

power_sdpd_saif_fileDefines for the lib2saif command where to store theforward-annotation SAIF file, if you do not specifythe -output option.

Default value for this variable is power_sdpd.saif.


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rc_input_threshold_pct_fallSpecifies the threshold voltage that defines thestartpoint of the falling cell or net delay calculation.


rc_input_threshold_pct_riseSpecifies the threshold voltage that defines thestartpoint of the rising cell or net delay calculation.


rc_output_threshold_pct_fallSpecifies the threshold voltage that defines thestartpoint of the falling cell or net delay calculation.


rc_output_threshold_pct_riseSpecifies the threshold voltage that defines thestartpoint of the rising cell or net delay calculation.


rc_slew_derate_from_librarySpecifies the derating needed for the transition timesin the Synopsys library to match the transition timesbetween the characterization trip points.


rc_slew_lower_threshold_pct_fallSpecifies the threshold voltage that defines theendpoint of the falling slew calculation.


rc_slew_lower_threshold_pct_riseSpecifies the threshold voltage that defines thestartpoint of the rising slew calculation.


Synthesis Variables


rc_slew_upper_threshold_pct_fallSpecifies the threshold voltage that defines thestartpoint of the falling slew calculation.


rc_slew_upper_threshold_pct_riseSpecifies the threshold voltage that defines theendpoint of the rising slew calculation.


read_db_lib_warningsIndicates that warnings are to be printed while atechnology db library is being read in with the readcommand. When false (the default), no warnings aregiven.


read_name_mapping_nowarn_librariesSpecifies a list of libraries for which no warningmessages are to be issued by read -f edif -names_fileif the libraries are not found.


read_translate_msffIndicates (when true, the default) that master-slaveflip-flops (specified with the clocked_on_also syntax)are to be automatically translated to master-slavelatches. When false, both master and slave remainflip-flops.


reoptimize_design_changed_list_file_nameCreates a file in which to store the list of cells thatchanged and cells and nets that were added duringpost-layout or in-place optimization.



222


rtl_load_resistance_factorSpecifies a factor to be used by the set_rtl_loadcommand to calculate resistance values fromcapacitance values for RTL loads.


sdc_write_unambiguous_namesEnsures that cell, net, pin, lib_cell, and lib_pin namesthat are written to the SDC file are not ambiguous.The default value is true.


sdfout_allow_non_positive_constraintsWrites out PATHCONSTRAINT constructs withnonpositive (<= 0) constraint values.


sdfout_min_fall_cell_delaySpecifies the minimum non-back-annotated fall celldelay that the write_timing command writes to atiming file in SDF format.


sdfout_min_fall_net_delaySpecifies the minimum non-back-annotated fall netdelay that write_timing can write to a timing file inSDF format.


sdfout_min_rise_cell_delaySpecifies the minimum non-back-annotated rise celldelay that write_timing can write to a timing file inSDF format.


Synthesis Variables


sdfout_min_rise_net_delaySpecifies the minimum non-back-annotated rise netdelay that the write_timing command can write to atiming file in SDF format.


sdfout_time_scaleSpecifies the time scale of the delays written to timingfiles in SDF format.


sdfout_top_instance_nameSpecifies the name prepended to all instance nameswhen writing timing files in SDF format.


sdfout_write_to_outputSpecifies whether the write_timing -f sdf commandwrites interconnect delays between cells and top-leveloutput ports.


search_pathSpecifies directories that Design Compiler and DFTCompiler search for files specified without directorynames.

Default value for this variable is {search_path + .}.

sh_archThe sh_arch variable is set by the application toindicate the current system architecture of themachine you are using; such as sparcOS5, hpux10,and so on. This is a read-only variable.

Default value for this variable is Platform-dependent.


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sh_command_abbrev_modeCommand abbreviation is meant as an interactiveconvenience. Script files should probably not use anycommand or option abbreviation because these filesare then susceptible to command changes insubsequent versions of the application.

Default value for this variable is Anywhere.

sh_command_log_fileSpecifies the name of the file to which is written a logof the initial values of variables and executedcommands. For use in dc_shell-t (Tcl mode ofdc_shell) only.

Default value for this variable is ./command.log.

sh_continue_on_errorUnder normal circumstances, when executing a scriptwith source, Tcl errors (syntax and semantic) causethe execution of the script to terminate. Settingsh_continue_on_error to true allows processing tocontinue when errors occur. By default, this variableis set to false.


sh_dev_nullThe sh_dev_null variable is set by the application toindicate the current null device. For example, on Unixmachines, this is set to /dev/null. This is a read-onlyvariable.

Default value for this variable is Platform-dependent.

sh_enable_page_modeWhen true, long reports are displayed one page at atime (similar to the UNIX more command). Consultthe man page for various commands that generatereports to see if they are affected bysh_enable_page_mode.


Synthesis Variables


sh_new_variable_messageThe sh_new_variable_message variable controls adebugging feature for tracing the creation of newvariables. It's primary debugging purpose is to catchthe misspelling of an application-owned globalvariable. When true, an informational message(CMD-041) is displayed when a variable is definedfor the first time at the command line. When false, nomessage is is displayed.


sh_new_variable_message_in_procThe sh_new_variable_message_in_proc variablecontrols a debugging feature for tracing the creationof new variables in a Tcl procedure. It's primarydebugging purpose is to catch the misspelling of anapplication-owned global variable.


sh_new_variable_message_in_scriptThe sh_new_variable_message_in_script variablecontrols a debugging feature for tracing the creationof new variables within a sourced script. It's primarydebugging purpose is to catch the misspelling of anapplication-owned global variable.


sh_product_versionThis variable is set to the version of the applicationcurrently running. The variable is read only.


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sh_script_stop_severityWhen a script is executed with the source command,there are several ways to get it to stop executingbefore it completes. One is to use thesh_script_stop_severity variable. This variable can beset to none, W, or E. When set to E, the generation ofone or more error messages by a command will causea script to stop. When set to W, the generation of oneor more warning or error messages will cause a scriptto stop. Note that sh_script_stop_severity is ignored ifsh_continue_on_error is set to true.


sh_source_emits_line_numbersWhen a script is executed with the source command,error and warning messages can be emitted from anycommand within the script. Using thesh_source_emits_line_numbers variable, you can helpisolate where errors and warnings are occurring.


sh_source_loggingWhen you source a script, the source command isechoed to the command log file. By default, eachcommand in the script is logged to the command logfile as a comment. You can disable this logging bysetting sh_source_logging to false.


sh_source_uses_search_pathCauses the search command to use the search_pathvariable to search for files. This variable is for use indc_shell-t (Tcl mode of dc_shell) only.


Synthesis Variables


sh_tcllib_app_dirnameThe sh_tcllib_app_dirname variable is set by theapplication to indicate the directory whereapplication-specific Tcl files and packages are found.This is a read-only variable.

single_group_per_sheetSpecifies to the tool to put only one logic group on asheet.


site_info_fileContains the path to the site information file forlicensing.


sort_outputsSorts output ports on the schematic by port name.


suppress_errorsSpecifies a list of error codes for which messages areto be suppressed during the current DesignAnalyzer/dc_shell session.


symbol_librarySpecifies the symbol libraries to use during schematicgeneration.

Default value for this variable is {lsi_10k.sdb}.

synlib_disable_limited_licensesDisables or enables limited licenses for syntheticlibrary parts.



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synlib_dont_get_licenseSpecifies a list of synthetic library part licenses thatthe compiler does not automatically check out.


synlib_evaluation_modeEvaluates synthetic library parts, when noDesignWare-Basic or DesignWare-FPGA-Basic keysare available.


synlib_hiis_force_on_cellsSpecifies a list of design cells on which the compileris to force hierarchical incremental implementationselection (hiis).


synlib_iis_use_netlistAllows netlists of the DesignWare parts to be used asopposed to timing models for cost comparison duringthe Incremental Implementation Selection step.Timing models are created without considering thedesign context while netlists are mapped in thecontext of the design.


synlib_model_map_effortDetermines the map_effort used during modeling ofsynthetic library parts.

Default value for this variable is medium.

synlib_optimize_non_cache_elementsControls whether non-cached models are optimized orused in an unoptimized form.


Synthesis Variables


synlib_prefer_ultra_licenseDetermines the use by Design Compiler ofDesignWare Foundation library parts andDesignWare-Foundation and DesignWare-Foundation-Ultra licenses.


synlib_replace_synthetic_oaniReplaces non-inferable, single implementationsynthetic parts after elaboration.


synlib_sequential_moduleControls the amount of processing the compilecommand does during resource sharing andimplementation selection, on synthetic librarymodules that have implementations with sequentialelements.


synlib_wait_for_design_licenseSpecifies a list of authorized synthetic library licensesthat Design Compiler is to wait for.


synopsys_program_nameThis variable is read only, and is set by the applicationto indicate the name of the program you are running.This is useful when writing scripts that are mostlycommon between some applications, but containsome differences based on the application.

synopsys_rootThis variable is read only, and is set by the applicationto indicate the root directory from which theapplication was run.


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syntax_check_statusReports whether the syntax_check mode is enabled.


synthetic_librarySpecifies a list of synthetic libraries to use whencompiling. Default is {}.


systemcout_debug_modeThis variable is to be used only when thesystemcout_levelize variable is set to true, to generatedebug information.


systemcout_levelizeLevelizes and flattens the netlist and replaces standardDesignWare operations with simulatable SystemC,before writing out the netlist, during write -f systemccommand activity.


target_librarySpecifies the list of technology libraries ofcomponents to be used when compiling a design.

Default value for this variable is {your_library.db}.

tdlout_upcaseConverts to uppercase all names within TDL netlists.


template_naming_styleGenerates automatically a unique name when amodule is built.

Default value for this variable is %s_%p.

Synthesis Variables


template_parameter_styleGenerates automatically a unique name when amodule is built.

Default value for this variable is %s%d.

template_separator_styleGenerates automatically a unique name when amodule is built.

Default value for this variable is _.

test_allow_clock_reconvergenceAllows reconvergent nets to originate from the sametop-level clock port.


test_bsd_allow_tolerable_violationsAllows the optimize_bsd command to replaceobserve_and_control BSR cells with observe_onlycells or remove BSR cells during timing-driven orarea-driven optimization.


test_bsd_control_cell_drive_limitSpecifies the number of cells a single BSR control cellcan drive while optimizing control cell allocationduring optimize_bsd command activity.


test_bsd_manufacturer_idSpecifies the manufacturer ID to use to create thevalue captured in the device identification registerduring execution of the insert_bsd command.



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test_bsd_optimize_control_cellWhen true, allows the optimize_bsd command tooptimize allocation of BSR control cells during area-driven optimization, using the value of thetest_bsd_control_cell_drive_limit variable.


test_bsd_part_numberSpecifies the part number to use to create the valuecaptured in the device identification register duringexecution of the insert_bsd command.


test_bsd_version_numberSpecifies the version number to use to create the valuecaptured in the device identification register duringexecution of the insert_bsd command.


test_bsdl_default_suffix_nameSpecifies the default suffix for the name of the BSDLfile generated by the write_bsdl command.

Default value for this variable is bsdl.

test_bsdl_max_line_lengthSpecifies the maximum number of characters per linefor the output BSDL file the write_bsdl commandproduces.


test_capture_clock_skewSpecifies a qualitative measure of clock skew.

Default value for this variable is small_skew.

Synthesis Variables


test_cc_ir_masked_bitsIdentifies instruction register (IR) bits to be maskedduring the search by the check_bsd command for allpossible implemented instructions.


test_cc_ir_value_of_masked_bitsSpecifies values to be forced into bits of theinstruction register (IR) that are masked, during thesearch by the check_bsd command for all possibleimplemented instructions.


test_check_port_changes_in_captureChecks (through the check_test command) forchanges in values applied to bidirectional ports in theparallel measure cycle.


test_clock_port_naming_styleSpecifies the naming style used by the insert_scancommand for global test signal ports created indesigns during the addition of test circuitry.

Default value for this variable is test_c%s.

test_dedicated_subdesign_scan_outsInstructs DFT Compiler to create dedicated scan-outports on subdesigns.


test_default_bidir_delayDefines the default switching time of bidirectionalports in a tester cycle.



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test_default_client_orderEnables or disables test point utilities and determinesthe order in which they are invoked.


test_default_delayDefines the default time in a tester cycle to applyvalues to input ports.


test_default_periodDefines the default length of a test vector cycle.


test_default_scan_styleDefines the default scan style for the insert_dftcommand if a scan style is not specified with theset_scan_style command.

Default value for this variable ismultiplexed_flip_flop.

test_default_strobeDefines the default strobe time in a test cycle foroutput ports and bidirectional ports in output mode.


test_default_strobe_widthDefines the default strobe pulse width, which is thedefault time that specifies how long after invocationthe strobe pulse needs to be held active.


test_design_analyzer_uses_insert_scanExecutes (when true) the insert_scan commandthrough a Design Analyzer menu.


Synthesis Variables


test_disable_find_best_scan_outSelects (when true) the scan-out pin on a scan cellbased on availability instead of timing slack.


test_dont_fix_constraint_violationsMinimizes performance constraint violations.


test_enable_capture_checksControls checking for capture violations duringexecution of the check_dft command.


test_infer_slave_clock_pulse_after_captureGuides protocol inference for master/slave test designmethodologies during execution of the check_testcommand.

Default value for this variable is infer.

test_isolate_hier_scan_outPrevents the insert_dft command inserting logic thatisolates scan connections at hierarchical boundariesduring functional operation.


test_jump_over_bufs_invsDetermines whether or not insert_scan andpreview_scan consider output pins of buffers andinverters to be internal clocks.


test_mode_port_inverted_naming_styleSpecifies the naming style to use for thetest_hold_logic_zero type of test mode signal ports tobe created in the design.

Default value for this variable is test_mode_i%s.


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test_mode_port_naming_styleSpecifies the naming style to use for thetest_hold_logic_one type of test mode signal portscreated in the design.

Default value for this variable is test_mode%s.

test_mux_constant_siSpecifies how scan insertion uses a port you declareas scan input, when the port is tied high or to theground in functional mode.


test_mux_constant_soSpecifies how scan insertion uses a port you declareas scan output, when the port is tied high or to theground in functional mode.


test_non_scan_clock_port_naming_styleSpecifies the style the insert_dft command uses toname the ports that clock gating creates for nonscanclocks.

Default value for this variable is test_nsc_%s.

test_point_keep_hierarchySynthesizes (when true) test points and ungroups thetest point design, during execution of the insert_dftcommand.


test_preview_scan_shows_cell_typesShows (when true) cell instance types, duringexecution of the preview_scan command.


Synthesis Variables


test_protocol_add_cycleAdds an extra cycle (when true) after the shift cycle,in the test protocol, during execution of the check_testcommand.


test_rtldrc_latch_check_styleSpecifies the latch check style to use during rtldrccommand activities.


test_scan_clock_a_port_naming_styleDetermines the naming style to be used by theinsert_scan command for test scan clock a portscreated in designs during the addition of test scancircuitry.

Default value for this variable is test_sca%s.

test_scan_clock_b_port_naming_styleDetermines the naming style to be used by theinsert_scan command for test scan clock b portscreated in designs during the addition of test scancircuitry.

Default value for this variable is test_scb%s.

test_scan_clock_port_naming_styleDetermines the naming style used by the insert_scancommand for global test scan signal ports created indesigns during the addition of test circuitry.

Default value for this variable is test_scs%s.

test_scan_enable_inverted_port_naming_styleDetermines the naming style to be used by theinsert_scan command for scan enable inverted portscreated in designs during the addition of test scancircuitry.

Default value for this variable is test_sei%s.


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test_scan_enable_port_naming_styleDetermines the naming style to be used by theinsert_scan command for test scan enable portscreated in designs during the addition of test scancircuitry.

Default value for this variable is test_se%s.

test_scan_in_port_naming_styleSpecifies the naming style used by the insert_scancommand for serial test-signal ports created indesigns during the addition of test circuitry.

Default value for this variable is test_si%s%s.

test_scan_link_so_lockup_keyIndicates to the preview_scan command what key touse to identify cells with scan-out lock-up latches inreports.

Default value for this variable is l.

test_scan_link_wire_keyIndicates to the preview_scan command the key to useto identify cells that drive wire-scan links in reports.

Default value for this variable is w.

test_scan_out_port_naming_styleUsed the same as test_scan_in_port_naming_style .

Default value for this variable is test_so%s%s.

test_scan_segment_keyTells the preview_scan command what key to use toidentify scan segments in reports.

Default value for this variable is s.

test_scan_true_keySpecifies to the preview_scan command the key to useto identify in reports cells with true scan attributes.

Default value for this variable is t.

Synthesis Variables


test_stil_max_line_lengthSpecifies the maximum line length for the file writtenby the write_test_protocol -format stil command.


test_stil_multiclock_capture_proceduresIndicates to the write_test_protocol -format stilcommand to create capture procedures in the STILprotocol, with multiple clocks active in eachprocedure.


test_stil_netlist_formatIndicates to the write_test_protocol command whatnetlist format to use when writing out STIL protocolfiles.

Default value for this variable is db.

test_user_defined_instruction_naming_styleIndicates to the check_bsd command and thewrite_bsdl command the naming style to use for theuser-defined (nonstandard) instructions inferred bythese commands.

Default value for this variable is USER%d.

test_user_test_data_register_naming_styleIndicates to the check_bsd command and thewrite_bsdl command the naming style to use for theuser-defined (nonstandard) test data registers inferredby these commands.

Default value for this variable is UTDR%d.

test_write_four_cycle_stil_protocolInstructs the write_test_protocol -format stilcommand to insert in the output STIL protocol file adummy cycle between all measure and capture cyclesin the STIL protocol.



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text_editor_commandSpecifies the command that executes when theEdit/File menu is selected in the Design Analyzer textwindow.

Default value for this variable is xterm.

text_print_commandSpecifies the command that executes when theFile/Print menu is selected in the Design Analyzertext window.

Default value for this variable is lpr.

timing_disable_internal_inout_cell_pathsDisables bidirectional feedback paths in a cell if set totrue.


timing_disable_internal_inout_net_arcsDisables bidirectional feedback paths that involvemore than one cell if the variable is true.


timing_report_attributesSpecifies the list of attributes to be reported with thereport_timing -attributes command.

Default value for this variable is {dont_touch,dont_use, map_only, size_only, ideal_net}.

timing_self_loops_no_skewAffects the behavior, runtime, and CPU usage ofreport_timing and compile.


true_delay_prove_false_backtrack_limitSpecifies to the report_timing -true command thenumber of backtracks to use in searching for falsepaths.


Synthesis Variables


true_delay_prove_true_backtrack_limitSpecifies the number of backtracks the report_timing-true command is to use in searching for true paths.


uniquify_naming_styleSpecifies the naming convention to be used by theuniquify command.

Default value for this variable is %s_%d.

use_port_name_for_oscsSpecifies that when off-sheet connectors for nets alsohave ports on them, they are given the name of theport.


verbose_messagesCauses more explicit system messages to be displayedduring the current Design Analyzer dc_shell session.


verilogout_debug_modeInstructs Behavioral Compiler (under specificconditions) to insert additional code to write outdebugging information during the RTL simulationrun. This variable (when set to true) is to be used onlywhen the variable verilogout_levelize is also set totrue.


verilogout_equationWrites Verilog assign statements (Boolean equations)for combinational gates, rather than gateinstantiations.



242


verilogout_higher_designs_firstWrites Verilog modules so that the higher leveldesigns come before lower level designs, as definedby the design hierarchy.


verilogout_ignore_caseInstructs the compiler not to consider case whencomparing identifiers to Verilog reserved words.


verilogout_include_filesSpecifies to the write -f verilog command (when theverilogout_levelize variable is set to true) to write aninclude statement that will have the name of the valueyou set for this variable.


verilogout_levelizeSpecifies, when true, to the write -f verilog commandto levelize and flatten the netlist and to replacestandard DesignWare operations with simulatableVerilog, before writing out the netlist.


verilogout_no_negative_indexShifts the negative range to the positive range starting0. For example, if you have 0 downto -7, it becomes 7downto 0.


verilogout_no_triDeclares three-state nets as Verilog wire instead of tri.This variable is useful in eliminating assign primitivesand tran gates in the Verilog output.


Synthesis Variables


verilogout_show_unconnected_pinsInstructs the Verilog writer in dc_shell to write out allof the unconnected instance pins, when connectingmodule ports by name. For example, modb b1(.A(in),.Q(out),.Qn()).


verilogout_single_bitInstructs the compiler not to output vectored ports inthe Verilog output. All vectors are written as singlebits.


verilogout_unconnected_prefixInstructs the Verilog writer in dc_shell to use thename (SYNOPSYS_UNCONNECTED_) to createunconnected wire names. The general form of thename is SYNOPSYS_UNCONNECTED_%d.

Default value for this variable isSYNOPSYS_UNCONNECTED_.

vhdllib_architectureDetermines the VHDL model types for the write_libcommand to generate.

Default value for this variable is {FTGS,VITAL}.

vhdllib_glitch_handleDetermines if timing hazards have glitch-forced (on-detect) or spike-forced (on-event) Xs. When true (thedefault value), Xs are glitch-forced; when false, theXs are spike-forced.



244


vhdllib_logic_systemSelects the logic system in which to create the VHDLlibraries. Currently only ieee-1164, for the IEEE1164.1 nine value (std_logic) logic system, isallowed. Do not change the value of this variable toanything other than ieee-1164.

Default value for this variable is ieee-1164.

vhdllib_logical_nameThis variable defines the logical name to be used bythe VHDL libraries. If the variable is set to an emptystring, the file base name is used as the default.


vhdllib_negative_constraintDetermines whether a generated VITAL model is tohave negative constraint handling capability.


vhdllib_pulse_handleDetermines the algorithm used to handle timinghazards for the FTGS model. Values are glitch, spike,transport, inertial, or use_vhdllib_glitch_handle (thedefault).

Default value for this variable isuse_vhdllib_glitch_handle.

vhdllib_tb_compareControls library testbench generation. No testbenchesare created if this variable is set to 0 (the default).


vhdllib_tb_x_eq_dontcareSpecifies the default value for the testbenchesX_Eq_DontCare generic Boolean flag. IfX_Eq_DontCare is true, X states are ignored duringoutput comparisons. The default is false.


Synthesis Variables


vhdllib_timing_checksDetermines the default value for the cellTimingChecksOn generic Boolean flag in the VITALmodel.


vhdllib_timing_mesgDetermines the default value for the cellTiming_mesg generic Boolean flag in FTSM, UDSM,and FTGS models. It also determines the value of theGlitchMode parameter for theVitalPropagatePathDelay procedure in the VITALmodel.


vhdllib_timing_xgenDetermines the default value for the cell Timing_xgengeneric Boolean flag in FTSM, UDSM, and FTGSmodels. It also determines the default value for thecell XGenerationOn generic Boolean flag in theVITAL model.


vhdlout_architecture_nameDetermines the name to be used for the architecturethe write -f vhdl command writes out.

Default value for this variable is SYN_%a_%u.

vhdlout_bit_typeSets the basic bit type in a design written to VHDL.

Default value for this variable is std_logic.

vhdlout_bit_type_resolvedPrevents the VHDL writer (VHDLout) creating newbus resolution functions when writing wired logic.



246


vhdlout_bit_vector_typeSets the basic bit vector type in a design written toVHDL.

Default value for this variable is std_logic_vector.

vhdlout_conversion_functionsOverrides conversion functions that are written out.


vhdlout_debug_modeInstructs Behavioral Compiler (under specificconditions) to insert additional code to write outdebugging information during the RTL simulationrun.


vhdlout_dont_create_dummy_netsInstructs the VHDL writer not to create dummy netsfor connecting unused pins or ports.


vhdlout_dont_write_typesSpecifies to the compiler not to write typedeclarations for any types declared in the originalVHDL.


vhdlout_equationsSpecifies to the compiler how to write combinationallogic and sequential logic.


vhdlout_follow_vector_directionSpecifies to the compiler to use the original rangedirection when writing out an array.


Synthesis Variables


vhdlout_levelizeSpecifies to the write -f vhdl command to levelize andflatten a netlist.


vhdlout_one_nameDetermines the literal name for constant bit value 1 ina design written in VHDL.


vhdlout_package_naming_styleDetermines the name to be used for the typeconversion packages written out by the VHDL writer(VHDLout).

Default value for this variable is CONV_PACK_%d;.

vhdlout_preserve_hierarchical_typesAffects the way in which the write -f vhdl commandwrites out ports on lower-level designs>

Default value for this variable is VECTOR.

vhdlout_separate_scan_inAffects the way in which the scan chain is written outin VHDL.


vhdlout_single_bitAffects the way in which the write -f vhdl commandwrites out ports on the top-level design.

Default value for this variable is USER.

vhdlout_synthesis_offInstructs the write -f vhdl command to write outsynthesis_off and synthesis_on at the beginning andend of the configuration statement, but only when thevhdlout_write_top_configuration variable is also true.



248


vhdlout_target_simulatorNames the target simulator to which the VHDL file iswritten. Currently, the only valid value is xp.


vhdlout_three_state_nameNames the high impedance bit value used for three-state device values.

Default value for this variable is `Z.'

vhdlout_three_state_res_funcNames a user-supplied three-state resolution functionthat must be in one of the packages specified by thevhdlout_use_packages variable.


vhdlout_time_scaleSpecifies the scaling of the delays the compiler writesto timing files in Synopsys VHDL format.


vhdlout_top_configuration_arch_nameDetermines the name of the outside architecture,depending on the setting of thevhdlout_write_top_configuration variable, and causesthe VHDL writer (VHDLout) to write out aconfiguration statement.

Default value for this variable is A.

vhdlout_top_configuration_entity_nameDetermines the name of the outside entity, dependingon the setting of the vhdlout_write_top_configurationvariable, and causes the VHDL writer (VHDLout) towrite out a configuration statement.

Default value for this variable is E.

Synthesis Variables


vhdlout_top_configuration_nameDetermines the name of the configuration statementthe write command writes out when thevhdlout_write_top_configuration variable is set totrue.

Default value for this variable is CFG_TB_E.

vhdlout_unknown_nameSpecifies the value the compiler uses to drive a signalto the unknown state.

Default value for this variable is X.

vhdlout_upcase

vhdlout_use_packagesInstructs the write command to write into the VHDLfile a use clause containing a list of package names,for each of these packages, for all entities.

Default value for this variable is{IEEE.std_logic_1164}.

vhdlout_wired_and_res_funcSpecifies the name of a wired and resolution function.


vhdlout_wired_or_res_funcSpecifies the name of a wired or resolution function.


vhdlout_write_architectureInstructs the write -format vhdl command to write outarchitecture declarations.



250


vhdlout_write_componentsInstructs the write -format vhdl command to write outcomponent declarations for cells mapped to atechnology library.


vhdlout_write_entityInstructs the write -format vhdl command to write outentity declarations.


vhdlout_write_top_configurationInstructs the write -format vhdl command to write outa configuration statement if necessary, such as whenports on the top-level design are written as vectorsinstead of user types.


vhdlout_zero_nameDetermines the literal name for constant bit value `0'in a design written to VHDL.


view_analyze_file_suffixSpecifies, in a list of file extensions, the files shown inthe File/Analyze dialog box of Design Analyzer.

Default value for this variable is {v, vhd, vhdl}.

view_arch_typesSets the contents of the architecture option menu.Contains a list of host machine architectures you canuse for background jobs from the Design Analyzerviewer.

Default value for this variable is {sparcOS5, hpux10,rs6000, sgimips}.

Synthesis Variables


view_backgroundSpecifies the background color of the DesignAnalyzer viewer.

Default value for this variable is white.

view_cache_imagesSpecifies to Design Analyzer that the tool is to cachebitmaps for fast schematic drawing.


view_command_log_fileNames a file and its location that is to contain all textwritten to the Design Analyzer Command window.


view_command_win_max_linesContains the maximum number of lines to be saved inthe Design Analyzer command window.


view_dialogs_modalRequires that the question and error dialogs in DesignAnalyzer be confirmed, before you can continueentering commands.


view_disable_cursor_warpingCauses the cursor to be automatically warped(moved). When false, the cursor is automaticallywarped (or moved) to dialog boxes.


view_disable_error_windowsInstructs Design Analyzer not to post the errorwindows when errors occur.



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view_disable_outputDisables output to the Design Analyzer commandwindow.


view_error_window_countSpecifies the maximum number of errors DesignAnalyzer reports for a command.


view_execute_script_suffixDisplays only files with the stated suffixes, fromdirectories you select in the Execute Script optionwindow of the Setup menu of Design Analyzer.

Default value for this variable is {.script, .scr, .dcs,.dcv, .dc, .con}.

view_info_search_cmdInvokes, if set, the online information viewer throughthe optional menu item On-Line Information.


view_log_fileSpecifies the file in which the tool stores events thatoccur in the viewer.


view_on_line_doc_cmdInvokes, if set, the online documentation viewer,through the optional menu item On-LineDocumentation.


view_read_file_suffixDisplays only files with the stated suffixes, fromdirectories you select with the Read option of the Filemenu of Design Analyzer.

Default value for this variable is v, vhd, vhdl, xnf.

Synthesis Variables


view_report_appendSpecifies to the tool to append to the specified file thereports the Design Vision menus generate.


view_report_interactiveSpecifies to the tool to send to the command line viewthe reports generated by Design Vision menus.


view_report_output2fileSpecifies to the tool to send to the specified file thereports generated by Design Vision menus.


view_script_submenu_itemsAllows users to add to the Design Analyzer Setuppulldown menu valid items to invoke user scripts.


view_tools_menu_itemsPermits partial configuration of the Tools pulldownmenu to add a new menu item for invoking userscripts.


view_use_small_cursorSpecifies to the tool that the X display is to supportonly 16 x 16-bit map size cursors.


view_use_x_routinesEnables the use of internal arc-drawing routines(instead of X routines).



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view_write_file_suffixDisplays only files with the stated suffixes, fromdirectories you select with the Save As option of theFile menu of Design Analyzer.

Default value for this variable is vhd, vhdl, xnf}.

write_name_mapping_nowarn_librariesSpecifies a list of libraries for which no warningmessages are to be issued by write -f edif -names_fileif the command does not find the libraries.


write_name_nets_same_as_portsSpecifies to the tool that nets are to receive the samenames as the ports the nets are connected to.


write_test_formatsSpecifies the test vector formats recognized andcreated by the write_test command.

Default value for this variable is {synopsys, tssi_ascii,tds, verilog, vhdl, wgl}.

write_test_include_scan_cell_infoSpecifies to the write_test command to include in thevector files scan-chain, cell, and inversion informationfor vector formats.


write_test_input_dont_care_valueControls the logic value the write_test commandoutputs when you have an input with a don't carecondition.

Default value for this variable is X.

Synthesis Variables


write_test_max_cyclesControls the automatic partitioning of long test setsacross multiple files, by specifying the maximumnumber of tester cycles any one vector file cancontain.


write_test_max_scan_patternsControls the automatic partitioning of long test setsacross multiple files, by specifying the maximumnumber of scan test patterns any one vector file cancontain.


write_test_pattern_set_naming_styleSpecifies how to name pattern sets when long test setsare partitioned across multiple files.

Default value for this variable is TC_Syn_%d.

write_test_round_timing_valuesSpecifies to the write_test command to round to thenearest integer all timing values.


write_test_scan_check_file_naming_styleSpecifies how to name the file containing the vectorsthat test the scan chain logic.

Default value for this variable is %s_schk.%s.

write_test_vector_file_naming_styleSpecifies how to name scan vector files, when longtest sets are partitioned across multiple files.

Default value for this variable is %s_%d.%s.

x11_set_cursor_backgroundSpecifies background color of the cursor in the DesignAnalyzer menus and viewer.



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x11_set_cursor_foregroundSpecifies foreground color of the cursor in the DesignAnalyzer menus and viewer.


x11_set_cursor_numberSpecifies the cursor, from the standard X cursor fontused by the Design Analyzer menus and viewer.

Default value for this variable is -1.

xnfin_dff_clock_enable_pin_nameInstructs the read -format xnf command to assumethat the clock enable pin name on the DFF (D flip-flop) component has the given string name.

Default value for this variable is CE.

xnfin_dff_clock_pin_nameInstructs the read -format xnf command to assumethat the clock pin name on the DFF (D flip-flop)component has the given string name.

Default value for this variable is C.

xnfin_dff_data_pin_nameInstructs the read -format xnf command to assumethat the data pin name on the DFF (D flip-flop)component has the given string name.

Default value for this variable is D.

xnfin_dff_q_pin_nameInstructs the read -format xnf command to assumethat the Q pin name on the DFF (D flip-flop)component has the given string name.

Default value for this variable is Q.

Synthesis Variables


xnfin_dff_reset_pin_nameInstructs the read -format xnf command to assumethat the reset pin name on the DFF (D flip-flop)component has the given string name. Use thisvariable to support different versions of the Xilinxlibrary, which can have differing pin names for thesesequential devices.

Default value for this variable is RD.

xnfin_dff_set_pin_nameInstructs the read -format xnf command to assumethat the set pin name on the DFF (D flip-flop)component has the given string name.

Default value for this variable is SD.

xnfin_familyInstructs the read -format xnf command to assumethat the file being read is a design of the specifiedXilinx family. The XNF reader supports only the 4000family of Xilinx parts, so 4000 is the only valid value.


xnfin_ignore_pinsInstructs the read -format xnf command to leaveunconnected the given Xilinx component pin names.

Default value for this variable is GTS, GSR, GR.

xnfout_clock_attribute_styleControls the style in which the write -format xnfcommand writes XNF netlist timing constraints.

Default value for this variable is CLK_ONLY.

xnfout_constraints_per_endpointSpecifies the number of constraints the write -formatxnf command will write out for each endpoint in thedesign for a constraint type. An endpoint is either anoutput port or an input pin to a sequential element.



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xnfout_default_time_constraintsInstructs the write -format xnf command (when set totrue, the default) to write out default time constraintsfor the paths in the design that are not covered by aspecific path timing constraint.


xnfout_library_versionInstructs the write -format xnf command to write outthe LIBVER= attribute with this string, on symbolrecords.


xterm_executableSpecifies the path to an xterm program spawned torun Synopsys analysis tools (for example, RTLAnalyzer or BCView). The default is xterm.

Default value for this variable is xterm.

Synthesis Variables

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