VHDL 360©

by: Mohamed Samy Samer El-Saadany

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Module 4

Synthesis Examples

Objective

• Getting familiar with code changes' impact on synthesis

• Skills gained:– Writing synthesis friendly code

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Outline• Introduction• Synthesize and Learn

– Combinational Logic– Latch Inference– Sequential Logic– Flip-Flop Inference

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Introduction

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• VHDL is a H/W modeling language used to model digital circuits

• Digital circuits can be either Combinational or Sequential– Combinational Logic circuits: Implement Boolean

functions whose output is only dependant on the present inputs

– Sequential Logic circuits: Implement circuits whose output depends on the present inputs & the history of the inputs. i.e. Circuits having storage elements

Introduction

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• Synthesis tools translate the VHDL code to a gate level netlist representing the actual H/W gates [and, or, not, Flip-Flops…etc]

• Only a subset of the language is synthesizable– A model can be either

• Synthesizable: Used for both Simulation & Synthesis• Non-Synthesizable: Used for Simulation only

VHDL Standard

Synthesizable VHDL

SYNTHESIZE AND LEARN

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Synthesize and Learn

• In the next slides we will use examples from the previous modules to demonstrate synthesis and study the synthesized logic

• We will also modify these examples and observe the impact on the synthesized logic

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Combinational Logiclibrary IEEE; use IEEE.std_logic_1164.all; Entity mux_case is Port(a, b, c, d: in std_logic; Sel: in std_logic_vector(1 downto 0); F: out std_logic); End entity;

Architecture rtl of mux_case is begin process (a,b,c,d,sel) is begin Case sel is When "00" => f <= a; When "01" => f <= b; When "10" => f <= c; When "11" => f <= d; when others => f <= a; End case; End process; End architecture;

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Example 1: 4x1 Multiplexer

Skills Check• What is the impact of removing some signals from the sensitivity list

as shown in example 2?

Architecture rtl of mux_case is begin process (a,b,c,d,sel) is begin

Case sel is When "00" => f <= a; When "01" => f <= b; When "10" => f <= c; When "11" => f <= d; when others => f <= a; End case; End process; End architecture;

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Architecture rtl of mux_case is begin process (a, sel) is begin

Case sel is When "00" => f <= a; When "01" => f <= b; When "10" => f <= c; When "11" => f <= d; when others => f <= a; End case; End process; End architecture;

Example 2: 4x1 Multiplexer Example 1: 4x1 Multiplexer

Skills Check (Soln.)

Architecture rtl of mux_case is begin process (a,b,c,d,sel) is begin

Case sel is When "00" => f <= a; When "01" => f <= b; When "10" => f <= c; When "11" => f <= d; when others => f <= a; End case; End process; End architecture;

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Architecture rtl of mux_case is begin process (a, sel) is begin

Case sel is When "00" => f <= a; When "01" => f <= b; When "10" => f <= c; When "11" => f <= d; when others => f <= a; End case; End process; End architecture;

Example 2: 4x1 MultiplexerExample 1: 4x1 Multiplexer

• No Impact on the synthesis results, however we will find that the simulation results differ

• Synthesis tools don’t use the sensitivity list to determine the logic, but simulation tools depend on the sensitivity list to execute the process

• Example 2 suffers a problem called “Simulation – Synthesis mismatch”

Combinational Logic• VHDL 2008* introduced the keyword "all" that implicitly adds all read

signals to the sensitivity list to avoid “Simulation Synthesis mismatch”

Architecture rtl of mux_case is begin process (all) is begin

Case sel is When "00" => f <= a; When "01" => f <= b; When "10" => f <= c; When "11" => f <= d; when others => f <= a; End case; End process; End architecture;

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*Not yet supported by all tools in the market

Example 3

Golden rule of thumb• To avoid “Simulation Synthesis mismatch” problems when

modeling Combinational logic, add all read signals to the sensitivity list

Combinational Logic

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LIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY add_sub IS port (a, b : in integer; result : out integer; operation: in std_logic);END ENTITY;

ARCHITECTURE behave OF add_sub IS BEGIN process (a, b, operation) begin if (operation = '1') then result <= a + b; else result <= a - b; end if; end process;END ARCHITECTURE;

Example 4: Adder-Subtractor

Combinational Logic

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LIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY adder IS port (a, b : in integer; result : out integer; enable: in std_logic); END ENTITY adder;

ARCHITECTURE behave OF adder IS BEGIN process (a, b, enable) begin if (enable = '1') then result <= a + b; end if; end process;END ARCHITECTURE;

• Consider that someone tries to re-use that code to implement an adder with an enable He modifies the add_sub example; removes the else branch & renames the “operation” port to “enable” as shown below, How would these changes affect the logic?

Example 5:

Combinational Logic

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LIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY adder IS port (a, b : in integer; result : out integer; enable: in std_logic); END ENTITY adder;

ARCHITECTURE behave OF adder IS BEGIN process (a, b, enable) begin if (enable = '1') then result <= a + b; end if; end process;END ARCHITECTURE;

Example 5:

• This will infer a latch, because we didn’t specify what should happen to “result” when “enable” isn’t equal to '1'

• Simulation & synthesis tools will just keep the value as is…i.e. It latches the last value

Combinational Logic

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY incomplete_case IS port(sel : std_logic_vector (1 downto 0); A, B: std_logic; F : out std_logic); END ENTITY; ARCHITECTURE rtl OF incomplete_case IS BEGIN process (sel, A, B) begin case (sel) is when "00" => F <= A; when "01" => F <= B; when "10" => F <= A xor B; when others => null; end case; end process; END ARCHITECTURE;

Example 6:

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• In the below example, the "11" value of "sel" signal is not listed as a case choice, hence signal "F" is not assigned a value in this case

• A Latch is inferred in this example Probably that wasn’t needed

Skills Check

LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY incomplete_assignment IS port(sel : in std_logic_vector (1 downto 0); A, B : in std_logic; O1, O2: out std_logic); END ENTITY; ARCHITECTURE rtl OF incomplete_assignment ISBEGIN process (sel, A, B) begin case (sel) is when "00" => O1 <= A; O2 <= A and B; when "01" => O1 <= B; O2 <= A xor B; when "10" => O1 <= A xor B; when "11" => O2 <= A or B; when others => O1 <= '0'; O2 <= '0'; end case; end process; END ARCHITECTURE;

Example 7:

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• Do you think a Latch would be inferred in the below example?

Skills Check (Soln.)

LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY incomplete_assignment IS port(sel : in std_logic_vector (1 downto 0); A, B : in std_logic; O1, O2: out std_logic); END ENTITY; ARCHITECTURE rtl OF incomplete_assignment ISBEGIN process (sel, A, B) begin case (sel) is when "00" => O1 <= A; O2 <= A and B; when "01" => O1 <= B; O2 <= A xor B; when "10" => O1 <= A xor B; when "11" => O2 <= A or B; when others => O1 <= '0'; O2 <= '0'; end case; end process; END ARCHITECTURE;

Example 7:

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• Do you think a Latch would be inferred in the below example?

• Latches are inferred for both signals "O1" & "O2"• Though the case is complete & no "null" statement

is there, we find that "O1" & "O2" are not assigned in all case's branches This is called “Incomplete signal assignment”

Latch Inference• Most of the time latches are not desired in the

design because they affect timing badly• To remove unintended latches:

– Cover all branches of if-else and case statements– Avoid incomplete signal assignment by assigning a value

to each signal in each branch• if you don’t care about other conditional values then assign the

output to '0' or '1'

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ENOUGH COMBINATIONALLET'S GO SEQUENTIAL

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Sequential Logic

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Library ieee; use ieee.std_logic_1164.all;Entity d_ff is Port(d, clk, rst : in std_logic; Q, nQ : out std_logic);end entity;Architecture behav of d_ff is Begin process(clk) begin If (rising_edge(clk)) then If (rst = '1') then Q <= '0'; nQ <= '0'; else Q <= d; nQ <= not (d); end if; end if; end process;end behav;

• Let's model the well known D-FF with outputs Q & nQ and see the synthesis results

Example 8:

Sequential Logic

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Library ieee; use ieee.std_logic_1164.all;Entity d_ff is Port(d, clk, rst : in std_logic; Q, nQ : out std_logic);end entity;Architecture behav of d_ff is Begin process(clk) begin If (rising_edge(clk)) then If (rst = '1') then Q <= '0'; nQ <= '1'; else Q <= d; nQ <= not (d); end if; end if; end process;end behav;

• Let's model the well known D-FF with outputs Q & nQ and see the synthesis results

Example 8:

Two Flip-Flops ?!

Change the code to have only one Flip-Flop

Sequential Logic

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• Let's model the well known D-FF with outputs Q & nQ and see the synthesis results

Example 9:

Yep…That's what we want!

Library ieee; use ieee.std_logic_1164.all;Entity d_ff is Port( d, clk, rst : in std_logic; Q, nQ : out std_logic);end entity;Architecture behav of d_ff is signal Q_int: std_logic;Begin process(clk) begin If (rising_edge(clk)) then If (rst = '1') then Q_int <= '0'; else Q_int <= d; end if; end if; end process; Q <= Q_int; nQ <= not (Q_int); end behav;

Sequential Logic

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Library ieee; use ieee.std_logic_1164.all;Entity d_ffs is Port(d: std_logic_vector (3 downto 0); clk, rst : in std_logic; Q, nQ : out std_logic_vector (3 downto 0));end entity;Architecture behav of d_ffs is signal Q_int: std_logic_vector (3 downto 0); Begin process(clk) begin If (rising_edge(clk)) then If (rst = '1') then Q_int <= (others => '0'); else Q_int <= d; end if; end if; end process; Q <= Q_int; nQ <= not (Q_int); end behav;

• What about making an array of D-FFs?Example 10:

7 6 5 4 3 2 1 0

Library ieee; use ieee.std_logic_1164.all;entity shift_register is Port ( clk, D, enable : in STD_LOGIC; Q : out STD_LOGIC); end entity; architecture Behavioral of shift_register is begin process(clk) variable reg: std_logic_vector(7 downto 0); begin if rising_edge(clk) then if enable = '1' then for i in 1 to 7 loop reg(i-1) := reg(i); end loop; reg(7) := d; end if; end if; Q <= reg(0); end process; end Behavioral;

Sequential LogicExample 11: 8-bit Shift Register (Shift right)

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Flip-Flop Inference

• Assignments under clock edge where the object value needs to be remembered across multiple process invocations Flip-Flop– Signal assignment under clock edge will always infer a Flip-Flop– Variable assignment under clock edge will infer Flip-Flop only when

its value ought to be remembered across process invocations

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Exercise 1

LIBRARY ieee; USE ieee.std_logic_1164.all; Entity unknown is port(x: out std_logic; y: in std_logic_vector(3 downto 0); c: in integer); End entity; Architecture behave of unknown is Begin x <= y(c); End behave;

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• Deduce what the below code models• Use synthesis tool to validate your answer

Contacts

• You can contact us at:– http://www.embedded-tips.blogspot.com/

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