Synchronous design process
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Synchronous Design Process1. Construct a state diagram and/or state/output table
corresponding to the word description or specification
2. Minimize the number of states
3. Choose a set of state variables and assign state variable combinations to the named states
4. Obtain the transition/output table
5. Determine the number of flip-flops and select the type of flip-flop to be used (D is often the default)
6. Construct the excitation table
7. Derive excitation equations
8. Derive output equations
9. Draw the logic diagram that realizes the equations
1
Design a clocked synchronous state machine
which detects a sequence of three or more
consecutive 1’s in a string of bits coming through
an input line.
Let the input be X and output be Z
Assuming Mealy machine design
Mealy machine with D flip flops
Moore machine with D flip flops
Moore machine with JK flip flops
Mealy machine with D flip flops (change of encoding)
Obtaining the state Diagram
Assume initial condition to be Z = 0Let the initial state be represented by state A If X = 0, then output Z = 0, same state A
= 1, then output Z = 0, goes to state B
A B0/01/0
X/Z
01
0
A
0
B
Mealy machine
Moore machine
Obtaining the state Diagram
Assume machine has moved to state B If X = 0, then output Z = 0, goes back to state A
= 1, then output Z = 0, goes to state C
A B0/01/0
X/Z
01
0
A
0
B
C1/0
0/0
1
0
C
0
Mealy machine
Moore machine
Obtaining the state Diagram
Assume machine has moved to state C If X = 0, then output Z = 0, goes back to state A
= 1, then output Z = 1, same state C
A B0/01/0
X/Z
01
0
A
0
B
C1/0
0/0
1
0
0C
0
1/1
0/0
0
1
1
1C1
0
Mealy machine
Moore machine
Obtaining the state/output table
State/output table
Next State S*, Z
State Input X
S 0 1
A A,0 B,0
B A,0 C,0
C A,0 C,1
State/output table
Next State S*
State Input X
S 0 1
A A B
B A C0
C0 A C1
C1 A C1
Output
Z
0
0
0
1
Mealy machine Moore machine
Assigning state variable to obtain transition/output
tableTransition/output table
Encoding A = 00, B = 01 C0 = 10,C1 = 11
Choosing D type flip flop
Next State Q1*Q0*, Z
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 10,0
10 00,0 10,1
Next State Q1*Q0*
State Input X
Q1Q0 0 1
00 00 01
01 00 10
10 00 11
11 00 11
Output
Z
0
0
0
1
Transition/output tableMealy machine Moore machine
Constructing the excitation table
Excitation/output table
D1D0, Z
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 10,0
10 00,0 10,1
D1D0
State Input X
Q1Q0 0 1
00 00 01
01 00 10
10 00 11
11 00 11
Output
Z
0
0
0
1
Excitation/output tableMealy machine Moore machine
Transferring onto K-maps to derive excitation
equations (Mealy Machine)State Input X
Q1Q0 0 1
00 0 0
01 0 1
11 X X
10 0 1
D1
State Input X
Q1Q0 0 1
00 0 1
01 0 0
11 X X
10 0 0
D0XQXQD 101
Excitation/output table
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 10,0
10 00,0 10,1
D1D0, Z XQQD 010
Transferring onto K-maps to derive output equation
(Mealy Machine)Excitation/output table
State Input X
Q1Q0 0 1
00 0 0
01 0 0
11 X X
10 0 1
ZXQZ 1
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 10,0
10 00,0 10,1
D1D0, Z
Circuit (logic) diagram
excitation equations
output equation
D Q
Q
Q0
Z
Q0' Q1
Clk
D Q
Q
Q0D0
D1 Q1
X
XQXQD 101XQQD 010
XQZ 1
Q1'
Mealy machine
Transferring onto K-maps to derive excitation
equation (Moore Machine)State Input X
Q1Q0 0 1
00 0 0
01 0 1
11 0 1
10 0 1
D1
State Input X
Q1Q0 0 1
00 0 1
01 0 0
11 0 1
10 0 1
D0XQXQD 101
Excitationtable
XQXQD 010
D1D0
State Input X
Q1Q0 0 1
00 00 01
01 00 10
10 00 11
11 00 11
Transferring onto K-maps to derive output equation
(Moore Machine)Excitation/output table
01 QQZ
D1D0
State Input X
Q1Q0 0 1
00 00 01
01 00 10
10 00 11
11 00 11
Output
Z
0
0
0
1
Circuit (logic) diagram
excitation equations
output equation
D Q
Q
Q0Z
Q0' Q1
Clk
D Q
Q
Q0D0
D1 Q1
X
XQXQD 010 XQXQD 101
01 QQZ
Moore machine
Assigning state variable to obtain transition/output
tableTransition/output table
Next State Q1*Q0*
State Input X
Q1Q0 0 1
00 00 01
01 00 10
10 00 11
11 00 11
Output
Z
0
0
0
1
Q Q* J
0 0 0
0 1 1
1 0 X
1 1 X
K
X
X
1
0
Excitation table for JK flip flop
Moore machine with JK flip flops
Constructing the excitation table
J1K1,J0K0
State Input X
Q1Q0 0 1
00 0X, 0X 0X, 1X
01 0X, X1 1X, X1
10 X1, 0X X0, 1X
11 X1, X1 X0, X0
Output
Z
0
0
0
1
Excitation/output tableTransition/output table
Next State Q1*Q0*
State Input X
Q1Q0 0 1
00 00 01
01 00 10
10 00 11
11 00 11
Output
Z
0
0
0
1
Transferring onto K-maps to derive excitation
equationsState Input X
Q1Q0 0 1
00 0 0
01 0 1
11 X X
10 X X
J1
State Input X
Q1Q0 0 1
00 X X
01 X X
11 1 0
10 1 0
K1XQJ 01
Excitationtable
XK 1
J1K1,J0K0
State Input X
Q1Q0 0 1
00 0X, 0X 0X, 1X
01 0X, X1 1X, X1
10 X1, 0X X0, 1X
11 X1, X1 X0, X0
Transferring onto K-maps to derive excitation
equationsState Input X
Q1Q0 0 1
00 0 1
01 X X
11 X X
10 0 1
J0
State Input X
Q1Q0 0 1
00 X X
01 1 1
11 1 0
10 X X
K0XJ 0
Excitationtable
XQK 10
J1K1,J0K0
State Input X
Q1Q0 0 1
00 0X, 0X 0X, 1X
01 0X, X1 1X, X1
10 X1, 0X X0, 1X
11 X1, X1 X0, X0
Transferring onto K-maps to derive output equation
01 QQZ
J1K1,J0K0
State Input X
Q1Q0 0 1
00 0X, 0X 0X, 1X
01 0X, X1 1X, X1
10 X1, 0X X0, 1X
11 X1, X1 X0, X0
Output
Z
0
0
0
1
Excitation/output table
Circuit (logic) diagram
excitation equations output equation
J Q
Q
Q0Z
Q1'
Clk
J Q
Q
Q0J0
J1 Q1
X
01 QQZ XQJ 01 XK 1XJ 0 XQK 10
K0
K1
X'
K
K
Assigning state variable to obtain transition/output
table
Change of Encoding A = 00 B = 01 C = 11
Choosing D type flip flop
Next State Q1*Q0*, Z
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 11,0
11 00,0 11,1
Transition/output tableMealy machine
Constructing the excitation table
Excitation/output table
D1D0, Z
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 11,0
11 00,0 11,1
Mealy machine
Transferring onto K-maps to derive excitation
equations (Mealy Machine)State Input X
Q1Q0 0 1
00 0 0
01 0 1
11 0 1
10 X X
D1
State Input X
Q1Q0 0 1
00 0 1
01 0 1
11 0 1
10 X X
D0XQD 01
Excitation/output table
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 11,0
11 00,0 11,1
D1D0, Z XD 0
Transferring onto K-maps to derive output equation
(Mealy Machine)Excitation/output table
State Input X
Q1Q0 0 1
00 0 0
01 0 0
11 0 1
10 X X
ZXQZ 1
State Input X
Q1Q0 0 1
00 00,0 01,0
01 00,0 11,0
11 00,0 11,1
D1D0, Z
Circuit (logic) diagram
excitation equations
output equation
D Q
Q
Z
Clk
D Q
Q
Q0D0
D1 Q1
X
XQD 01XD 0
XQZ 1
Mealy machine
26
Example 1: State Diagram
• Design the FSM for the given state diagram– Graphical version of states, inputs, transitions and
outputs
Assigned state diagramAssigned state diagram
W
X Y
Z
State State assignmentassignment
Given state diagramGiven state diagram
27
Example 1: State Table
• For each current-state, specify next-state(s) as a function of the present inputs
• For each current-state, specify the output(s) as a function of the present inputs
We often use Q0, Q1, We often use Q0, Q1, Q2, etc. to acknowledge Q2, etc. to acknowledge that state variables are that state variables are F-F outputsF-F outputs
State VariablesState Variables
28
Example 1: Alternate State Table
• State table, alternate format emphasizing state transitions
• Notation: A → Q(t) and A+ → Q(t+1), used to indicate the change in state variable needed for the desired transition
Q1(t) Q0(t) Q1(t) Q0(t) →→ Q1(t+1) Q0(t+1)Q1(t+1) Q0(t+1)
a more a more descriptive descriptive
notationnotation
( )
Example 1: Flip-Flop Excitation Tables
• Use these tables to “move” Q to next state• Used to design the memory control CL circuit
29We will use the D F-FWe will use the D F-F
Example 1: Flip-Flop Excitation Tables
• Why are we are interested in the D Flip-Flop for this design?
30
Q(t) Q(t+1) D Operation 0 0 0 Reset 0 1 1 Set 1 0 0 Reset 1 1 1 Set
We select D Flip-Flops because the D input is We select D Flip-Flops because the D input is simply the value of Q(t+1) that we desiresimply the value of Q(t+1) that we desire
Example 1: Block Diagram
• We need to use two D flip-flops
• The sequential circuit would look as shown
• We will design the CL for a 3-input, 3-output circuit– CL for Output (y)– CL for Next State
controls (D1 and D2)
31
x y
inputs = x, Q1, Q2inputs = x, Q1, Q2outputs = y, D1, D2outputs = y, D1, D2
Q1
Q2
D1
D2
(output)
(next state)
Example 1: Truth Table
• The truth table for this 3-input, 3-output circuit can be generated from the original state table
• We will need to minimize each output function using Karnaugh maps, mindful of overlap
32
01234567
mintermsminterms
y
B+A+
Example 1: Karnaugh Maps• Minimizing each of the three outputs:
33
1 11 1 1
1 1 1
A+ = x ∙ Q1 + x ∙ Q2 B+ = x ∙ Q1
y = x ∙ Q1 + x ∙ Q2
A = Q1 and B = Q2
Example 1: Circuit Diagram
• The circuit that results from these equations is shown below:
34
A+ = x ∙ Q1 + x ∙ Q2
B+ = x ∙ Q1
y = x ∙ Q1 + x ∙ Q2
y = x ∙ (Q1 + Q2)
A+ = x ∙ (Q1 + Q2)
35
Design: Example 2• Given the state diagram as follows, design the
sequential circuit using JK Flip-Flops
A
B
C
D
A = 01B = 10C = 11D = 00
state assignment
36
Design: Example 2• Note that this is a state diagram for a Mealy machine
inputsinputs outputsoutputs
37
Design: Example 2• Block diagram, signal identification
We need to determine what
goes in here?
Input, x
1-bit
SequentialLogicCircuit
CP
KB = Ax + A’x’
38
Design: Example 2• From state table, get input flip-flop function
KB = Ax + A’x’
A xBxx B
x
39
Design: Example 2• Input flip-flop function
• Logic Diagram
Input, x
1-bit
CP
x
AB
JAKA
JBKB
01
0
A
0
B 0
0
0C
1
0
1
1
1C
1
0
101 overlap Moore machine
CLK
QA
QB
QC
QD
0 1 2 3 4 8 9 10 11 12 0
CLK
QA
QB
QC
QD
0 1 2 3 4 8 9 10 11 12 0
CLKCLK
QD
QA
QB
QC
5 6 7 8 9 10 11 12 13 14 5
LD
Initial Loading
Counting starts
Reloading
1110 Moore machine
0
10
A
0
B 10
C
0
1
0
D1
01
E0
01
0
43
44
Next State S*
State Input X
S 0 1
A A B
B A C0
C A C1
D A C1
Output
Z
0
0
0
1
D Q
Q
Q0
Z
Q0'
Q1
Clk
D Q
Q
Q0D0
D1 Q1
D Q
Q
D2 Q2
X
X'
46
Next State S*
State Input X
S 0 1
A A B
B A C0
C0 A C1
C1 A C1
Output
Z
0
0
0
1