Synchronization over packet-switching networks: theory and applications Raffaele Noro PhD exam...

Synchronization overpacket-switching networks:

theory and applications

Raffaele Noro

PhD exam

Lausanne, May 12th 2000

Institute for computer

Communications and

Applications (ICA)

Swiss Federal Institute

of Technology,

Lausanne (EPFL)

Synchronization over packet-switching networks:theory and applicationsRaffaele Noro, PhD exam, May 12th 2000

2

Outline Synchronization over packet-switching networks:

Needs and problems in packet-switching networks

Theory: Conventional solution: Phase-Locked Loops (PLLs)

Do not scale to packet-switching networks Proposed solution: Least-square Linear Regression (LLR)

Satisfies the new requirements

Applications: Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks

Conclusions

Introduction Theory Applications Conclusions


3

Synchronization over packet-switching networks

Synchronous Time Division Multiplexing Periodic, fixed-size frames

Global, static synchronization

Asynchronous Statistical Multiplexing Bursty traffic, variable delay

Point-2-point, dynamic synchronization

Packet-switchingnetwork

Circuit-switchingnetwork

Synchronousapplication




• Voice• Digital TV• …

• Voice• Digital TV• …

Application-specificsynchronization

Global to pt2pt

synchronization

Requirement of point-to-point synchronization: Synchronize the terminal clocks (fast, efficiently) even in the presence of (higher) transmission jitter



4

The problem of synchronization in packet-switching networks - part I

Network jitter Removed through the de-jittering buffer Controlled playout of data Optimal size: B= (max- min)· C

de-jitteringbuffer


Variable delay[min…max]

Constant delay


Generation Playout


5

The Network Time Protocol (NTP, [Mills ’92])provides only poor clock synchronizationguarantees (millisecond accuracy at best)

The problem of synchronization in packet-switching networks - part II

Physically dispersed clocks Clock drift f /f : speed of writing speed of reading (on average) Overflow (or underflow) of the de-jittering buffer Time-to-overflow (or underflow) depends on buffer size, bitrate, and drift

de-jitteringbuffer



Constant delay

Generation Playout

fC

BT

f /

Example: B= 10 kbits, C= 1 Mbps, f/f= 10-4

(10 ms of jitter absorption in the buffer)

TT= 100 seconds !!= 100 seconds !!



6

The problem of synchronization in packet-switching networks

Objective

Control and reduce to zero the clock drift within a convergence time shorter than the time-to-overflow: f /f 0 within t < T

de-jitteringbuffer



Constant delay

Generation Playout

fC

BT

f /



7







Conclusions



8

Timing of receiv.+ jitterdata

Synchronization of dispersed clocks

Timestamping of data flow1. Information about the timing of data

2. Information about the transmitter clock Processing of timestamps

Jitter limits the ability of the algorithm to reduce f /f to zero A convergence time is needed (… still not exceeding T )


Generation Playout

Synchalgorithm

Clock oftransmitter

Clock of receiver(free-running)

Synchonizedclock

Timing of transm.data

Timing of transm.(original)

cTx(t)

cRx(t)cTx(t)

Effect ofjitter and drift


Timestamps


9

State of the art: Phase-Locked Loops (PLLs)

Linear filtering of network jitter Proportional-Integrative (PI) loop filter Controlled frequency of the local oscillator (VCO) Feedback used to trigger an error signal

Characteristics of linear filtering For better accuracy narrower bandwidth With narrower bandwidth longer response time

VCO(pulse

generator)

Pulsecounter

Periodicpulses

Synchronized clocksignal

Loopfilter

+-

Controlsignal

Errorsignal

Phasecomparator

JitterReference clock

signal

cRxPLL(t)

xi

PLL Local clock

PLL synchronization algorithm



10

State of the art: Phase-Locked Loops (PLLs)

Accuracy

Performance budget

VCO(pulse

generator)

Pulsecounter

Periodicpulses

Synchronized clocksignal

Loopfilter

+-

Controlsignal

Errorsignal

Phasecomparator

JitterReference clock

signal

cRxPLL(t)

xi

PLL Local clock

PLL synchronization algorithm

2000 4000 6000 8000 10000

-0.02

-0.01

0

0.01

0.02

Relative frequency drift, Kp= 0.0015, Ki= 0.000005

Time (s)

Fre

quen

cy d

rift (

%) Network

jitter

Residual jitter

Convergence time

200 jitterresidual

jitternetworkd

005.00 timetransient

d

The performance budget of PLLs (here: 0.005)results below the expected performance budgetfor packet-switching (ex: 0.2)



11







Conclusions



12

x(t)= CRx(t)

x1, y

1

xN, y

N

y(t)= CTx(t)

Clock model: cTx(t)= a cRx(t)+ b[Mills, ’93; Cristian ‘89]

Estimation of (a, b) with the N last collected (x, y)

iiii

2iiiii

LLR

iiii

2

i2i

LLR

yxyxN

yxyxyb

yxyxN

yyNa

Recovered clock:cTx

LLR(t)= aLLR cRx(t)+ bLLR

Each cycle is triggered by the reception of one timestamp

Least-square Linear Regression (LLR): statistical filtering of network jitter



13

LLR circuitry and performance budget

Accuracy

d0 20

Performance budget

0.2

2000 4000 6000 8000 10000

-0.02

-0.01

0

0.01

0.02

Relative frequency drift, N= 1000, = 0.98

Time (s)

Fre

quen

cy d

rift (

%)

xi

âLLR

cRx(t)

yi

cTxLLR(t)

yi

yi2

xiyi

xi

aLLR

+

Mem.

Mem.

^2x

Mem. +

+

+

Mem. x

^2

xN

xN

+

+

-

--

-

-

-

x(1- ) +

x

+- x

+

Slope computationLow-pass filter

Timekeeping

Networkjitter

Residual jitter

Co

nv

erg

en

ce

time

The performance budget of LLR (here: 0.2) is1. Better than for PLLs (10 to 100 times)2. Supports the needs of packet-switching

applications Introduction Theory Applications Conclusions


14

Comparative perfomance of LLR and PLL

Choose the parameters of LLR (N, ), and of PLL (Kp, Ki)

trade-off between accuracy and rapidity The trade-off is much better with the LLR

Accuracy(jitter resilience capability)

Convergence time (s)

PLL: Accuracy/ Conv.time 0.05(nearly independent of )

100

0%

10

1000

90% 99% 99.9%

Region of interest forpacket-switching networks

10000

LLR: Accuracy/ Conv.time 0.25 / (= 0.1 s for this example)



15







Conclusions



16

Applications and synchronization (I):Circuit Emulation over IP networks

Objective Support of circuit-switched leased-lines (e.g., T1) with high-speed IP

backbones (e.g., optical IP)[ TDM-over-IP Forum, Geneva ‘99]

Relevance Seamless migration to IP backbones without interruption of legacy

services Transparent to the end-user Can be simpler than VoIP solutions

Contributions Definition of the functions Design of the protocol Performance assessment

Introduction Theory Applications — Application I: Circuit Emulation Conclusions


17

Applications and synchronization (I):Circuit Emulation over IP – definition of the functions

Emulation functions are allocated in a Circuit Emulation adapter

TDM traffic- Isochronous- Periodic

IPbackbone

TDM

LT

Circuit Emulation

LTIP

Circuit EmulationAdapter

User(e.g., T1/T3 leased lines)

IP Networkoperator

IP

Circuit EmulationAdapter • Jitter Removal • Clock recovery• Data structure handling

IP packets- Asynchronous- Aperiodic



18

Applications and synchronization (I):Circuit Emulation over IP – design of the protocol

Real-Time Protocol has been developed for real-time applications, including VoIP applications [Schulzrinne, ’96]

Native features include timestamping and sequencing Includes a control protocol – RTCP Extended features can be added

IP

UDP

RTP

PayloadRTP-H

PayloadRTP-HUDP-H

PayloadRTP-HUDP-HIP-H

Timestamping& Sequencing



19

Applications and synchronization (I):Circuit Emulation over IP – design of the protocol

Data timing, jitter removal timestamp Clock recovery source clock indication Data handling structure and spacing Session information RTCP messages

number unused...

contributing source (CSRC) id. #1

synchronization source (SSRC) id.

timestamp

V PX M

RTP packet

CC PT sequence number

indication (optional)

source clock

profile length

4 bytes

Payload ofConsecutiveData Units

Payload

Extensionheader

Fixedheader

…

structure spacing

d_max x

Other fields

RTCP message

SR extensionor

APP data



20

Applications and synchronization (I):Circuit Emulation over IP – design of the adapter

Scheduling

Packingpayload

idlenon-idle

Timestamp

StructureSpacing

Masterclock

Circuit Emulation adapter

RTPpackets

RTPpackets

payload

Timestamp

StructureSpacing

Timestamp

Circuit Emulation adapter

Packing

Slave clock(LLR/PLL)

Scheduling

Transmitter part

Receiver part Transmitter part

Receiver part

Leasedline

Leasedline


Timestamps+

Source clockindications Source clock

indications


21

Same nominal convergence time,more stable end-to-end delaywith LLR (and more stable bitrate)

Applications and synchronization (I):Circuit Emulation over IP – performance assessment

End-to-end delay and loss rate for: Best-effort service class Expedited forwarding service class Guaranteed service

Network jitter model: [Bolot, ‘93]

0 50 100 150

60

80

100

120

140

160

180

200

220

End-to-end delay for a LLR with N= 1200 and = 0.992

Time (s)

Del

ay (

ms)

Best Effort

Exp. Forwarding

Guar. Service


Convergence time= 100 s

End-to-end delay for a PLL with Kp= 0.05 and Ki= .0005

0 50 100 150

60

80

100

120

140

160

180

200

220

Time (s)

Del

ay (

ms)

Best Effort

Exp. Forwarding

Guar. Service



22

Same nominal convergence time,lower losses with LLR

Applications and synchronization (I):Circuit Emulation over IP – performance assessment

Loss rate (log scale) for a PLL with Kp= 0.05 and Ki= .0005

0 50 100 15010

-4

10-3

10-2

10-1

100

Time (s)

Loss

rat

e

Best Effort

Exp. Forwarding

Guar. Service


0 50 100 15010

-4

10-3

10-2

10-1

100

Loss rate (log scale) for a LLR with N= 1200 and = 0.992

Time (s)

Loss

rat

e

Best Effort

Exp. Forwarding

Guar. Service


23







Conclusions



24

Applications and synchronization (II)Synchronous AAL

Objective Tranport of statistically multiplexed Variable Bitrate (VBR) traffic in ATM

networks with constant end-to-end delay

[AAL-1; AAL-2; AAL-3/4; AAL-5]

Relevance Multimedia applications (Voice over ATM, video distribution)

Contributions Design of the protocol Performance assessment

Introduction Theory Applications — Application II: Synchronous AAL Conclusions

ATMswitch

ATMswitch

Constant delay

ATM layerSynch AAL

Application

ATM layerSynch AAL

Application

Variable delay


25

Applications and synchronization (II)Synchronous AAL – design of the protocol

CRCReserved

Application layer

Synchronous AAL

ATM layer

SSCS

CPCS (AAL-5)

SAR (AAL-5)

Padding Length

Synchronous AAL SDU

(AAL-5) CPCS PDU

TS

TS

4-byte timestamp addedby the synchronous AAL(in units of microseconds)

(AAL-5) CPCS SDU



26

Applications and synchronization (II)Synchronous AAL – design of the protocol

AAL SDU

Transmitterclock

Synchronous AAL(transmitter)

AAL-5 CPCS trailer

ATM cells payload

SSCS

CPCS

SAR

AAL-5 CPCS SDU

Self-synchLLR/PLL

Synchronous AAL(receiver)

AAL-5 CPCS trailer

ATM cells payload

SSCS

CPCS

SAR

AAL-5 CPCS SDU

Scheduling

AAL SDU

To the ATM network From the ATM network

AAL SDUTimestamp


Timestamp


27

Same nominal convergence time,lower loss with LLR during theconvergence time

Applications and synchronization (II)Synchronous AAL – performance assessment

Loss rate and rate discrepancy for: 376-byte AAL SDU 1 Mbps average rate Erlang jitter distribution

Network jitter model:[Parekh, ’93; Singh, ’94; …]

0 50 100 150 200 25010

-4

10-3

10-2

10-1

Loss rate (log scale) for a LLR withN= 10000 and = 0.9992

Time (s)

Loss

rat

e


Loss rate (log scale) for a PLL withKp= 0.05 and Ki= 0.00025

0 50 100 150 200 25010

-4

10-3

10-2

10-1

Time (s)

Loss

rat

e

Convergence time= 100 s Convergence time= 100 s


28

Same nominal convergence time,more stable rate with LLR duringthe convergence time

Applications and synchronization (II)Synchronous AAL – performance assessment



0 50 100 150 200 250-20

-15

-10

-5

0

5

10

15

20

Time (s)D

iffer

ence

of r

ate

(kbp

s)

Difference between output and input rateper each second of the session (PLL)

Average rate= 1 Mbps

0 50 100 150 200 250-20

-15

-10

-5

0

5

10

15

20

Difference between output and input rateper each second of the session (LLR)

Time (s)

Diff

eren

ce o

f rat

e (k

bps)

Average rate= 1 Mbps



29







Conclusions



30

Applications and synchronization (III)Digital TV services

Objective Synchronization of MPEG-2 systems over IP and ATM channels

[MPEG-2, ’94; Tryfonas ’99; …]

Relevance Penetration of Digital TV services Network-independence of MPEG codecs

Contribution Performance assessment

Distributionnetwork

DVD

Residentialuser

Receiver/decoder #1

Videoserver

Returnchannel

Stored material(films)

Live material(TV)

The electron beam of TVmust be in-sync with thevideo camera

Receiver/decoder #N

The decoder mustsynchronize to the server:- generation of TV signal- audio and video sync

Introduction Theory Applications — Application III: Digital TV services Conclusions

DVB: Video broadcast (cable, terrestrial and sat) VoD: Video-on-demand (interactive TV) PPV: Pay-per-view (pre-scheduled TV programs)


31

Applications and synchronization (III)Digital TV services– standardized protocol

Timestamping for: Intra- and inter-flow synchronization (DTS or PTS) Clock recovery and synchronization (PCR)

Mux

Programclock

Compression

Audio Video

Demux

Programclock

Decompression

AudioVideo

SynchLLR/PLL

Transmitter Receiver

PESpacketizer

PESdepacketizer

Transportnetwork

PCR PCR

PCR

PTS/DTS PTS/DTS

Audio and video part containPresentation TS referred to a

common timebase

The PC Referenceis used to reconstructthe common timebase



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Same nominal accuracy,faster convergence with LLR

Applications and synchronization (III)Digital TV services – performance assessment

Frequency reconstruction error of the System Clock 50 ms of network jitter PCRs inserted each 100 ms 20 parts-per-million (tolerance dictated by MPEG-2)

Network jitter model: [Andreotti, ’95; Noro, ’99; …]


Time (s)

Frequency error (log scale) of the recovered clockwith Kp= 0.002, Ki= 0.000001

1000 2000 3000 4000 5000

0.01

0.1

1

10

100

1000

Fre

quen

cy d

evia

tion

(par

ts-p

er-m

illio

n) Convergence time= 2000 s

Frequency error (log scale) of the recovered clockwith N=4000 and =0.99

Time (s)1000 2000 3000 4000 5000

0.01

0.1

1

10

100

1000

Fre

quen

cy d

evia

tion

(par

ts-p

er-m

illio

n)



33

ConclusionsAddressed problem

How to synchronize fast and efficiently dispersed clocks in the presence of network jitter – satisfy new needs of packet-switching

Contributions A solution based on LLR – overcomes limitations of conventional PLLs

Circuit Emulation over IP – support to legacy TDM leased-lines Synchronous AAL – transport of ATM traffic with constant delay Digital TV over packet-switching – distribution of MPEG-2 streams

Future work Standardization of Circuit Emulation in the Internet community (RFCs) Synchronization for mobile services Global synchronization for IP networks



34

Most relevant publicationsPatents1. ''Real-time remote inspection of high resolution images'', European Patent

n.EP946919A1, Issued Oct. 1999 2. R. Noro, J.P. Hubaux and M. Hamdi, ``Clock Synchronization over Data

Transmission Networks'', US Patent Application, filed July 1998, in progress 3. M. Hamdi, R. Noro and J.P. Hubaux, ``Fresh Packet First Scheduling for

Voice Traffic in Congested Networks'', US Patent Application, filed July 1998, in progress

Articles1. ''Circuit Emulation over IP Networks'', Proc. of the IFIP 6th International

Workshop on Protocols for High-Speed Networks, Salem- MA, USA, Aug. 1999

2. ''Clock Synchronization of MPEG-2 Services over Packet Networks'', Telecommunication Systems Journal, Baltzer Science Publisher, Vol. 11, Nos. 1- 2, Mar. 1999,

3. ''Improving Clock Synchronization for MPEG-2 Services over ATM Networks'', Proc. of the 4th Int. Workshop on Interactive Distributed Multimedia Systems, Darmstadt, Germany, Sep. 1997, pp. 176- 188

Seminars1. Design of a Circuit Emulation Protocol based on extended functionalities of

RTP, at the TDM over IP Forum, Geneva, Switzerland, Oct. 1999 2. Synchronization of Networks and Applications: a Survey, EPFL-SSC

Seminars Series, Lausanne, Switzerland, July 1999

Synchronization over packet-switching networks: theory and applications Raffaele Noro PhD exam...

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