Confidential Information

Reducing Regression Turnaround Time using

Multi-Snapshot Incremental Elaboration

Anantha Ramanand Garlapati, Cirrus Logic

Babak Zakeri, Cadence Design Systems

Confidential Information

Agenda

Problem Statement and Motivation

Introduction to MSIE

Application of MSIE to UVM based Verification Environments

Enhancements and Results

Conclusions and Future Work

24/29/2015

Confidential Information

Problem Statement

Complexity of Chips leading to

• Huge Regression Turn Around Time for

• full Chip RTL ,GATE and Mixed Signal Simulations.

• Work space needed for compile libraries

• typically GBs at Chip Level

• Different configurations of Design/Testbench

All the mentioned problems can cause

• A Barrier for productivity

• An Impact on the “Time to Market”

4/29/2015 3

Confidential Information

Motivation• At least 50%Reduce overall TAT for

Regressions

• A biggest bottle neck in Verification Execution.“Simulation Duration”

• Subsystems

• CHIP – RTL/GLS/MS.“one size fits all” solution for all

Verification levels

• Single Simulations

• RegressionsRe-usable flow

• Breaks entire regression if there are erroneous check-ins by test developers.Avoid the need for a Test library.

• Utilising the available options.No additional costs.

4/29/2015 4

Considering all these Opted for “MSIE”

Confidential Information

Introduction

to

Multi-Snapshot Incremental Elaboration

4/29/2015 5

Confidential Information

Traditional Simulation Flow

Compilation Phase

• All the source code including libraries are compiled.

Elaboration Phase

• Module instances are resolved, Parameters and macros processed, Timing info annotated, etc.

• Any change in the design, need to go through full elaboration. Repetitive in Regressions.

• A simulation image is created for the next step.

Simulation Phase

• Stimulating the design.

• Functional scenarios based on test.

4/29/2015 6

Confidential Information

MSIE flow at a Higher level

Partition the Design/Testbench

• Identify Unstable and Stable portions and partition them.

Primary Snapshots

• Major and Stable portions compiled – elaborated once to create primary snapshots.

Incremental Snapshots

• Compile - elaborate the unstable portion as Incremental snapshots and run the simulation.

4/29/2015 7

Confidential Information

Application of MSIE to UVM Based

Verification Environments

4/29/2015 8

Confidential Information

Testbench Partitioning

Primary Instantiating Incremental

• Most effective for regressions.

• Primary Snapshot : Ex: DUT+ most of UVM TB stable.

• Incremental Snapshot: Only small portion of test changing.

4/29/2015 9

Confidential Information

Customizing Testbench

TestBench

Partitioning

TB_Top

Primary Top

UVM Packages

DUT and other model

instances.

Test case Incremental

Top.

Package imports

run_test()

Href files

To handle OOMRs

Automation

Primary Snapshot

Incremental Snapshot

4/29/2015 10

1 2 3

Confidential Information

Multiple Primary SnapshotsR

equ

irem

ents

• Different configurations of the Design/Testbench.

• Use of multiple Third-party VIPS/UVCs.

• Gate level Corners with SDF annotation.

• Control macro enabled code in Primary Partition.

Solu

tio

n

• Create multiple primary snapshots.

• Ex:

• Normal [Default]

• Slimbus Enabled

• GLS_MAX

• GLS_MIN

• Automation for each simulation to point respective primary snapshot.

4/29/2015 11

Confidential Information

Enhancements & Results

4/29/2015 12

Confidential Information

Simulation Flow Enhancement at Cirrus with MSIE

4/29/2015 13

Compile Elaborate Simulation

Test

1Te

st1

00

0

Compile Elaborate Simulation

Test

2

Compile Elaborate Simulation

Test

3

Created 1000 Simulation Snapshots

Time

Legacy New

Compile Elaborate

Created “n” Primary Snapshots

Pro

gres

sio

n

Simulation

Incremental Snapshots

Simulation

Simulation

Test 1Test 2

Test 3

Regression Start TimeRegression Start Time

Pro

gres

sio

n

Time

Test1

00

0

Confidential Information

Overall Regression TAT

-- 30 Tests in Parallel.

4/29/2015 14

Mode of Design Overall Duration[Legacy]

Overall Duration[MSIE]

% Improvement

CHIP RTL[1000 Tests]

~24 Hrs ~12 Hrs 50%

CHIP GLS[140 Tests – Min & Max]

~23 Hrs ~11 Hrs 52.1%

CHIP MS[325 Tests]

~9 Hrs ~4Hrs 55.55%

Confidential Information

Improvement in Elaboration Time

4/29/2015 15

Single Simulation Statistics

Mode of Design AverageElaboration Time

[Legacy]

Average Elaboration Time

[MSIE]

% Improvement

CHIP RTL - Normal 820s 11s 98.6%

CHIP RTL – Slimbus 1006 9s 99%

CHIP GLS [Min and Max]

1262s 25s 98%

CHIP MS 720s 9s 98.75%

Confidential Information

Additional Advantages Runtime disk Memory Consumption with each Test

Enables more parallel simulations running without memory crashes.

4/29/2015 16

Mode of Design Disk space[Legacy]

Disk space[MSIE]

CHIP RTL 1.5GB 10MB

CHIP GLS 2GB 17MB

CHIP MS 1.3GB 9MB

Reduced load on the computing farm in proportion to the TAT

saving.

Confidential Information

Conclusions and Future Work

4/29/2015 17

Confidential Information

Conclusions

Successfully utilised in couple of Projects.

Achieved a Partition approach which works for all levels of verification.

Significant reduction in the regression TAT.

•Overnight regressions.

Primary Snapshots re-used for both Single simulations and regressions.

4/29/2015 18

Confidential Information

Future Work

Extend MSIE to CPF simulations.

Make MSIE a default flow for all Projects.

4/29/2015 19

Confidential Information

Thank You

Queries…!!

4/29/2015 20