svenk/mikrodatorsystem/HC11/... · The MC68HC11 MICROCONTROLLER Applications of Microcontrollers...

TheMC68HC11Microcontroller

LectureOverheads

SokolSalius

ChalmersLindholmen

September2,2003

CHALMERSLindholmen

TheMC68HC11MICROCONTROLLER

Whatwouldwelearnabout?

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◦I.INTRODUCINGMICROCONTROLLERTECHNOLOGY

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1.MicrocontrollerConcepts.

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◦II.SOFTWARE

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◦II.SOFTWARE

2.Programming.

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◦II.SOFTWARE

2.Programming.

3.TheStack,Subroutines,Interrupts,andResets.

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◦II.SOFTWARE

2.Programming.


4.CrossAssemblyandProgramDevelopment.

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◦II.SOFTWARE

2.Programming.



◦III.HARDWARE

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◦II.SOFTWARE

2.Programming.



◦III.HARDWARE

5.BusConceptsandModesofOperation.

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◦II.SOFTWARE

2.Programming.



◦III.HARDWARE


6.MicrocontrollerHardware.

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◦II.SOFTWARE

2.Programming.



◦III.HARDWARE


6.MicrocontrollerHardware.

7.ClockedOperation.

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Whatmore?

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Whatmore?

◦IV.INTERFACING

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Whatmore?

◦IV.INTERFACING

8.InterfacingConcepts.

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Whatmore?

◦IV.INTERFACING


9.ParallelInput/Output.

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Whatmore?

◦IV.INTERFACING



10.SerialSubsystems.

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Whatmore?

◦IV.INTERFACING




11.ProgrammableTimerOperations.

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Whatmore?

◦IV.INTERFACING





12.TheAnalogConverterSubsystem.

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Whatmore?

◦IV.INTERFACING





12.TheAnalogConverterSubsystem.

13.ApplicationsControlSoftware.

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ApplicationsofMicrocontrollers

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◦ConsumerElectronic

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(Automotiveanti-theftsystemusingRFID)

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◦MedicalMonitoringDevices

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(Abeltthatmeasuresaperson’sheartrateandrespiration—whenoutofsafelimitsa

RFsignalistransmittedtoamicrocontroller/pager)

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◦SecuritySystems

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◦SecuritySystems

(An”intelligent”phonethatreceivesradiosignalsfromsmokealarms,intrusion

sensors,andpanicswitchestoalertacentralmonitoringstation)

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◦SecuritySystems



◦EnvironmentalControls

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◦SecuritySystems




(Controlsystemthatcontrolstheheating,ventilating,andairconditioninginlarge

buildingstominimizepeakenergydemands.)

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◦SecuritySystems






◦ClosedLoopProcessControls

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◦SecuritySystems







(Afuelcontrolsystemthatmonitorsandcontrolstheflowoffueltoaturbinejet

engine)

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◦SecuritySystems








engine)

◦DesktopPC

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◦SecuritySystems








engine)

◦DesktopPC(multipleembeddedprocessorsinthekeyboard,printer,themodem,and

evenintheCRTmonitor!)

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SomeApplicationsofMC68HC11

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◦Transmissionandenginecontrolmodules(Chrysler)

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◦Digitalinstrumentsclusters(Ford)

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◦Driveandemissioncontrol(JeepCherokee)

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◦Automaticcameras(CanonEOSmodel)

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◦Harddiskcontroller(Conners,Inc.)

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◦Harddiskcontroller(Conners,Inc.)

◦Skibindingtoreducekneeinjuries(Fiock),etc.

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CPUBlockDiagram

CPU

Clock

ControlSequencer

Arithmetic &Logic Unit

Internal Data B

us

InstructionDecoder

CPU Registers

Program Counter

Address Register

ALU

Data Driver

External Address BusExternal Data Bus

SP

Control signals

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MC68HC11insinglechipandexpandedmode

I/O Controland StatusRegisters

ROM

RAM

EPROM/EEPROM

I/O Registers

Internal Bus

I/O Ports

clock

controllines

Vss

Vpp

CPU

I/O Controland StatusRegisters

ROM

RAM

EPROM/EEPROM

Internal Bus

clock

controllines

Vss

Vpp

CPU

DataBuffer

AddressLatch

Address/Data Bus

Address Bus

Single-chipmodeExpandedmode

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SimplifiedBlockDiagramofMC68HC11E

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timer &counter system

CPU coreserial I/O

A/Dconverters

Port A

Port BPort CPort D

Port E

Handshake I/O

Address/Data bus

PWM/Other Ports

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DemultiplexingofAddress/DataBus

LEOE

AS

AD0-AD7

A8-A15

A0-A7

D0-D7

A8-A15

74HC373

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DeviceRAMROMEPROMEEPROMCOMMENTS

MC68HC11A82568K051216-bitTimer,8-bitA/D,SCI,SPIMC68HC11A125600512”

MC68HC11D319204K016-bittimer,SCI,SPIMC68HC11D01920”

MC68HC11E951212K051216-bitTimer,8-ChA/D,SCI,SPIMC68HC711E9512012K512”MC68HC11F1102400512Nonmultiplexedbus,8channel8-bitA/D,4

chipselects,SCI,SPIMC68HCG751224K00Nonmultiplexedbus,8channel10-bitA/D,4

channelPWM,SCI,SPI,66I/OpinsMC68HCM212800K32K640Nonmultiplexedbus,8channel8-bitA/D,

4channelPWM,DMA,On-chipmathcoprocessor,SCI,2SPI

MC68HC11N476824K0640Nonmultiplexedbus,12-channel8-bitA/D,2

channel8-bitD/A,6channelPWM,On-chipmathcoprocessor,SCI,SPI

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µControllertoµProcessor

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PROsCONs




PROsCONs

FewerchipsrequiredReducedflexibility




PROsCONs


Lowercost,smallersizeLimitedexpansion




PROsCONs



LowerpowerLimitedperformance




PROsCONs




MoreuserI/OpinsLimitedI/O




PROsCONs





SimplerdesignTradeofftofitallinachip




PROsCONs






Fewerconnections




PROsCONs






Fewerconnections

Higherreliability



Memorymapofthe68HC11A1/A8

$0000

$1000

$00FF

$B7FF

$103F

$B600

$FFFF

$E000

NA

NAExternal

External

External

256-Byte RAM

64-ByteRegister Block

512-ByteEEPROM

Single Chip ExpandedMultiplexed

BF40BFFF

BootloaderROM

Specialbootstap mode

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NA

*ROM can be disabled by ROMON bit in CONFIG

**MC68HC11A8 delivered with ROM disabled

* **

8-K ROM



Memorymapofthe68HC711E9

$0000

$1000

$01FF

$B7FF

$103F

$B600

$FFFF

$D000

Not available

External

External

External

512-Byte RAM

64-ByteRegister Block

512-ByteEEPROM

12-KB ROM

Single Chipmode

Expandedmode

Not available

Not available

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PARTII

MachineLevels

↑I5ApplicationprogramL5↓

↑I4HLLcompiler-interpreterL4↓

↑I3ASMLanguageL3↓

↑I2OperatingsystemL2↓

↑I1Micro-programL1↓

↑I0ElectroniccircuitL0↓



PARTII

MachineLevels







Architecturedefinesthefunctionalappearancetotheuser



PARTII

MachineLevels








Processorarchitectureisdefinedastheinterfacebetweenhardwareandsoftware,(I1).



PARTII

MachineLevels









LevelsL3,L4,andL5areconsideredvirtualmachines;



PARTII

MachineLevels









LevelsL3,L4,andL5areconsideredvirtualmachines;L5iswhatmostuserusersee



MachineLevels(cont.)

High Level

Assembly

Machine

RegisterTransfer

Gate

Circuit

Sum : = Sum+1

LDAA SUM INCASTAA SUM

10000110 10100000 0100 11001001 0111 10100000

Fetch Intruction Increment PC Load ALU with SUM ...

D

CLK

Q



FromSourcetomachinecode

AssemblyLanguage

High-levelLanguage

Assembler

Machine Code

Compiler

To ComputerMemory

Object Code

Languagesshapethewaythinkand

determinewhatwecanthinkabout.

L.Dwarfaboutnaturallanguages



Programmer’sModelofMC68HC11

A,B

D

X

Y

SP

PC

0 07 7

15

15

0

8-bit accumulators A and B or 16-bit(double) accum D

index register X

index register Y

stack pointer

program counter

0

0

0

0

15

15

15

0 7

condition code register CCR

S X H I N Z V C

carry/borrow (from MSB)

overflow zero

negative

I-interrupt mask half carry (from bit 3)

stop disable

X-interrupt mask

CCR



InstructionSet

iAccumulatorandMemoryInstructions1

1twooperands—onefromanaccumulatororindexregistertheotherfrommemory



InstructionSet


◦loads,storesandtransfers:




InstructionSet



CLR,CLRB,LDAA,PSHA,PULB,STAB,STD,TAP,TBA,XGDY,etc.




InstructionSet




◦arithmeticoperations:




InstructionSet





ABX,ADCB,CMPB,DECA,NEGB,INCB,SUBD,TSTA,etc.




InstructionSet






◦multiplyanddivide:




InstructionSet







MUL,FDIV,IDIV




InstructionSet







MUL,FDIV,IDIV

◦logicaloperations:




InstructionSet







MUL,FDIV,IDIV


ANDA,ANDB,COM,COMA,EORA,ORAB,etc.




InstructionSet







MUL,FDIV,IDIV



◦datatestingandbitmanipulations:




InstructionSet







MUL,FDIV,IDIV




BITA,BITB,BCLR,BSET,BRCLR,BRSET




InstructionSet







MUL,FDIV,IDIV





◦shiftsandrotates:




InstructionSet







MUL,FDIV,IDIV





◦shiftsandrotates:

ASLD,ASRA,LSLB,LSRA,ROLA,RORB,etc.1twooperands—onefromanaccumulatororindexregistertheotherfrommemory



iiStackandindexregistersinstructions




◦ABX,CPY,DES,DEY,INX,LDX,PULY,PHSX,TSX,TYS,XGDX,etc.

iiiConditioncoderegisterinstruction






◦CLS,CLI,CLV,SEC,SEI,SEV,TAP,TPA

ivProgramControlInstructions








◦branches:








◦branches:

BCC,BCS,BGE,BHI,BLO,BLS,BMI,BNE,BRCLR,BRSET,BVC,etc.








◦branches:


◦jumps:








◦branches:


◦jumps:

JMP








◦branches:


◦jumps:

JMP

◦subroutinecallsandreturns:








◦branches:


◦jumps:

JMP


BSR,JSR,RTS








◦branches:


◦jumps:

JMP


BSR,JSR,RTS

◦interrupthandling:








◦branches:


◦jumps:

JMP


BSR,JSR,RTS


RTI,SWI,WAI








◦branches:


◦jumps:

JMP


BSR,JSR,RTS


RTI,SWI,WAI

◦miscellaneous:








◦branches:


◦jumps:

JMP


BSR,JSR,RTS


RTI,SWI,WAI

◦miscellaneous:

NOP,STOP,TEST



Addressingmodes

◦inherentCLRA2

◦immediateLDX#$10003

◦extendedaddressingSTAA$10004

◦directaddressingSTAA$205

◦indexedaddressingLDAB$5,X6

◦relativeBRA$0C7

2datais”inherent”toCPU,noexternaladdressisneeded3datalocated’immediately’intheinstruction4the16-bitaddressoftheamemorybyteisspecifiedintheinstruction5the8-bitaddress($00–$FF)—256byteschip’sRAM—oftheamemorybyteisspecifiedintheinstruction6the(effective)addressisobtainedfromthecontentofregisterXplustheoffset,inthiscase57locationisspecifiedbyanoffsetfromtheaddressoftheinstructioncurrentlybeingexecuted



addressopcode*addressingmodes

1000ORG$1000

*Immediate

10008E00FFLDS#$FF1003C680LDAB#$80

1005CEC000LDX#$C000

*Extended

1008B700C0STAA$C0

*Direct100B97C0STAA>$C0

*Indexed100DE300ADDD0,X

100F18A703STAA3,Y

*Inherent

10121BABA101308INX

*Relative

10142000PREVBRANEXT101622FCNEXTBHIPREV

10182402BCCOK101A20FEHANGBRAHANG

*Absolute101C7ED000OKJMP$D000



*Illustrationofaddressingmodes

QA11-MC68HC11Absolutecross-assembler,Version1.0

(c)GMV1989-2002

File:addmodes.lst

1.*Illustrationofvariousaddressingmodes

2.

3.*--------------------------------------------

4.*inherentaddressingmode

5.

10006.ORG$1000startaddressoftheprogram

7.

10004F8.CLRA0->A

10015C9.INCBB+1->B

1002188F10.XGDYD<->Y

1004180911.DEYY-1>Y

12.

13.*---------------------------------------------

14.



15.*Immediatemode

1006864C16.LDAA#$4C$4C->A

10088B0217.ADDA#$02A+2->A

100AC61718.LDAB#$17$17->B

100C1B19.ABAA+B->A(inherent)

20.

21.*DirectendExtendedmode:

22.*Directmode

23.*Transfersdatafromaddress$20toaddress$30

24.

100DB6002025.LDAA>$20$(20)->A

1010B7003026.STAA>$30A->(30)

27.

28.*Extendedmode

29.*Transfersdatafromaddress$2000toaddress$3000

30.

1013B6200031.LDAA$2000($2000)->A

1016B7300032.STAA$3000A->($3000)

33.

1019B6200134.LDAA$2001($2001)->A

101CB7300135.STAA$3001A->($3001)

36.*...



37.

38.*---------------------------------------

39.*Indexedaddressing

101FCE200040.LDX#$2000$2000->X

102218CE300041.LDY#$3000$3000->Y

1026A60042.LOOPLDAA0,X(X+0)->A

102818A70043.STAA0,YA->(Y+0)

102B0844.INXX->X+1

102C180845.INYY->Y+1

46.*...

102E20F647.BRALOOPLOOP->PC



Keyboardinterface

ML4EQU$1400LEDindicator

ML2EQU$100Keyboardstatus/dataregister(ML2/ML15)

*%10000000nokeypressed%0xxxxxxxkeypressed(7bitdata)

KEYBS1PSHB

LOOPDLDAAML2readstatus/dataregister

CMPA#$80isanykeypressed?

BEQLOOPDifnotkeeppolling

otherwisesAcontainsthecodeofkeypressed

STAAML4fortestpurposetovisualizeAcontent

LOOPULDABML2

CMPB#$80isthekeyreleased?

BNELOOPUifnotkeeppolling

PULB

RTS



Programmingconstructs



Programmingconstructs

*----------------------*----------------------

if...else...*do...while...

*----------------------*-----------------------

......

BEQCTif(conditionequalTRUE)LDAB#10

*elseDOWLDAA$0,Xreadfrom

CFLDAB#’F’setFALSEflagSTAA$0,Ymoveto

BRASKIPINX

INY

CTLDAB#’T’setTRUEflagDECBnext

SKIPBNEDOWwhileB<10

......



"ConditionalJump"Construct

*--------------------------------

*Example:"JNELABEL"

*(nosuchinstructionexistsonHC11)

*--------------------------------

CBACompareAtoB

*--------------

BEQCONT

JMPLABEL"JNE"LABEL

CONT

*--------------

...

LABEL

...



DataTestingandBitManipulation

◦Data(Bit)testing:




◦Data(Bit)testing:–BITAM,BITBM(operation:ACCx·M)

◦Bitmanipulations:





◦Bitmanipulations:–BSETMmask(operation:M←M+mask)






–BCLRMmask(operation:M←M·mask)

◦Example:







◦Example:

–BSET$1000,X$07







◦Example:

–BSET$1000,X$07

xxxxx111←xxxxxxxx+00000111







◦Example:

–BSET$1000,X$07


–BCLR$1000,X$̃07($F8)







◦Example:

–BSET$1000,X$07


–BCLR$1000,X$̃07($F8)

xxxxx000←xxxxxxxx·11111000



Branchinstructionsbasedonbitsvalues




◦BRSETMmask(M·mask==0)





◦BRCLRMmask(M·mask==0)

◦Example:






◦Example:

–BRSET$1000,X$07






◦Example:

–BRSET$1000,X$07

xxxxxxxx·00000111=00000xxx






◦Example:

–BRSET$1000,X$07


–BRCLR$1000,X$07



NormalExecution,Reset,Interrupts



NormalExecution,Reset,Interrupts

Power on reset Initialisationroutines

Main program

***

*


Main program

Subroutine

JSR address *

**

**

**

RTS

*




Main program

Reset

***

*


Main program

Interrupt

Interrupt ServiceRoutine

precoded/prespecified memory locations

***

*

*

*RTI

*

*



ResetsandInterrupts



◦Resets:

◦Resets:

-Poweronreset(POR)

◦Resets:

-Poweronreset(POR)

-RESET

◦Resets:

-Poweronreset(POR)

-RESET

-Clockmonitorfail

◦Resets:

-Poweronreset(POR)

-RESET

-Clockmonitorfail

-COPfail◦Resets:

-Poweronreset(POR)

-RESET

-Clockmonitorfail

-COPfail

◦Non-maskableInterrupts:

◦Resets:

-Poweronreset(POR)

-RESET

-Clockmonitorfail

-COPfail


-XIRQ

◦Resets:

-Poweronreset(POR)

-RESET

-Clockmonitorfail

-COPfail


-XIRQ

-Illegalopcode(ILLOP)

◦Resets:

-Poweronreset(POR)

-RESET

-Clockmonitorfail

-COPfail


-XIRQ

-Illegalopcode(ILLOP)

-Softwareinterrupts(SWI)

◦Maskableinterrupts8


-Timeroverflow


-Timeroverflow

-PACoverflow,


-Timeroverflow

-PACoverflow,PACinputedge


-Timeroverflow


-SPItransfercomplete


-Timeroverflow



-SCISerialsystem


-Timeroverflow



-SCISerialsystem

-IRQ


-Timeroverflow



-SCISerialsystem

-IRQ

-RTII


-Timeroverflow



-SCISerialsystem

-IRQ

-RTII

-TIC1–3


-Timeroverflow



-SCISerialsystem

-IRQ

-RTII

-TIC1–3

-TOC1–5



8,

Maskableinterruptsmainlygeneratedbyon-chipperipherals.,

Maskableinterruptsmainlygeneratedbyon-chipperipherals.,Havefixedinterruptpriorities.

Maskableinterruptsmainlygeneratedbyon-chipperipherals.,Havefixedinterruptpriorities.Anyinterruptcanbeelevatedto

thehighestpriority.

Maskableinterruptsmainlygeneratedbyon-chipperipherals.,Havefixedinterruptpriorities.Anyinterruptcanbeelevatedto

thehighestpriority.TIC1–3,PAC,IC,STRA/AScanbeconfiguredasexternalinterrupts(insingle-chipmode).



AddressvectorInterruptsourceCCRmaskLocalmask

FFD6SCIIbitTIE/TCIE/RIE/ILIE

FFD8SPIIbitSPIEFFDAPAIEIbitPAII

FFDCPAOIbitPAOVI

FFDETOFIbitTOIFFE0TOC5IbitOC5I

FFE2TOC4IbitOC4IFFE4TOC3IbitOC3I

FFE6TOC2IbitOC2IFFE8TOC1IbitOC1I

FFEATIC3IbitIC3IFFECTIC2IbitIC2I

FFEETIC1IbitIC1IFFF0RTIIbitRTI

FFF2IRQIbitNone/STAIFFF4XIRQXbitNone

FFF6SWINoneNoneFFF8ILLOPNoneNone

FFFACOPNoneNOCOPFFFCCLMNoneCME

FFFERESETNoneNone



MappingsofInterrupts

________________________________________________________________________

*BUFFALO’svectormapping*Uservectorinitialization

...xxxxLDX#TOF_ISR

FFDEVTOFFDBJTOF*TOFinterruptvectorxxxxSTX$3FDE

..._______________________________

FFFCVCMFFDBJCMF*CMFResetVector*UserInterruptServiceRoutine

FFFEVRSTFDBBUFFALO*ResetVectorTOF_ISR

________________________.

PseudovectorsinRAM.

...

EE41JTOFLDX$3FDE.

EE44JMP0,XRTI

__________________________________________________________



PARTIII

I/0INTERFACES/SUBSYSTEMS



PARTIII


◦ParallelInput/Output



PARTIII


◦ParallelInput/Output–SimpleparallelI/O



PARTIII



–HandshakeparallelI/O



PARTIII




◦TheSerialSubsystems



PARTIII




◦TheSerialSubsystems–SerialCommunicationInterface



PARTIII





–SerialPeripheralInterface



PARTIII






◦ProgrammableTimers



PARTIII






◦ProgrammableTimers–Outputcompare



PARTIII







–Inputcapture



PARTIII







–Inputcapture

–Pulseaccumulator



PARTIII







–Inputcapture

–Pulseaccumulator

–Real-timeinterrupt



PARTIII







–Inputcapture

–Pulseaccumulator


◦A/Dconverter



PARTIII







–Inputcapture

–Pulseaccumulator


◦A/Dconverter

◦Othersubsystems



ProgrammableTimerOperations




◦Timersubsystemfunctions/modules




◦Timersubsystemfunctions/modules–Outputcompare





–Inputcapture





–Inputcapture

–Pulseaccumulator





–Inputcapture

–Pulseaccumulator,also





–Inputcapture


RTII(realtimeinterrupt)





–Inputcapture



COP(computeroperatingproperly)





–Inputcapture




◦Applications





–Inputcapture




◦Applications–DecisionsinRealtime





–Inputcapture





–Precisetimingofevents





–Inputcapture





–Precisetimingofevents,e.g.





–Inputcapture






(i)timemeasurementofinputevents,





–Inputcapture







(ii)timingofoutputevents





–Inputcapture








–Countingofevents





–Inputcapture








–Countingofevents

–Periodicrealtimeinterrupts





–Inputcapture








–Countingofevents

–Periodicrealtimeinterrupts

–Watchdog



PortApins

IC3

IC2

IC1

OC5/OC1

OC4/OC1

OC3/OC1

OC2/OC1

PAI/OC1

PA0

PA2

PA1

PA3

PA4

PA5

PA6

PA7



MainTimer&andRealTimeInterrupt

TCNTTCNT (HI)(LO)16 bit free-running counter

TOI

TOF

Prescaler1,4,8,or 16

PR1 PR0

MCU E clock

16-bit timer bus

Interruptrequest



TimerOutputcompare&Inputcapture

TOCTOC (HI)(LO)16-bit compare

OCxF

OCxI

FOCxOCx

16-bit timer bus Interruptrequest



TimerOutputcompare&Inputcapture

TOCTOC (HI)(LO)16-bit compare

OCxF

OCxI

FOCxOCx

16-bit timer bus Interruptrequest

Interruptrequest

TICTIC (HI)(LO)

16-bit latchICxF

ICxI16-bit timer bus

ICx



OC&ICApplications



OC&ICApplications

t tp

t tw

(a)(b)

Figure1:(a)periodic/pulsewaveformgenerationand(b)period/pulse-widthmeasurement



Timersubsystem’scontrolandstatusregisters



Timersubsystem’scontrolandstatusregisters

Miscellaneous Timer Interrupt FlagRegister 2

OM2OL2OM3OL3OM4OL4OM5OL5

1B 1A 2B 2A 3B 3A

OC1IOC2IOC3IOC4IOC5IIC1IIC2IIC3I

TCTL1

TMSK1

TCTL2

TFLG1OC1FOC2FOC3FOC4FOC5FIC1FIC2FIC3F

TMKS2TOIRTIIPAOVIPAIIPR1PR0

TFLG2TOFRTIFPAOVFPAIF

Main Timer Interrupt Mask Register 1

Main Timer Interrupt Flag Register 1

Miscellaneuos Timer Interrupt MaskRegister 2

Timer Control Register 2



EDG4B 4A

00

00

RTR1RTR0

OPTIONCR1 CR0

PACTLDDR7PAENPAMODPEDGE00

00



Typicaltimersoftwaresequence




◦Configurethecontrolregisters





◦Writetothedataregister(ifrequired)






◦Waitforaflagtobeset







◦Cleartheflag







◦Cleartheflag

◦Readorwritedataasrequired







◦Cleartheflag

◦Readorwritedataasrequired

◦Repeatifdesired



RatesSelection

PR1 PR0

Timer prescaler

500 ns/ 32,77ms2 us /131.1 ms4us /262.1 ms 8us /524.3 ms

RTR1 RTR0

RTI rate selects

4.10 ms8.19 ms16.38 ms32.77 ms

resolution/overflow

CR1 CR0

COP time out

16.384 ms65.536 ms262.14 ms1.049 s

E-clock 2 MHz

TMSK2PACTLOPTION

00011011



OutputCompare



OutputCompare

1

OOO1O11

OMxOLxNo outputToggle outputDrive output lowDrive output high

TCTL1

OCxF

GenerateInterrupt

OCxIInterrupt Enable

x =2,3,4,5

OCx output

OC1M

OC1D

On succesful compare on TOC1 thedata in OC1D are output to selected(OC1M) lines (PA3--PA7)

AdditionalregiistersOC1's



Oneshotpulse

*10msone-shotpulse*(E=2MHz,pre-scale1)

PWIDTHEQU$2000*WaitfortriggerbypollingforOC2Fhigh

BASEREGEQU$1000PULSE1

ORG$2000BRCLRTFLG1,X,$40,PULSEnowoutputlow

LDX#BASEREGBCLRPORTA,X,$40clearlatchforPA6

LDDTCNT,XPreventLDAA#$40

STDTOC2,XprematureOCSTAATFLG1,XclearOC2F

BSETPORTA,X,$40PA6/OC2highBCLRTCTL1,X$80disconnectOC2

LDAA#$80OKBRAOK

STAATCTL1,Xdriveoutputlow

LDAA#$40

STAATFLG1,XclearOC2Fisset

LDDTCNT,X

ADDD#PWIDTH-17

STDTOC2,X



OC1example

*Thefollowingcodewouldgeneratesthepattern0xx11(outofpinsPA7,PA4,PA3)

*onasuccessfulTOC1compare.UsesOC1MandOC1Dregisters

LDX#BASEREG

BSETPACTL,X,$80*MakesPA7output

LDAA#$98

STAAOC1M,XsetsOC1Mbits7,4,3(clearstheothers)

*anddrivesPA4,3high,PA7low

LDAA#$18setsOC1D4,3,clearsOC1D7

STAA$OC1DX

BSETTMSLK1,X$80*EnablesOC1Iinterrupt

CLI

...



ICCapture



ICCapture

1

OO

O

1O

11

EDGxBTCTL2

EDGxA ICx input

none

ICxF



Measurementofpulsewidth

*betweenrisingandfallingedgesonIC1

ORG$2000POLLFALL

LDX$1000RegisterbaseBRCLRTFLG1,X$04POLLFALL

LDAA#$10LDDTIC1,X

STAATCTL2,XtocapturesrisingedgeSUBDRISETIME

LDAA#$04STDPULSEWIDTH

STAATFLG1,XclearIC1FflagifsetAGNBRAAGN

POLLRISERISETIMEFDB$0000

BRCLRTFLG1,X$04POLLRISEPULSEWIDTHFDB$0000

LDDTIC1,X

STDRISETIME

LDAA#$20

STAATCTL2,Xtocapturefallingedge

LDAA#$04

STAATFLG1,XclearflagIC1Fifset



PAEventCountingmode

PA7/OC18-bit counter

8-bit counter

Input edgedetection

PEDGE

01

PACTL PAinput

PAOVI

PAOVF

PAII

PAIF

Interrupt

TMSK2

TFLG2

TFLG2

TMSK2

Event counting(PAMOD = 0)

Interrupt



PATimeAccumulationmode

PA7/OC1

Clock

8-bit counter

8-bit counter

Input edgedetection

PEDGE

01

PACTLPA input

PAOVI

PAOVF

PAII

PAIF

InterruptTMSK2

TFLG2

TFLG2

TMSK2

Gated time accumulation (PAMOD = 1)

Interrupt

E/64 Clock



PA-relatedregisters/bits



PA-relatedregisters/bits

COP timer

TMSK2

TOF RTIF PAOVF PAIF 0 0 0 0 TFLG2

RTR1 RTR0 PAEN PAMOD PEDGE 0 0 PACTL

TOI RTII PAOVI PAII 0 0 PR1 PR0

DDR7

COP timer

Bit 7Bit 0 PACNT



PAincountingmode

ORG$4000

INIT_PACMODEPAOVF_ISR

*PAEN1,PEDGE0,PAMODE0BCLRTFLG2,X~$20*i.e.$DF

BSETPACTL,X$40BCLRTMSK2,X$20*disbleinterrupt

RTSJSRSTOP_PAINT

RTI

PA_Count

*numberofcarstobepaintedinA

BCLRTFLG2,X~$20*ClearPAOVF

BSETTMSK2,X$20*EnablePAOVI

NEGA*Twoscomplementofcount

STAAPCNT,X

CLI

RTS



RealTimeInterrupts

FCNTEQU244NumberofRTItomakeasecond

INITRTI

LDD#$0000

STDSECF

BCLRFLAG2~$40ClearRTIF

BSETTMKSK2$40EnableRTIinterrupts

RTS

RTI_ISR*interruptserviceroutineSECHCLRSECF

BCLRFLAG2,~$40ClearRTIFCLRSECF+1

LDYSECFLDYSECC

INYINY

STYSECFSTYSECC

CPY#FCNTRTI

BEQSECHSECFFCB$00secondfractions

RTISECCFCB$00secondscounts



COPtimer.Servicing

.

.

LDAA#$55

STAACOPRSTarmstheCOPtimerclearingmechanism

.

.

*Timecriticalcode

*tobeenteredherebetween

.

.

LDAA#$55

STAACOPRSTclearstheCOPtimer



ParallelInput/Output




◦GeneralPurposeI/O




◦GeneralPurposeI/O–I/OisdonebysimplyreadingorwritingtoI/Oports





–AllfiveHC11ports(A,B,C,DandE)canbeusedforgeneral(simple)I/O






–Eachporthasacorrespondingdataregister,PORTA,PORTB,PORTC,PORTD

andPORTE







andPORTE

–BidirectionalportsDandChavecorrespondingdatadirectionregistersDDRCand

DDRD







andPORTE


DDRD

◦StrobedandFull-HandshakeI/Omodes







andPORTE


DDRD

◦StrobedandFull-HandshakeI/Omodes–PortCalternatelatchedregister(PORTCL)







andPORTE


DDRD


–ParallelI/OcontrolregisterPIOC







andPORTE


DDRD



–STRAinputpin(relatedtoPORTCL)







andPORTE


DDRD



–STRAinputpin(relatedtoPORTCL)

–STRBoutputpin(relatedtoPORTB)



GeneralPurposeI/O



GeneralPurposeI/O

1

0

111

00

01

0

1

DDRCPORTC+5v

0

Off

On x

xx

x

6K2

6K2

6K2

6K2

CMOS sinking 1.6 ma

Drivers



GeneralPurposeI/O

1

0

111

00

01

0

1

DDRCPORTC+5v

0

Off

On x

xx

x

6K2

6K2

6K2

6K2

CMOS sinking 1.6 ma

Drivers

*Example

LDAA#$F0

STAADDRC,X%1111000PC7-4ouput,PC3-0input

LDAA#$80

STAAPORTC,X%1000xxxxPC7high,PC6low

LDAAPORTC,Xvaluered%xxxxxx10



StrobedInput/Output

Relevantregisters



StrobedInput/Output

Relevantregisters

PORTCL

PORTB

PIOC

STRA

STRB

STAFSTAIHNDSEGAINVB CWOMOINPLSStro

be A flag

Strobe A In

terrupt E

nable

Port C wire

d Mode

Handshake/Simple Strobe Select

Output/Input H

andshake

Select

Strobe B Pulse

Mode Select

Edge Select for S

trobe A

Invert S

trobe B



StrobedInput/Output

Asampleprogram



StrobedInput/Output

Asampleprogram

*TheMCreceivesdatasentbyaperipheral(onSTRAedge)and

echoesthemback(STRBlowfortwoclockcycles)

ORG$C000startaddress

LDY#DPTRYpointstodatatobereceived

BSETPIOC,X$40enableSTRAinterrupt

CLIclearinterruptmask(Ibit)

RPTWAIwaitforinterrupt

*fromfallingedgeSTRAinput

STAA0,Ysavereceiveddata

STAAPORTB,Xechoback

INY

...

BRARPT



StrobedInput/Output(cont.)

%Interruptserviceroutine

SIO_ISRLDAAPIOC,Xtheinstructionspair

LDAAPORTCL,XclearSTAF

RTI



FullOutputHandshake



FullOutputHandshake

68HC11

PORTC

Peripheral device

STRA

STRB

Data

Ready

Ack

deasserted by STRA

Writing to PORTCL(i )Assert STRB

STRA (i) Deassert STRB(i) Set STAF

Strobed

Interlocked



FullInputHandshake



FullInputHandshake

68HC11

PORTCL

Peripheral device

STRA

STRB

Data

Send

Data read

deasserted by STRA

STRA (i )Data latched(ii)Set STAF(iii)Deassert STRB

Reading Port C(i) Assert STRB

Strobed

Interlocked



AnInputHandshakeProgram

INIT_HNDSIN_HNDS

PSHA*UsesinputhandshaketoreadportC;

*strobemodefirst*pollsforSTRAtransitionsBCLRPIOC,X,$10BRCLRPIOC,X,\$80INHNDS

*clearSTAFifset*InputsstrobeddataandclearSTAF

LDAAPIOC,XLDAAPORTCL,X

LDAAPORTCL,XRTS

*PortCInput*-----------------------------------

LDAA\#\$00RDDATA

STAADDRC,X*Readdatafromperipheral

*InputHandshakeModeJSRINIT_HNDS

LDAA#$10JSRIN_HNDS

STAAPIOC,X%HNDS1...

PULABRARPT

RTSRTS



SerialCommunicationInterface




◦Asynchronouscommunicationwithremotedevices





◦InterfacingstandardRS232(orEIA232A)






Thestandarddefines






Thestandarddefinessignallevels,






Thestandarddefinessignallevels,connectors,






Thestandarddefinessignallevels,connectors,andpinassignment







◦Onetransmittermanyreceivers








◦Thebasicunitofinformationisthecharacterordataframe








◦Thebasicunitofinformationisthecharacterordataframe

◦Baudratedefinesthenumberofbits(includingstart,stopandparitybits)persecond



SCI(cont.)

TxD

RxD

DTEDCE

SG

TxD

RxDSG

DTE DCE

2/BA

3/BB

7/AB

3

2

7

Tx1

Rx1

TxD

RxDPD1

PD0

RxD

TxDSG

DB25Sconnector MC144507

68HC11

DI1

D01

(a)(b)

Figure2:(a)NullMODEMand(b)RS232DCE(MCinterface)



TransmissioninSCIsystem

T8

R8

TDR Buffer

Shift Register

Shift Register

TDRE

RDRF RDR Buffer

Data from MCU

Data in

Data out

Data to MCU

TRANSMITTER

RECEIVER

1

1

STARTSTOP

PARITY IDLE

BREAK

01234567

Framing



SCIregistersandcontrolbits

BAUD

SCCR1

SCCR2

SCSR

SCDR

TCLR0SCP1SCP2RCKBSCR2SCR1SCR0

R8T8

0

0MWAKE0 00

TIETCIERIEILIETERERWUSBK

TDRETCRDRFIDLEORNFFE

R7R6R5R4R3R2R1R0T T6 T5 T4 T3 2T T1 T0 7

prescalerrate select

Mode 8/9 bitsIdle line/ address mark

Sent break

receiver wake up

control

Transfer completeIddle line

Transmit enable

Receiver enable

R,T eight bit

emptycompletefull

iddle line

overrun erro

r

noise erro

r

framing erro

r

interrupt(s) enable



UsingSCI

INITSCIINSCI

LDAA#$309600baudLDAASCCRReadstatusregister

STAABAUDbaudregisterANDA#$20CheckRDRF

LDAA#$00BEQINSCIWaitfordata

STAASCCR11start,8bits,1stopLDAASCDATReaddata

LDAA#$0CANDA#$7FMaskparity

STAASCCR2transmitterreceiverenableRTS

RTS

OUTSCI

LDABSCCRReadstatusregister

BITB#$80CheckTDRE

BEQOUTSCILoopuntilTDRE=1

ANDA#$7FMaskparity

STAASCDATSendcharacter

RTS



Protocols

CRC Data block

Simplex

CRC Data block

ACK/NAK

(XON/XOF)

Half duplex

(a)(b)

CRC Data block CRC Ack block

CRC Ack blockCRC Data block

Duplex

(c)



SPIbasics



SPIbasics

data registerdata register

shift registershift registerMOSI

MISO

MasterSlave

VDD

SSSS

SCKSCK



ICthatusesynchronousserialinterface

◦PLLfrequencysynthesizers(MC145156)

◦Seven-segmentsdisplaydecoders/drivers(MC14499)

◦LCDdisplaydecoders/drivers(MC145453)

◦ADC(MC145041)

◦DAC(MC144110,DAC-8840)

◦Shiftregisters(74HC589,74HC595)

◦Realtimeclocks(MC68HC68T1)

◦ISDNtransceivers

◦SerialRAMchip(DS1200),etc.



SPITopologies



SPITopologies��

��

��

��

��

��

��

��

��

��

��

��

��

��

Bus topology

Cascade topology

��

��

��

��

��

��

��

��

��

MOSISCK

MISO

SCK

MOSI MISO



SPIBustopology



SPIBustopology

MISOMOSI

SCK

SS

SS_1

SS_2

SSSS

MISO

MOSI

SCK

MISO

MOSI

MOSI

+5v

PD2

PD3

PD4

PD5

from other port



SPICascadetopology



SPICascadetopology

MISOMOSI

SCK

SS

SI

SS

SO

Slave 1

SI

SCKSS

SO

Slave 2

SCK

+5v



SPIOperations

Master

iWriteabytetodataregisterSPDR(SSpreviouslyassertedlow)

iiWaitforSPIFtobeset(deassertslaveSShigh)

iiireadabytefromSPDR

Slave

iwriteabytetoSPDR

iiWaitforSPIFtobeset

iiiReadsabytefromdataregisterSPDR



MasterSPIOperations:Example

DemonstratesSPIbyteoutputandinput(slavealwaysenabled)

DATAEQU0

ORG$4000

LDX#$1000

LDAA#$38enableSPIoutputs

STAADDRD,XPD5general-purposeoutput

LDAA#$57

STAASPCR,XSPImaster

CPHA=1,CPOL=0,clockrate1/32

LDAADATAgetsomedata

STAASPDR,Xandtransmitit

POLL

TSTSPSR,Xwaitfortransfercomplete

BPLPOLLbranchifplus(SPIFbit0)

LDAASPDR,Xgetdatafromtheslave

(alsoclearsSPIF)

DONEBRADONE



SlaveSPIOperations:Example

DemonstratesSPIbyteoutputandinput(slavealwaysenabled)

DATAEQU0

ORG$4000

LDX#$1000

LDAA#$04EnableMISOoutput

STAADDRD,Xothersforcedasinputs

LDAA#$47

STAASPCR,XSPIslave,CPHA=1,CPOL=0,

Clockratedon’tcare

LDAADATAGetsomedata

STAASPDR,Xandsendtodataregister

POLLWaitformasterclocktoshift

itoutandmaster’sdatein

TSTSPSR,Xwaitfortransfercomplete

PBLPOLLuntilmastertransfercomplete

LDAASPDR,Xgetdatafromtheslave

(alsoclearsSPIF)

DONEBRADONE



SummaryofFeatures

◦CentralProcessingUnit(CPU)

–Upto5/3Mhz(5/3V)

–Two8-bitandone16bitaccumulator

–Two16-bitindexregisters

–16-bitstackpointer

–(Powerful)bit-manipulationinstructions

–Six(powerful)addressingmodes

–Memory-mappedI/Oandspecialfunctions

–16x16integerandfractionaldivide

–8x8multiply

–Power-savingstopandwaitmodes

◦EEPROM

–On-chipbyte-erasableEEPROM



–Noseparatevoltagerequired



◦ExpandedBusmemoryinterface

–64KBaddressingspace

–(Some68HC11s)Upto1MBaddressingspace

–Eithermultiplexedornon-multiplexedinterfaces

◦SerialCommunicationInterface(SCI)9

–Standardmark/spacenon-returntozeroformat

–Fullduplexoperation

–Doublebufferingofbothreceiverandtransmitter

–Programmable8-bitor9-bitcharacterlength

–Errordetection—at1/126ofabittime

–Baudrategeneratorwithprogrammablebaudrate

–Idlelineandaddressmarkwakeupmethods

–Receiverframingerrordetection

–Breaksendcapability

–Optionalparitycheckingandgeneration

–Separatetransmitter,receiveranderrorinterruptvectors9usedforasynchronouscommunicationwithaterminal,computerormicrocontrollernetworkoverlongdistance(RS-232)



◦SerialPeripheralInterface(SPI10

)

–Fullduplex,threewiresynchronoustransfers

–Masterorslaveoperation

–BitfrequencyisE/2(Master)E/1(Slave)

–Fourprogrammablemasterbit-rates

–Programmableclockpolarityandphase

–Endoftransitioninterruptflag

◦Lower-PowerOperation

–Lowpowerforvoltages(3–5V)

–Phase-lockedloop(PLL)clocksynthesizercircuit11

◦HighPerformanceTimer

–Freerunning16bitcounter

–Programmableprescaler10usedforsynchronouscommunicationwithperipheraldevicesovershortdistances(usuallyonasinglePCB)suchasshift

register,serialEEPROM,LCDorADCsubsystems11PLLreducestheclockspeed



–Overflowinterrupt

–Separatefunctioninterrupts



◦AdditionalFeatures

–Multipleinputcaptureandoutputcomparefunctions

–Real-timeinterrupts

–ComputerOperatingProperlyWatchdog(COP)

–Pulseaccumulatorforexternaleventcountingorgatedaccumulations

–OptionalPWM12

–Optionaleventcountersystemforadvancetimingoperation

◦AnalogtodigitalConverter(ADC)

–Linearsuccessiveapproximation

–8-bitor10-bitresolution

–Singleorcontinuousconversionmodes

–Multipleresultregisters

–SelectableADCclock

–Analogmutiplexer13

12offeringuptosixchannelsandupto16-bitPWM13allowsvariablenumberofchannelswithasingleADC



◦Pulse-widthmodulation

–UptosixPWMchannels14

–Softwareselectabledutycycles(from0–100%)

14whichcancreatecontinuouswaveformswithprogrammablerates


svenk/mikrodatorsystem/HC11/... · The MC68HC11 MICROCONTROLLER Applications of Microcontrollers...

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Transcript of svenk/mikrodatorsystem/HC11/... · The MC68HC11 MICROCONTROLLER Applications of Microcontrollers...